Explanation Of Watchdog Timer Operations And Setup Procedure Example - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 11 WATCHDOG TIMER
11.4 Explanation of Watchdog Timer Operations and Setup
Procedure Example
The watchdog timer generates a watchdog reset when the watchdog timer counter
overflows.
Operations of Watchdog Timer
How to activate the watchdog timer
• The timer of the watchdog timer is activated when "0101
watchdog timer control register (WDTC:WTE3 to WTE0) for the first time after a reset. The count
clock switch bits of the watchdog timer control register (WDTC:CS1,0) should also be set at the same
time.
• Once the watchdog timer is activated, a reset is the only way to stop its operation.
Clearing the watchdog timer
• When the counter of the watchdog timer is not cleared within the interval time, it overflows, allowing
the watchdog timer to generate a watchdog reset.
• The counter of the watchdog timer is cleared when "0101
watchdog timer control register (WDTC:WTE3 to WTE0) for the second or any succeeding time.
• The watchdog timer is cleared at the same time as the timer selected as the count clock (timebase timer
or watch prescaler) is cleared.
Operation in standby mode
Regardless of the clock mode selected, the watchdog timer clears its counter and stops the operation when
entering a standby mode (sleep/stop/timebase timer/watch).
Once released from the standby mode, the timer restarts the operation.
Note:
The watchdog timer is also cleared when the timer selected as the count clock (timebase timer or
watch prescaler) is cleared.
For this reason, the watchdog timer cannot function as such, if the software is set to clear the
selected timer repeatedly during the interval time of the watchdog timer.
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" is written to the watchdog control bits of the
B
" is written to the watchdog control bits of the
B