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External Status Lines (10 lines, ESL, A)
These lines are used to test various conditions in a buffer unit. The condition tested by each
line depends on the particular buffer unit.
The conditions are listed under "Buffer Selector
Instructions" as the NES instructions.
Buffer Address Decode (128, N)
This unit decodes the C-register into a 1 out of 128 signal to select the desired buffer address.
THE CONTROLLER SELECTOR
Data Register (21 bits, no abb., N)
The controller selector data register contains the data being transferred between the controller
selector and the DATANET-30.
Address Register (14 bits, no abb., N)
The controller selector address register contains the address of the next memory location
to be accessed by the controller selector.
PARITY NETWORKS (21 bits, no abb., A)
Although not shown on the block diagram, the parity networks are attached to the B-register
and consist of a word parity network and a character parity network.
There are two outputs from the parity network, one for character parity and one for word parity.
Either output may be tested to check incoming data. The appropriate output is automatically
sent to a buffer unit when information is transmitted.
The input to the word parity network consists of the 18 bits of the B-register and the control
bit 1 and control bit 2 flip-flops.
The output of the word parity network is bit 21 and is used
with the word buffer channel and CIU.
The inputs to the character parity network are bits
1-6 of the B-register and the control bit 1 and 3 flip-flops. The character parity is used almost
exclusively for generating correct parity on 8-level teletype characters. Each time a word
. is brought into the B-register, the word parity network will generate correct parity on it. At
the same time, proper character parity will be generated on bits 1-6 of the B-register.
CONTROL BITS 1, 2 and 3
The control bits are special-purpose flip-flops and are used as needed. Since there are 21
receive data lines and the registers are 18-bit registers, the receive data lines 19, 20, and
21 go to control bits 1, 2, and 3, respectively. Control bit 3 is also referred to as the "parity
bit." The following chart shows the instructions and conditions affecting the control bits.
[IDruu&~~uc:J ~@------------
I-15
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