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W632GU6NB Series
User Manuals: Winbond W632GU6NB Series SDRAM Specialty
Manuals and User Guides for Winbond W632GU6NB Series SDRAM Specialty. We have
1
Winbond W632GU6NB Series SDRAM Specialty manual available for free PDF download: General Description Manual
Winbond W632GU6NB Series General Description Manual (162 pages)
16M x 8 BANKS x 16 BIT DDR3L SDRAM
Brand:
Winbond
| Category:
Storage
| Size: 4 MB
Table of Contents
Table of Contents
1
1 General Description
5
2 Features
5
3 Order Information
6
4 Key Parameters
7
5 Ball Configuration
9
6 Ball Description
10
7 Block Diagram
12
8 Functional Description
13
Basic Functionality
13
RESET and Initialization Procedure
13
Power-Up Initialization Sequence
13
Reset Initialization with Stable Power
15
Programming the Mode Registers
16
Mode Register MR0
18
Burst Length, Type and Order
19
CAS Latency
19
Test Mode
20
DLL Reset
20
Write Recovery
20
Precharge PD DLL
20
Mode Register MR1
21
DLL Enable/Disable
21
Output Driver Impedance Control
22
ODT RTT Values
22
Additive Latency (AL)
22
Write Leveling
22
Output Disable
22
Mode Register MR2
23
Partial Array Self Refresh (PASR)
24
CAS Write Latency (CWL)
24
Auto Self Refresh (ASR) and Self Refresh Temperature (SRT)
24
Dynamic ODT (Rtt_Wr)
24
Mode Register MR3
25
Multi Purpose Register (MPR)
25
No Operation (NOP) Command
26
Deselect Command
26
DLL-Off Mode
26
DLL On/Off Switching Procedure
27
DLL "On" to DLL "Off" Procedure
27
DLL "Off" to DLL "On" Procedure
28
Input Clock Frequency Change
29
Frequency Change During Self-Refresh
29
Frequency Change During Precharge Power-Down
29
Write Leveling
31
DRAM Setting for Write Leveling & DRAM Termination Function in that Mode
32
Write Leveling Procedure
32
Write Leveling Mode Exit
34
Multi Purpose Register
35
MPR Functional Description
36
MPR Register Address Definition
37
Relevant Timing Parameters
37
Protocol Example
37
ACTIVE Command
43
PRECHARGE Command
43
READ Operation
44
READ Burst Operation
44
READ Timing Definitions
45
READ Timing; Clock to Data Strobe Relationship
46
READ Timing; Data Strobe to Data Relationship
47
Tlz(Dqs), Tlz(DQ), Thz(DQS), Thz(DQ) Calculation
48
Trpre Calculation
49
Trpst Calculation
49
Burst Read Operation Followed by a Precharge
55
WRITE Operation
57
DDR3L Burst Operation
57
WRITE Timing Violations
57
Motivation
57
Data Setup and Hold Violations
57
Strobe to Strobe and Strobe to Clock Violations
57
Write Timing Parameters
57
Write Data Mask
58
Twpre Calculation
59
Twpst Calculation
59
Refresh Command
66
Self-Refresh Operation
68
Power-Down Modes
70
Power-Down Entry and Exit
70
Power-Down Clarifications - Case 1
76
Power-Down Clarifications - Case 2
76
Power-Down Clarifications - Case 3
77
ZQ Calibration Commands
78
ZQ Calibration Description
78
ZQ Calibration Timing
79
ZQ External Resistor Value, Tolerance, and Capacitive Loading
79
On-Die Termination (ODT)
80
ODT Mode Register and ODT Truth Table
80
Synchronous ODT Mode
81
ODT Latency and Posted ODT
81
Timing Parameters
81
ODT During Reads
83
Dynamic ODT
84
Functional Description
84
ODT Timing Diagrams
85
Asynchronous ODT Mode
89
Synchronous to Asynchronous ODT Mode Transitions
90
Synchronous to Asynchronous ODT Mode Transition During Power-Down Entry
90
Asynchronous to Synchronous ODT Mode Transition During Power-Down Exit
93
Asynchronous to Synchronous ODT Mode During Short CKE High and Short CKE Low Periods
94
9 Operation Mode
95
Command Truth Table
95
CKE Truth Table
97
Simplified State Diagram
98
10 Electrical Characteristics
99
Absolute Maximum Ratings
99
Operating Temperature Condition
99
DC & AC Operating Conditions
99
Recommended DC Operating Conditions
99
Input and Output Leakage Currents
100
Interface Test Conditions
100
DC and AC Input Measurement Levels
101
DC and AC Input Levels for Single-Ended Command and Address Signals
101
DC and AC Input Levels for Single-Ended Data Signals
101
Differential Swing Requirements for Clock (CK - CK#) and Strobe (DQS - DQS#)
103
Single-Ended Requirements for Differential Signals
104
Differential Input Cross Point Voltage
105
Slew Rate Definitions for Single-Ended Input Signals
106
Slew Rate Definitions for Differential Input Signals
106
DC and AC Output Measurement Levels
107
Output Slew Rate Definition and Requirements
107
Single Ended Output Slew Rate
108
Differential Output Slew Rate
109
Output Driver DC Electrical Characteristics
110
Output Driver Temperature and Voltage Sensitivity
112
On-Die Termination (ODT) Levels and Characteristics
113
ODT Levels and I-V Characteristics
113
ODT DC Electrical Characteristics
114
ODT Temperature and Voltage Sensitivity
114
Design Guide Lines for RTT PU and RTT PD
115
ODT Timing Definitions
116
Test Load for ODT Timings
116
Input/Output Capacitance
120
Overshoot and Undershoot Specifications
121
AC Overshoot /Undershoot Specification for Address and Control Pins
121
AC Overshoot /Undershoot Specification for Clock, Data, Strobe and Mask Pins
121
IDD and IDDQ Specification Parameters and Test Conditions
122
IDD and IDDQ Measurement Conditions
122
IDD Current Specifications
132
Clock Specification
133
Speed Bins
134
DDR3L-1333 Speed bin and Operating Conditions
134
DDR3L-1600 Speed bin and Operating Conditions
135
DDR3L-1866 Speed bin and Operating Conditions
136
DDR3L-2133 Speed bin and Operating Conditions
137
Speed bin General Notes
138
AC Characteristics
139
AC Timing and Operating Condition for -09/09I/09J/-11/11I/11J Speed Grades
139
AC Timing and Operating Condition for -12/12I/12J/-15/15I/15J Speed Grades
143
Timing Parameter Notes
147
Address / Command Setup, Hold and Derating
150
Data Setup, Hold and Slew Rate Derating
157
11 Backward Compatible to 1.5V DDR3 SDRAM VDD/VDDQ Requirements
159
Input/Output Functional
159
Recommended DC Operating Conditions - DDR3L (1.35V) Operation
159
Recommended DC Operating Conditions - DDR3 (1.5V) Operation
159
VDD/VDDQ Voltage Switch between DDR3L and DDR3
159
12 Package Specification
161
13 Revision History
162
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