Tundra TSI308 Manuals

Manuals and User Guides for Tundra TSI308. We have 1 Tundra TSI308 manual available for free PDF download: User Manual

Tundra TSI308 User Manual

Tundra TSI308 User Manual (260 pages)

HyperTransport-to-PCI-X Bridge

Brand: Tundra | Category: Network Hardware | Size: 2 MB

Table of Contents

Table of Contents

7
- Contact Information
  
  3
- Corporate Profile
  
  5
  - Table of Contents
    7
List of Figures

13
- About this Document
  
  17
  - Scope
    17
  - Document Conventions
    17
  - Related Information
    19
  - Revision History
    19
- 1 Functional Description
  
  21
  - Overview
    22
  - Figure 1: Tsi308 Block Diagram
    22
  - Features
    23
    
    General Features
    23
  - Hypertransport Interface
    24
  - PCI-X Interface
    25
    
    PCI-X Master
    25
    
    PCI-X Arbiter
    26
    
    PCI-X Slave
    26
  - Interrupt Controller
    27
  - Interface Levels
    27
  - Table 1: Hypertransport PCI-X Bridge Interface Voltages
    27
  - Clocking
    28
  - Reset
    28
- 2 Interface Operation
  
  29
  - Figure 2: Block Diagram
    30
    
    Figure 3: Single Hypertransport Link Interface Block Diagram
    31
    
    Hypertransport Interface
    31
    
    Hypertransport Packet Reception
    32
    
    Table 2: Hypertransport Ordering
    34
    
    Hypertransport Address Map
    35
    
    Table 3: PCI Bus Transaction Ordering
    35
    
    Table 4: PCI-X Bus Transaction Ordering
    35
    
    Hypertransport Address Remap
    37
    
    Hypertransport Packet Transmission
    37
    
    Outbound Transactions
    38
    
    PCI-X Outbound Transactions
    39
    
    Inbound Transactions
    40
    
    PCI-X Address Map
    40
    
    PCI-X Delayed/Split Request Buffers
    41
    
    PCI-X Posted Write Queue
    41
    
    Memory Read Block (PCI-X Mode Only)
    42
    
    Prefetching (PCI Mode Only)
    42
    
    Read Responses
    43
    
    Sequences
    43
    
    Srctags
    43
    
    Continuous Prefetching (PCI Mode Only)
    44
    
    Interrupt Generation
    44
    
    Outbound Data Buffer
    44
    
    Transaction Disconnects
    44
    
    PCI-X Arbiter
    45
    
    LDTSTOP# Support
    46
    
    Online Insertion and Removal (OIR)
    46
    
    Cold Reset
    47
    
    Hypertransport Link Initialization
    47
    
    Power Management
    47
    
    Reset
    47
    
    Reset Configuration
    47
    
    Warm Reset
    47
    
    Hypertransport Fabric Initialization
    48
    
    Error Handling
    49
    
    Reporting
    49
    
    Secondary Bus Reset
    49
    
    Hypertransport Errors
    50
    
    Table 5: Hypertransport Link Error CSR Bits
    51
    
    Table 6: Hypertransport Forwarding Error CSR Bits
    51
    
    PCI Errors
    53
    
    Table 7: Hypertransport Master Errors CSR Bits
    53
    
    Table 8: PCI System Error CSR Bits
    54
    
    Table 9: PCI Master Errors CSR Bits
    54
    
    Jtag
    56
    
    Table 10: PCI Parity Errors CSR Bits
    56
    
    Test Features
    56
    
    Table 11: Boundary Scan Chain Order
    58
    
    SCAN and ATPG
    68
    
    Table 12: Scan Input and Output Pins
    68
- 3 Clock Frequency and Mode Selection Hardware Straps
  
  71
- 4 Register Descriptions
  
  81
  - Configuration Registers
    82
    
    Figure 5: Single Tsi301 Mode
    82
    
    Operating Modes
    82
    
    Figure 6: Dual Tsi301 Mode
    83
    
    Configuration Mechanism
    84
    
    Figure 7: Tsi308 Single PCI-X Mode
    84
    
    Figure 8: Tsi308 Dual PCI-X Mode
    84
  - Summary of Configuration Registers
    85
    
    Mode Encodings
    85
    
    Register Access Definitions
    85
    
    Register Access Rules
    85
    
    CSR Layout
    86
    
    Table 20: Tsi308 CSR Header
    86
  - 64-Bit Address Remapping Capability Indices
    89
    
    ISOC Bit Setting
    89
    
    Table 21: 64-Bit Address Remap Indexed Registers
    89
    
    Read Control 2 Register
    90
    
    Interrupt Definition Registers
    91
    
    Table 22: Interrupt Definition Registers
    91
    
    SRI Indices
    93
    
    Tsi308 Registers
    97
    
    CSR Layout for IOAPIC
    181
    
    IOAPIC Registers
    183
- 5 Electrical Characteristics
  
  189
  - AC Timing Definitions
    190
  - Figure 9: Timing Definitions Waveform
    190
  - Table 23: AC Timing Definitions
    190
    
    AC Timing Values
    191
    
    Table 24: Typical AC Timing Values
    191
  - Clock Parameters
    193
    
    Figure 10: Input Clock Parameters Waveform
    193
    
    Input Clock
    193
    
    Table 25: Input Clock Parameters
    193
  - Hypertransport Output Timing Characteristics
    194
    
    Differential Output Skew
    194
    
    Figure 11: TODIFF
    194
    
    Figure 12: TCADV
    195
    
    TCADV (Tcadvalid)
    195
  - Hypertransport Input Timing Characteristics
    196
    
    Figure 13: TIDIFF
    196
    
    Input Differential Skew
    196
    
    Figure 14: TSU and THD
    197
    
    TSU and THD
    197
  - Hypertransport Interconnect Timing Characteristics
    198
    
    Figure 15: TCADVRS / TCADVRH
    198
    
    Tcadvrs/Rh
    198
  - Hypertransport Transfer Timing Characteristics
    199
  - Table 26: Hypertransport Link Transfer Timing Specifications
    199
  - Hypertransport Impedance Requirements
    201
  - Table 27: RTT and RON DC Specifications
    201
  - Hypertransport Signal AC Specifications
    202
  - Figure 16: Output Loading for AC Timing
    202
  - Table 28: Hypertransport Link Differential Signal AC Specifications
    202
  - Hypertransport DC Electrical Characteristics
    203
  - Figure 17: Output Reference System Load
    203
  - Table 29: HT Link Differential Signal DC Specifications
    203
  - Reset Timing
    204
  - Figure 18: Tsi308 Reset Timing
    205
  - Power Consumption
    206
  - Table 30: Recommended Operating Temperature
    206
  - Table 31: Thermal Maximum
    206
  - Table 32: Thermal Characteristics
    206
  - Figure 19: Recommended Heat Sink for Tsi308
    207
  - Thermal Recommendations
    207
  - Table 33: Supply Operating Ranges
    208
  - Table 34: Absolute Maximum Ratings
    208
  - Power Sequencing
    208
- 6 Packaging
  
  209
  - Table 35: Tsi308 Sorted by Name
    210
    
    Package Specification
    210
    
    Pins Sorted by Number
    221
    
    Table 36: Tsi308 Sorted by Number
    221
    
    Table 37: Tsi308 Multiplexed Pins
    232
    
    Table 38: Tsi308 +1.2V Hypertransport Power
    232
    
    Table 39: Tsi308 +1.8V Core Power
    233
    
    Table 40: Tsi308 1.8V Analog PLL Power and Ground
    234
    
    Table 41: Tsi308 +3.3V PCI Core and I/O Power and HT Receive Power
    234
    
    Table 42: Tsi308 Ground Pins
    236
    
    Package Diagram
    238
- 7 Online Insertion and Removal
  
  239
  - Figure 20: OIR Sequence
    240
- 8 Typical Applications
  
  241
  - Figure 21: Terminating Unused HT CAD Inputs
    242
  - Figure 22: Recommended PLL Power Filtering
    242
    
    Decoupling Capacitor Recommendations
    243
    
    Layout Guidelines
    246
    
    Table 43: System Board Design Rules
    247
    
    Power Distribution
    250
    
    Decoupling
    251
    
    Table 44: Pad-To-Ball Trace Length Information
    252
    
    Example PCB Stackup for Hypertransport
    255
    
    Figure 23: PCB Stackup for Hypertransport
    256
    
    Table 45: Ordering Information
    257
    
    Index
    259

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