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TMS 440 SH-3 7708
Tektronix TMS 440 SH-3 7708 Manuals
Manuals and User Guides for Tektronix TMS 440 SH-3 7708. We have
1
Tektronix TMS 440 SH-3 7708 manual available for free PDF download: Instruction Manual
Tektronix TMS 440 SH-3 7708 Instruction Manual (100 pages)
Brand:
Tektronix
| Category:
Computer Hardware
| Size: 0.63 MB
Table of Contents
Table of Contents
5
General Safety Summary
9
Service Safety Summary
11
Preface
13
Manual Conventions
13
Logic Analyzer Documentation
14
Contacting Tektronix
14
Getting Started
15
Support Package Description
17
Logic Analyzer Software Compatibility
18
Logic Analyzer Configuration
18
Requirements and Restrictions
18
Configuring the Probe Adapter
20
Connecting to a System under Test with a Probe Adapter
20
Figure 1-1: Jumper Locations on the Probe Adapter
20
Connect the P6434 Probes to the Probe Adapter
21
Figure 1-2: Connecting Probes to a Probe Adapter
21
Connect the Test Clip to the Probe Adapter
22
Connect the Probe Adapter Assembly to the System under Test
22
Figure 1-3: Seating the Test Clip on the Probe Adapter
22
Figure 1-4: Placing the Probe Adapter Assembly Onto the SUT
23
Removing the Probe Adapter from the SUT
24
Connecting to a System under Test Without a Probe Adapter
24
Applying and Removing Power
25
Figure 1-5: Location of the Power Jack
25
Functionality Not Supported
26
Channel Assignments
26
Table 1-1: Address Channel Group Assignments
26
Table 1-2: Data Channel Group Assignments
28
Table 1-3: Control Channel Group Assignments
29
Table 1-4: Chip_Sel Channel Group Assignments
29
Table 1-5: Control2 Channel Group Assignments
30
Table 1-6: WEN Channel Group Assignments
30
Table 1-7: Misc Channel Group Assignments
30
Table 1-8: Signals that Are on the Probe Adapter but Not Acquired
31
CPU to Mictor Connections
32
Figure 1-6: Pin Assignments for a Mictor Connector (Component Side)
32
Table 1-9: CPU to Mictor Connections for Mictor a Pins
33
Table 1-10: CPU to Mictor Connections for Mictor D Pins
34
Table 1-11: CPU to Mictor Connections for Mictor C Pins
35
Operating Basics
39
Setting up the Support
41
Channel Group Definitions
41
Clocking Options
41
Custom Clocking
41
Figure 2-1: SRAM/ROM/PCMCIA Access Bus Timing
43
Figure 2-2: DRAM Access Bus Timing
44
Figure 2-3: EDO DRAM Access Bus Timing
45
Figure 2-4: SDRAM Read Bus Timing
46
Figure 2-5: SDRAM Write Bus Timing
47
Figure 2-6: PSRAM Access Bus Timing
48
Figure 2-7: SDRAM Mode Register Write Cycles Bus Timing
49
Symbols
50
Table 2-1: Control Group Symbol Table Definitions
50
Acquiring and Viewing Disassembled Data
53
Acquiring Data
53
Viewing Disassembled Data
53
Table 2-2: Meaning of Special Characters in the Display
53
Hardware Display Format
54
Table 2-3: Cycle Type Definitions
54
Software Display Format
55
Control Flow Display Format
55
Figure 2-8: Hardware Display Format
55
Subroutine Display Format
56
Changing How Data Is Displayed
56
Optional Display Selections
56
Marking Cycles
58
Displaying Exception Vectors
59
Viewing an Example of Disassembled Data
59
Table 2-4: Exception Vectors for Addressing Mode
59
Table 3-1: Electrical Specifications
63
Table 3-2: Environmental Specifications
65
Figure 3-1: Dimensions of the Probe Adapter
66
Figure 4-1: Location of the Fuse
72
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