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generatorNETBOX DN6.65 Series
Spectrum generatorNETBOX DN6.65 Series Manuals
Manuals and User Guides for Spectrum generatorNETBOX DN6.65 Series. We have
1
Spectrum generatorNETBOX DN6.65 Series manual available for free PDF download: Hardware Manual
Spectrum generatorNETBOX DN6.65 Series Hardware Manual (184 pages)
Ethernet/LXI remote waveform generator
Brand:
Spectrum
| Category:
Computer Hardware
| Size: 8.88 MB
Table of Contents
Table of Contents
3
General Safety at Work
9
Table 1: Symbols and Safety Labels
9
Safety Instructions
9
Requirements for Users and Duties for Operators
9
General Safety Information
9
Symbols and Safety Labels
9
Electrical Safety and Power Supply
10
Bringing the Product into Service
10
Requirements on the Ventilation
10
Requirements for the Location
10
Maintenance
10
Requirements for Operation
10
Requirements for the Technical State of the Product
10
Application Area of the Product
10
Intended Use
10
Repair/Service
11
Cleaning the Module Housing (NETBOX Devices, Cables, Amplifiers, Systems Only)
11
Opening the Module (NETBOX Devices, Amplifiers Only)
11
Dismounting Parts of the Card (Instrument Card Only)
11
Markings and Labelling
11
Packing List
12
Table 2: Packing List
12
Generatornetbox Overview
13
Image 1: Example of Generatornetbox
13
Introduction
13
General Information
13
Preface
13
Internal Generator Modules
14
Differences between Plain Cards and Generator Modules Inside the Generatornetbox
14
Overview of Generator Modules Inside the Dn2.65X and Dn6.65X Generatornetbox
14
Table 3: Dn2.65Xx and Dn6.65Xx Overview of Internal AWG Modules
14
Different Models of the Dn2.65X Series
15
Additional Options for DN2 Products
15
19" Rack Mount Kit
15
DC Power Supply
15
Image 2: 19" Rack Mount Kit Installed on DN2 Netbox
15
Different Models of the Dn6.65X Series
16
Additional Options for DN6 Products
16
19" Rack Mount Kit
16
Image 3: 19" NETBOX DN6 with Installed 19" Mounting Handles
16
AC Cable Options
17
The Spectrum Type Plate
18
Image 4: Spectrum Type Plate with All Information Found There
18
Hardware Information
19
Block Diagram of Generatornetbox Dn2.65X and Dn6.65X
19
Block Diagram of a Single Internal Generator Module
19
Image 5: Block Diagram of Internal Structure Showing Wiring of Auxiliary Signals
19
Image 6: Block Diagram of Internal AWG Module
19
DN2 / DN6 Technical Data
20
DN2 Specific Technical Data
25
DN6 Specific Technical Data
25
DN2 Order Information
26
DN6 Order Information
27
Cooling Precautions
28
Image 8: Airflow in DN6 Chassis
28
Sources of Noise
28
Image 7: Airflow in DN2 Chassis
28
Opening the Chassis
28
Warnings
28
Hardware Installation
28
ESD Precautions
28
Installing 19" Rack Mount Option for DN2
29
Installing 19" Rack Mount Option for DN6
29
Image 9: Un-Mounting the Bumper Feet to Prepare For19" Rack-Mount Kit
29
Image 10: Mounting the 19" Rack-Mount Kit to a DN2 Chassis
29
Image 11: Mounting the 19" Rack-Mount Kit to a DN6 Chassis
29
Image 12: Location of Connectors and Labels on the Back-Side of a DN2 Chassis
30
Table 4: Connector and Label Description on Back-Side of DN2 Chassis
30
Connections
30
Back Side DN2
30
Setup of Digitizernetbox/Generatornetbox
30
Front Panel DN2 Digitizernetbox/Generatornetbox
31
Image 13: Location of Connectors on a Front-Panel of a DN2 Chassis
31
Table 5: Connector and LED Description on Front-Side of DN6 Chassis
31
Front Panel DN2 Hybridnetbox Dn2.80X and Dn2.81X
32
Image 14: Location of Connectors on a Front-Panel of a DN2 Chassis
32
Table 6: Connector and LED Description on Front-Side of DN2 Chassis
32
Table 8: Connector and LED Description on Front-Side of DN2 Chassis
33
Front Panel DN2 Hybridnetbox Dn2.82X
33
Table 7: Location of Connectors on a Front-Panel of a DN2 Chassis
33
Table 9: Connector and LED Description on Front-Side of DN6 Chassis
34
Front Panel DN6 Digitizernetbox or Generatornetbox
34
Image 15: Location of Connectors on a Front-Panel of a DN6 Chassis
34
Ethernet Default Settings
34
Detecting the Digitizernetbox/Generatornetbox/Hybridnetbox
35
Discovery Function
35
Finding the Digitizernetbox/Generatornetbox/Hybridnetbox in the Network
35
Troubleshooting
36
Image 16: Windows Screenshot: Finding a Remote Spectrum Device Like Digitizernetbox
36
Software Driver Installation
37
Required Software for Operation
37
Location
37
Linux
38
Overview
38
Driver Installation with Installation Script
38
Update of a Self Compiled Kernel Driver
39
Compilation of Kernel Driver Sources (Optional and Local Cards Only)
39
Standard Driver Update
39
Installation from Spectrum Repository
40
Installing the Library Only Without a Kernel (for Remote Devices)
40
Image 17: Device Manager Showing a New Spectrum Card
41
Control Center
41
Image 18: Spectrum Kernel Driver, API Library and Software Structure
42
Image 19: Spectrum Control Center Installer
42
Card Control Center
42
Software Overview
42
Software
42
Wake on LAN of Digitizernetbox/Generatornetbox/Hybridnetbox
43
Image 20: Spectrum Control Center Showing Detail Card Information
43
Image 21: Spectrum Control Center - Entering an IP Address for a NETBOX
43
Image 22: Spectrum Control Center: Wake on LAN for a Cached Card
43
Discovery of Remote Cards, Digitizernetbox/Generatornetbox/Hybridnetbox Products
43
Netbox Monitor
44
Device Identification
44
Image 23: Netbox Monitor Activation
44
Image 25: Spectrum Control Center - Showing Firmware Information of an Installed Card
45
Hardware Information
45
Image 24: Spectrum Control Center: Detailed Hardware Information on Installed Card
45
Firmware Information
45
Software License Information
46
Driver Information
46
Image 26: Spectrum Control Center - Showing Firmware Information of an Installed Card
46
Image 27: Spectrum Control Center - Showing Driver Information Details
46
Installing and Removing Demo Cards
47
Feature Upgrade
47
Software License Upgrade
47
Performing Card Calibration (A/D Only)
47
Image 28: Spectrum Control Center - Adding a Demo Card to the Sysstem
47
Image 29: Spectrum Control Center - Feature Update, Code Entry
47
Image 30: Spectrum Control Center - Software License Installe
47
Image 31: Spectrum Control Center - Running an On-Board Calibration
47
Image 34: Spectrum Control Center - Activate Debug Logging for Support Cases
48
Image 33: Spectrum Control Center - Running a Transfer Speed Test of One Card
48
Image 32: Spectrum Control Center - Performing Memory Test
48
Debug Logging for Support Cases
48
Performing Memory Test
48
Transfer Speed Test
48
Device Mapping
49
Accessing the Hardware with Sbench 6
49
C/C++ Driver Interface
49
Image 35: Spectrum Control Center - Using Device Mapping
49
Image 36: Sbench 6 Overview of Main Functionality with Demo Data
49
Microsoft Visual C++ 2005 and Newer 64 Bit
50
Table 10: List of C/C++ Header Files in Driver
50
General Information on Windows 64 Bit Drivers
50
Microsoft Visual C++ 6.0, 2005 and Newer 32 Bit
50
Header Files
50
Linux Gnu C/C++ 32/64 Bit
51
C++ for .NET
51
Other Windows C/C++ Compilers 32 Bit
51
Other Windows C/C++ Compilers 64 Bit
51
Driver Functions
51
Table 11: C/C++ Type Declarations for Drivers and Examples
52
Table 12: C/C++ Type Naming Convention Throughout Drivers and Examples
52
Table 13: Spectrum Driver API Functions Overview and Differentiation between 32 Bit and 64 Bit Registers
54
Delphi (Pascal) Programming Interface
56
Driver Interface
56
Examples
57
Declaration
57
NET Programming Languages
57
Library
57
Using C
58
Using Managed C++/CLI
59
Using VB.NET
59
Using J
59
Python Programming Interface and Examples
60
Driver Interface
60
Examples
61
Java Programming Interface and Examples
61
Driver Interface
61
Examples
62
Labview Driver and Examples
62
MATLAB Driver and Examples
62
Image 38: Labview Driver Oscilloscope Example
62
Image 39: Spectrum MATLAB Driver Structure
62
LAN Configuration
63
Integrated Webserver
63
Home Screen
63
Security
64
Documentation
64
Status
64
Firmware Update
65
Power
65
Downloads
65
Logging
65
Login/Logout
66
Access
66
Embedded Server
66
IVI Driver
67
About IVI
67
General Concept of the Spectrum IVI Driver
67
Image 40: General Concept of IVI Drivers for Spectrum Products. Access of Different Type of Products
67
Supported Operating Systems
68
IVI Compliance
68
Supported Digitizernetbox Families
68
Supported Generatornetbox Families
68
Supported Data Acquisition and Generation Card Families
68
Supported Spectrum Hardware
68
Ividigitizer Supported Class Capabilities
69
Supported Standard Driver Features
69
Iviscope Supported Class Capabilities
69
Ivifgen Supported Class Capabilities
70
Find more Information on IVI
70
General Information on IVI
70
IVI Getting Started Guides and Videos
70
Installation
70
Shared Components
70
Installation Procedure
70
Installer
70
Installation of the IVI Driver Package
71
Configuration Store
72
General Information
72
Repeated Capabilities
72
Programming Examples
73
Table 14: Spectrum API: Command Register and Basic Commands
73
Overview
73
Programming the Board
73
Register Tables
73
Initialization
74
Initialization of Remote Products
74
Error Handling
74
Gathering Information from the Card
75
Card Type
76
Hardware and PCB Version
76
Image 41: Available Card Type Definitions and Decimal and Hexadecimal Values
76
Table 15: Spectrum API: Card Type Register
76
Table 16: Spectrum API: Register for Hardware and PCB Versions of Standard Card
76
Table 17: Spectrum API: Registers of Hardware and PCB Version of Optional Extension Card
76
Table 18: Spectrum API: Registers of Hardware and PCB Version of Optional Digital Extension Module
76
Table 20: Spectrum API: Register Overview of Reading Current Firmware
77
Table 21: Spectrum API: Production Date Register
77
Production Date
77
Table 19: Spectrum API: Register Overview of Firmware Versions
77
Last Calibration Date (Analog Cards Only)
77
Firmware Versions
77
Serial Number
78
Installed Memory
78
Installed Features and Options
78
Table 22: Spectrum API: Calibration Date Register
78
Table 23: Spectrum API: Hardware Serial Number Register
78
Table 24: Spectrum API: Maximum Sampling Rate Register
78
Table 25: Spectrum API: Installed Memory Registers. 32 Bit Read Is Limited to a Maximum of 1 Gbyte
78
Table 26: Spectrum API: Feature Register and Available Feature Flags
78
Maximum Possible Sampling Rate
78
Miscellaneous Card Information
79
Table 27: Spectrum API: Extended Feature Register and Available Extended Feature Flags
79
Table 28: Spectrum API: Register Overview of Miscellaneous Cards Information
79
Table 30: Spectrum API: Register Driver Type Information and Possible Driver Types
80
Table 31: Spectrum API: Driver Version Read Register
80
Table 32: Spectrum API: Kernel Driver Version Read Register
80
Table 29: Spectrum API: Register Card Function Type and Possible Types
80
Used Type of Driver
80
Function Type of the Card
80
Custom Modifications
81
Reset
81
Table 33: Spectrum API: Custom Modification Register and Different Bitmasks to Split the Register in Various Hardware Parts
81
Table 34: Spectrum API: Command Register and Reset Command
81
Digitizernetbox/Generatornetbox Specific Registers
82
Table 35: Spectrum API: Digitizernetbox/Generatornetbox Specific Registers and Available Information
82
Table 36: Spectrum API: Channel Enable Register: Used to Select the Channels for the Next Acquisition/Generation
83
Channel Selection
83
Single-Ended Inputs
83
Analog Outputs
83
Setting up the Outputs
84
Output Enable
84
Image 42: Scaling the Output Swing Using the Output Amplitude Registers
84
Table 37: Spectrum API: Channel Count Register to Read Back the Number of Currently Activated Channels
84
Table 38: Spectrum API: Output Enable Register
84
Table 39: Spectrum API: Output Amplifier Register and Available Range Depending on Model
85
Table 40: Spectrum API: Output Offset Register and Available Settings Depending on Model
86
Output Offset
86
Image 43: Output Offset in Relation to Output Signal and Programmed Amplitude
86
Output Amplitude Setting and Hysteresis
86
Maximum Output Range
87
Image 44: Output Signal When Exceeding Maximum Available Output Range
87
Image 45: Output Stage with Selectable Filters
87
Table 41: Spectrum API: Output Filter Register and Available Register Settings
87
Table 42: 65Xx Standard Output Filter Frequencies
87
Output Filters
87
Differential Output
88
Image 46: Schematic of Differential Output Mode
88
Table 43: Spectrum API: Differential Output Mode Registers
88
Table 44: Differential Output Mode Availability Depending on Model
88
Table 45: Spectrum API: Double Output Mode Registers
89
Table 46: Availability of Double Output Mode Depending on Model
89
Table 47: Spectrum API: Stoplevel Registers and Available Settings for Stoplevel
89
Image 47: Schematics of Double Output Mode
89
Double out Mode
89
Programming the Behaviour in Pauses and after Replay
89
Table 48: Spectrum API: Custom Stoplevel Registers
90
Read out of Output Features
91
Generation Modes
92
Overview
92
Setup of the Mode
92
Commands
92
Table 49: Spectrum API: Card Mode and Read out of Available Card Mode Software Registers
92
Table 50: Spectrum API: Card Command Register and Different Commands with Descriptions
92
Card Status
93
Table 51: Spectrum API: Timeout Definition Register
93
Table 52: Spectrum API: Card Status Register and Possible Status Values with Descriptions of the Status
93
Acquisition Cards Status Overview
94
Generation Card Status Overview
94
Data Transfer
94
Image 48: Acquisition Cards: Graphical Overview of Acquisition Status and Card Command Interaction
94
Image 49: Generation Cards: Graphical Overview of Generation Status and Card Command Interaction
94
Table 55: Spectrum API: Status Register and Status Codes for DMA Data Transfer
96
Table 53: Spectrum API: Memory Test Register
96
Table 54: Spectrum API: Command Register and Commands for DMA Transfers
96
Table 56: Spectrum API: Card Mode Register and Single Mode Settings
97
Table 57: Spectrum API: Memory and Loop Settings
97
Standard Single Replay Modes
97
Image 50: Timing Diagram of Single Replay Mode with Commands and Status Changes
97
Memory Setup
97
Card Mode
97
Image 53: Timing Diagram of Single Restart Mode with Commands and Status Changes
98
Table 58: Spectrum API: Overview of Mode Settings in Relation to Loops Settings and Resulting Behaviour
98
Continuous Marker Output
98
Image 52: Timing Diagram of Continuous Replay Mode Stopped by User with Commands and Status Changes
98
Image 51: Timing Diagram of Single Replay Mode with Two Loops with Commands and Status Changes
98
Example
99
FIFO Single Replay Mode
100
Length of FIFO Mode
100
Difference to Standard Single Mode
100
Table 59: Spectrum API: FIFO Single Replay Mode Register and Settings
100
Table 60: Spectrum API: FIFO Mode Length Settings Registers
100
Card Mode
100
Example (FIFO Replay)
101
Limits of Segment Size, Memory Size
102
Table 61: Limits of Segment Size, Memory Size, Loops Depending on Activated Channels and Mode
102
Table 63: Spectrum API: Content of DMA Buffer Handling Registers for Different Use Cases
103
Buffer Handling
103
Table 62: Spectrum API: Registers for DMA Buffer Handling
103
Image 54: Overview of Buffer Handling for DMA Transfers Showing and the Interaction with the DMA Engine
103
Output Latency
106
Image 55: Output Latency Involved Components
106
Table 64: Spectrum API: Output Buffer Size Register and Register Settings
106
Table 65: Output Latency Depending on Channel Settings, Buffer Settings and Output FIFO
106
Data Organization
108
Sample Format
108
Table 66: Spectrum API: Overview of Data Organization in Memory for Different Channel Configurations
108
Table 67: Sample Format Depending on the Selected Digital Output Mode
108
Hardware Data Conversion
109
Table 68: Spectrum API: Hardware Data Conversion Registers and Available Conversion Settings
109
Table 70: Spectrum API: Clock Mode Software Register and Setting
110
Table 69: Spectrum API: Clock Mode Register and Available Clock Modes
110
Image 56: Overview of M2P Clock Structure with Optional Star-Hub
110
The Different Clock Modes
110
Clock Generation
110
Standard Internal Sampling Clock (PLL)
110
Overview
110
Clock Mode Register
110
Maximum and Minimum Internal Sampling Rate
111
Oversampling
111
Direct External Clock
111
Table 71: Spectrum API: Samplerate Software Register
111
Table 72: Spectrum API: Clock Output and Clock Output Frequency Register
111
Table 73: Spectrum API: Clock Oversampling Readout Register
111
Table 74: Spectrum API: Software Clock Mode Register and External Clock Settings
111
External Reference Clock
112
Table 75: Spectrum API: Clock Termination Software Register
112
Table 76: Spectrum API: Clock Threshold Software Registers and Available Range Therefore
112
Table 77: Spectrum API: Clock Mode Software Register and External Reference Clock
112
Table 78: Spectrum API: Reference Clock Software Register
112
Table 79: Spectrum API: Clock Threshold Software Registers and Available Range Therefore
113
Image 57: M2P Card Trigger Engine Overview with the Different Trigger Sources and Trigger Outputs
114
Trigger Engine Overview
114
General Description
114
Trigger Modes and Appendant Registers
114
Trigger Masks
115
Trigger or Mask
115
Image 58: Trigger Overview - Trigger or Mask
115
Image 59: Trigger or Mask Details
115
Table 80: Spectrum API: External Trigger or Mask Related Software Register and Available Settings
115
Trigger and Mask
116
Image 61: Trigger and Mask Details
116
Table 81: Spectrum API: Channel Trigger or Mask Related Software Register and Available Settings
116
Image 60: Trigger Overview - Trigger and Mask
116
Software Trigger
117
Table 82: Spectrum API: External Trigger and Mask Related Software Register and Available Settings
117
Table 83: Spectrum API: Channel Trigger and Mask Related Software Register and Available Settings
117
Table 84: Spectrum API: Software Register and Register Setting for Software Trigger
117
Table 85: Spectrum API: Command Register and Force Trigger Command
118
Table 87: Spectrum API: Delay Trigger Software Registers and Programmable Settings
118
Table 86: Spectrum API: Command Register and Trigger Enable/Disable Command
118
Image 62: M2P Trigger Engine Overview and Delay Trigger
118
Trigger Delay
118
Force- and Enable Trigger
118
Table 88: Spectrum API: Trigger Holdoff Related Registers and Settings for These
119
Trigger Holdoff
119
Image 63: Trigger Engine Overview and External Trigger
120
Table 91: Spectrum API: Register for Controlling Analog Trigger Input Termination
120
Table 90: Spectrum API: Trigger or Mask and Setup for External Trigger
120
Table 89: Spectrum API: External Trigger Mode Registers and Available Settings Therefore
120
Trigger Level
120
Trigger Input Termination
120
Trigger Mode
120
Main Analog External Trigger (Ext0)
120
Detailed Description of the External Analog Trigger Modes
121
Table 92: Spectrum API: Software Registers for External Trigger Levels
121
Table 93: Spectrum API: Software Registers to Program External Trigger
121
Table 94: Spectrum API: Trigger Mode Register and Settings for Positive Edge External Trigger
121
Table 95: Spectrum API: Trigger Mode Register and Settings for Negative Edge External Trigger
121
Table 98: Spectrum API: Trigger Mode Register and Settings for Low Level External Trigger
122
Table 97: Spectrum API: Trigger Mode Register and Settings for High Level External Trigger
122
Table 96: Spectrum API: Trigger Mode Register and Settings for Positive and Negative Edges External Trigger
122
Table 99: Spectrum API: Trigger Mode Register and Settings for Long Positive Pulses on the External Trigger Input
123
Table 100: Spectrum API: Trigger Mode Register and Settings for Long Negative Pulses on the External Trigger Input
123
Table 101: Spectrum API: Trigger Mode Register and Settings for Short Positive Pulses on the External Trigger Input
123
Table 102: Spectrum API: Trigger Mode Register and Settings for Short Negative Pulses on the External Trigger Input
124
Table 103: Spectrum API: Register for Reading out the Maximum Available Value for Pulse Length Detection Using Pulse-Width Trigger
124
External Logic Trigger (X1, X2, X3)
125
Trigger Mode
125
Image 64: Trigger Engine Overview and Multi Purpose Trigger
125
Table 104: Spectrum API: External Logic Trigger Registers and Settings for Them
125
Table 105: Spectrum API: Trigger or Mask Register an Settings for External Logic Trigger
125
Detailed Description of the Logic Trigger Modes
126
Table 106: Spectrum API: Trigger Mode Register and Settings for Positive TTL Edge Trigger
126
Table 107: Spectrum API: Trigger Mode Register and Settings for High Level TTL Trigger
126
Table 108: Spectrum API: Trigger Mode Register and Settings for Negative TTL Edge Trigger
126
Table 111: Spectrum API: Trigger Mode Register and Settings for TTL on Long High Pulses Trigger
127
Table 112: Spectrum API: Trigger Mode Register and Settings for TTL on Short High Pulses Trigger
127
Table 110: Spectrum API: Trigger Mode Register and Settings for Positive and Negative TTL Edge Trigger
127
Table 109: Spectrum API: Trigger Mode Register and Settings for Low Level TTL Trigger
127
Table 113: Spectrum API: Trigger Mode Register and Settings for TTL on Long Low Pulses Trigger
128
Table 114: Spectrum API: Trigger Mode Register and Settings for TTL on Short Low Pulses Trigger
128
Table 115: Spectrum API: Register for Reading the Maximum Value for Defining External Pulse Length Using Pulsewidth Trigger
128
Image 65: Overview Block Diagram of Multi-Purpose I/O Lines
129
Table 116: Spectrum API: XIO Lines and Mode Software Registers with Their Available Settings
129
Programming the Behavior
129
Standard I/O Lines (X0, X1, X2, X3)
129
Multi Purpose I/O Lines
129
Asynchronous I/O
130
Special Behavior of Trigger Output
130
Image 66: Spectrum API: Compatibility Trigger Output Register and Settings Behaviour
130
Table 117: Spectrum API: Asynchronous I/O Register and Register Settings
130
Synchronous Digital Outputs
131
Table 118: Spectrum API: Synchronous Digital Output Registers and Register Settings
131
Table 119: Sample Format Depending on the Selected Digital Output Mode
131
Additional I/O Lines with Option -Digbnc
132
Table 121: Spectrum API: Digital Output Option Asynchronous I/O Register
133
Asynchronous I/O
133
Table 120: Spectrum API: Digtal Output Option Mode Registers and Available Mode Settings
133
Programming the Behavior
133
Synchronous Digital Outputs
134
Table 122: Spectrum API: Synchronous Digital Output Registers and Register Settings
134
Table 123: Sample Format Depending on the Selected Digital Output Mode
134
Image 67: Multiple Replay Output and Trigger Timing Diagram
136
Table 124: Spectrum API: Segment Size Register for Multiple Replay Mode
136
Programming Examples
136
Trigger Modes
136
Mode Multiple Replay
136
Replay Modes
137
Standard Mode
137
FIFO Mode
137
Image 68: Timing Diagram of Multiple Replay Mode Depending on Loops Settings
137
Image 69: Spectrum API: Card Mode Register and Multiple Replay FIFO Mode Settings
137
Table 125: Spectrum API: Card Mode Register and Multiple Replay Settings
137
Table 126: Spectrum API: Memory and Loop Registers with Related Multiple Replay Settings
137
Table 127: Spectrum API: Loops Register Settings When Using Multiple Replay FIFO Mode
137
Table 128: Limits of Segment Size, Memory Size, Loops Depending on Activated Channels and Mode
138
Limits of Segment Size, Memory Size
138
Image 70: Timing Diagram of Multiple Replay FIFO Mode with Different Loops Settings
138
Table 129: Spectrum API: Stoplevel Registers and Available Settings for Stoplevel
139
Table 130: Spectrum API: Custom Stoplevel Registers
139
Programming the Behaviour in Pauses and after Replay
139
Mode Gated Replay
140
Generation Modes
140
Standard Mode
140
Examples of Standard Standard Gated Replay with the Use of SPC_LOOPS Parameter
140
FIFO Mode
140
Image 71: Gated Replay Timing Diagram in Relation to Gate Signal
140
Image 72: Timing Diagram of Gated Replay Mode Depending on Different Loops Settings
140
Table 131: Spectrum API: Card Mode Register and Settings for Gated Replay Standard Mode
140
Table 132: Spectrum API: Memsize and Loops Register and Register Settings for Gated Replay Mode
140
Table 133: Spectrum API: Card Mode Register and Gated Replay FIFO Mode Settings
140
Table 134: Spectrum API: Gated Replay FIFO Mode Loops Register Settings
141
Table 135: Limits of Segment Size, Memory Size, Loops Depending on Activated Channels and Mode
141
Image 73: Timing Diagram of Gated Replay FIFO Mode Depending on Different Loops Settings
141
Limits of Segment Size, Memory Size
141
Examples of Fifo Gated Replay with the Use of SPC_LOOPS Parameter
141
Trigger
143
Detailed Description of the External Analog Trigger Modes
143
Table 136: Spectrum API: External Analog Trigger Registers
143
Table 137: Spectrum API: Trigger Mode Register and Settings for Positive Edge External Trigger
143
Table 138: Spectrum API: Trigger Mode Register and Settings for Negative Edge External Trigger
143
Table 141: Spectrum API: Trigger Mode Register and Settings for Long Positive Pulses for External Trigger Input
144
Table 140: Spectrum API: Trigger Mode Register and Settings for LOW Level External Trigger
144
Table 139: Spectrum API: Trigger Mode Register and Settings for HIGH Level External Trigger
144
Detailed Description of the Logic Gate Trigger Modes
145
Table 142: Spectrum API: Trigger Mode Register and Settings for Long Negative Pulses for External Trigger Input
145
Table 143: Spectrum API: Trigger Mode Register and Settings for Positive TTL Edge Trigger
145
Table 144: Spectrum API: Trigger Mode Register and Settings for High-Level TTL Trigger
145
Table 145: Spectrum API: Trigger Mode Register and Settings for Negative TTL Edge Rigger
145
Table 146: Spectrum API: Trigger Mode Register and Settings for Low-Level TTL Trigger
146
Table 147: Spectrum API: Trigger Mode Register and Settings for Long High-Pulses Trigger
146
Table 148: Spectrum API: Trigger Mode Register and Settings for Long Low-Pulses Trigger
146
Table 150: Spectrum API: Custom Stoplevel Registers
147
Table 149: Spectrum API: Stoplevel Registers and Available Settings for Stoplevel
147
Programming the Behaviour in Pauses and after Replay
147
Programming Examples
147
Sequence Replay Mode
148
Theory of Operation
148
Define Segments in Data Memory
148
Define Steps in Sequence Memory
148
Image 74: Sequence Mode: Segment Definition in Card Memory
148
Image 75: Sequence Mode: Steps and Step Looping
148
Table 152: Spectrum API: Card Mode Register with Sequence Mode Setup
149
Table 153: Spectrum API: Sequence Mode Registers for Segment Handling
149
Gathering Information
149
Table 151: Spectrum API: Sequence Mode Registers and Register Settings
149
Setting up the Registers
149
Programming
149
Table 154: Limits and Step Sizes for the Segment Memory in Sequence Replay Mode
150
Table 155: Spectrum API: Registers for Setting up the Step Memory in Sequence Replay Mode
150
Table 156: Spectrum API: Register for Defining the First Step (STARTSTEP) in a Sequence
150
Table 157: Spectrum API: Register for Reading out the Currently Replayed Sequence Step
151
Image 76: Sequence Mode Changing Sequence On-The-Fly
151
Synchronization
151
Changing Data Patterns During Runtime
151
Changing Sequences or Step Parameters During Runtime
151
Programming Example
152
Pulse Generator (Firmware Option)
153
General Information
153
Image 77: Overview Block Diagram of Multi-Purpose I/O Lines and Pulse Generators
153
Principle of Operation
154
Image 78: Overview Block Diagram of the Pulse Generator
154
Table 158: Spectrum API: Pulse Generator Clock Frequency Read Register
154
Table 159: Spectrum API: Pulse Generator Enable Registers
155
Table 161: Spectrum API: Pulse Generator HIGH Time Registers
155
Table 160: Spectrum API: Pulse Generator Length/Period Register
155
Setting up the Pulse Generator
155
Image 79: Timing Diagram Illustrating the Basic Pulse Parameters
155
Defining the Basic Pulse Parameters
155
Enabling, Disabling and Resetting a Pulse Generator
155
Table 164: Spectrum API: Pulse Generator Mode Registers with Their Available Settings
156
Table 163: Spectrum API: Pulse Generator Delay/Phase Shift Registers
156
Image 80: Timing Diagram Illustrating Delaying a Pulse Generator Output
156
Table 162: Spectrum API: Pulse Generator Loops/Pulse Repetition Registers
156
Defining the Trigger Behavior
156
Delaying (Phase Shifting) the Outputs
156
Image 81: Timing Diagram Illustrating the Pulse Generator Triggered Output Mode
157
Image 82: Timing Diagram Illustrating the Pulse Generator Single-Shot Triggered Output Mode
157
Image 83: Timing Diagram Illustrating the Pulse Generator Gated Output Mode
157
Table 165: Spectrum API: Pulse Generator Trigger MUX1 Registers with Their Available Settings
157
Configuring the Pulse Generator's Trigger Source
157
Table 166: Spectrum API: Pulse Generator Trigger MUX2 Registers with Their Available Settings
158
Table 167: Spectrum API: Pulse Generator Command Register for Trigger Forcing by Software
158
Table 168: Spectrum API: Pulse Generator Additional Configuration Registers with the Available Settings
158
Configuring Multi Purpose Lines to Output Generated Pulses
159
Table 169: Spectrum API: XIO Lines and Mode Software Registers with Their Reduced to the Settings Required for Outputting Pulses
159
Programming Example
160
Star-Hub Clock Engine
161
Software Interface
161
Image 84: Drawing of Star-Hub Clock Engine Location and Interaction with Card Clock
161
Star-Hub Trigger Engine
161
Star-Hub Introduction
161
Star-Hub Initialization
161
Option Star-Hub
161
Table 170: Spectrum API: Star-Hub Related Registers for Reading Detected Connections
162
Setup of Synchronization
163
Table 171: Spectrum API: Synchronization Enable Mask Register
163
Limits of Clock for Synchronized Cards
164
Setup of Trigger
164
Table 172: Spectrum API: Star-Hub Synchronization Commands
165
Run the Synchronized Cards
165
Error Handling
166
Accessing the Embedded Server
167
SSH Connection
167
Login
167
Mounting Network Folders
167
Image 85: Diagram of Embedded Server Option
167
Image 86: SSH Client Connection to Embedded Server of DN2/DN6
167
Option Embedded Server
167
Accessing the Cards
168
Examples
168
Editors
168
Programming
168
Installing Packages
168
Access to NTP (Network Time Protocol)
168
Autostart
169
Leds
169
Appendix
170
Error Codes
170
Table 173: Spectrum API: Driver Error Codes and Error Description
170
Spectrum Knowledge Base
171
Temperature Sensors
172
Temperature Read-Out Registers
172
Temperature Hints
172
65Xx Temperatures and Limits
172
Table 174: Spectrum API: Temperature Sensor Registers
172
Table 175: 65Xx Temperature Typical and Maximum Figures
172
Table 177: Spectrum API: M2P.654X and M2P.657X Specific Egisters for Accessing Analog Front-End Module Fault Detection
173
Table 176: Spectrum API: M2P.654X and M2P.657X Specific Temperature Monitor Read Registers
173
Additional Temperature Sensors for M2P.654X and M2P.657X
173
DN6 Temperature Sensors
174
Table 178: Spectrum API: DN6 Temperature Sensor Registers
174
Details on M2P Cards I/O Lines
175
Multi Purpose I/O Lines
175
Additional I/O Lines (Option -Digfx2)
175
Image 87: Electrical Connection and Termination of Multi-Purpose I/O Lines
175
Image 88: Electrical Connection of Additional I/O Lines on Connection Digfx2
175
Image 90: Electrical Connection of Additional I/O Lines on Connection Digbnc (Digitizernetbox)
176
Image 91: Electrical Interfacing of Clock Connections between M2P and M4I Cards
176
Additional I/O Lines (Option -Digsmb)
176
Image 89: Electrical Connection of Additional I/O Lines on Connection Digsmb
176
Interfacing M2P Clock In/Out with M4I/M4X
176
Additional I/O Lines (Option -Digbnc)
176
Abbreviations
178
Table 179: Abbreviations Used Throughout the Spectrum Documents
178
List of Figures
179
List of Tables
181
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