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ClockSoC SiT95145
SiTime ClockSoC SiT95145 IC Integration Manuals
Manuals and User Guides for SiTime ClockSoC SiT95145 IC Integration. We have
1
SiTime ClockSoC SiT95145 IC Integration manual available for free PDF download: User Manual
SiTime ClockSoC SiT95145 User Manual (95 pages)
Cascade Platform for Clock Generators, Jitter Cleaners, and Network Synchronizers
Brand:
SiTime
| Category:
Single board computers
| Size: 3 MB
Table of Contents
Table of Contents
1
1 Introduction
3
2 Document Applicability
4
3 Cascade GUI Installation
5
4 Starting the GUI
10
5 Functional Descriptions of Sit9514X Device Variants
11
6 GUI Usage
17
Sections in the GUI
17
GUI Sections Overview
17
Chip Communication and Interrupt
18
Input Clock Reference Section
19
Input Section
20
PLL Section
21
Output Section
22
Bird's Eye Section
23
7 Sit9514X Device Configuration Tasks
24
TASK 1: Select Inputs
24
Sit95141, Sit95145 Input Configuration
26
Sit95147, Sit95148 Input Configuration
27
Sit95148 Clock Loss Configuration
28
TASK 2: Set up PLL Parameters
29
TASK 3: Save or Load UI Configuration and Program the Sit9514X Device
31
Saving and Loading the UI Configuration File
31
Using the Dump Function
34
Saving Efuse.nvm.py (I2C/SPI) Files
37
Saving the Cascade Sitime GUI State
39
Using the Load NVM Function
41
Using the Load NVM Function
46
TASK 4: Use Realtime to Set Output Frequency with DCO or View Clock Monitor Status
48
Interrupts
49
On-The-Fly Change
51
Managing On-The-Fly Frequencies
52
Using the Dump Fly Function
53
Dynamic Profile On-The-Fly with Single Output Per PLL
55
Description of Dynamic Header Files
59
Using the Load Fly Function
63
Flexio
64
Phase Sync Feature
67
Input to Output Delay Control Feature
69
Sit9514X Jitter Attenuator as Timing Source for JESD204B RF Converters in 5G RRU
71
7.10.1 JESD204B Overview
71
Cascade as Clock Source for JESD204B Timing Signals
72
Configuring the Sit9514X for JESD204B Timing Signals
74
Generating SYSREF Via SYSREF_REQ
74
8 Snapshots of Specific Use Case Scenarios
81
Free Running DCO
85
Zero-Delay Buffer Mode
88
9 Low Wander Mode
89
10 Usage Guidelines for Jitter Performance Optimization
90
Output Placement and Frequency Planning
90
CMOS Output Type Selection
93
11 Document Information
95
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