Renesas R5F35783JFF Manuals

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Renesas R5F35783JFF Hardware User Manual

Renesas R5F35783JFF Hardware User Manual (1031 pages)

Brand: Renesas | Category: Microcontrollers | Size: 12 MB

Table of Contents

General Precautions in the Handling of MPU/MCU Products
3
About this Manual
4
Numbers and Symbols
5
Abbreviations and Acronyms
7
Table of Contents
8
Quick Reference
29
Overview
46
Features
46
Applications
46
Specifications
47
Product List
53
Block Diagrams
57
Pin Assignments
60
Pin Functions
69
Signal Name
70
Central Processing Unit (CPU)
72
Data Registers (R0, R1, R2, and R3)
73
Address Registers (A0 and A1)
73
Frame Base Register (FB)
73
Interrupt Table Register (INTB)
73
Program Counter (PC)
73
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
73
Static Base Register (SB)
73
Flag Register (FLG)
73
Carry Flag (C Flag)
73
Debug Flag (D Flag)
73
Interrupt Enable Flag (I Flag)
74
Stack Pointer Select Flag (U Flag)
74
Processor Interrupt Priority Level (IPL)
74
Reserved Areas
74
Memory
75
Special Function Registers (Sfrs)
77
Sfrs
77
Notes on Sfrs
124
Register Settings
124
Protection
126
Introduction
126
Register
126
Protect Register (PRCR)
126
Notes on Protection
128
Resets
129
Introduction
129
Registers
131
Processor Mode Register 0 (PM0)
131
Reset Source Determine Register (RSTFR)
132
Optional Function Select Area
133
Optional Function Select Address 1 (OFS1)
133
Operations
135
Status after Reset
135
Hardware Reset
137
Power-On Reset Function
138
Voltage Monitor 0 Reset
139
Voltage Monitor 2 Reset
139
Oscillator Stop Detect Reset
139
Watchdog Timer Reset
139
Software Reset
140
Notes on Resets
141
Power Supply Rising Gradient
141
Power-On Reset
141
OSDR Bit (Oscillation Stop Detect Reset Detect Flag)
141
Hardware Reset When VCC < Vdet0
141
Voltage Detector
142
Introduction
142
Registers
143
Voltage Detector 2 Flag Register (VCR1)
144
Voltage Detector Operation Enable Register (VCR2)
145
Voltage Monitor Function Select Register (VWCE)
146
Voltage Detector 2 Level Select Register (VD2LS)
147
Voltage Monitor 0 Control Register (VW0C)
148
Voltage Monitor 2 Control Register (VW2C)
149
Optional Function Select Area
151
Optional Function Select Address 1 (OFS1)
151
Operations
152
Digital Filter
152
Voltage Detector 0
153
Voltage Detector 2
155
Monitoring Vdet2
155
Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset
156
Interrupts
158
Clock Generator
159
Introduction
159
Registers
161
System Clock Control Register 0 (CM0)
162
System Clock Control Register 1 (CM1)
164
Oscillation Stop Detection Register (CM2)
166
Peripheral Clock Select Register (PCLKR)
168
PLL Control Register 0 (PLC0)
169
Processor Mode Register 2 (PM2)
170
40 Mhz On-Chip Oscillator Control Register 0 (FRA0)
171
40 Mhz On-Chip Oscillator Control Register 2 (FRA2)
172
Clocks Generated by Clock Generators
173
Main Clock
173
PLL Clock
174
Foco40M
175
Foco-F
175
125 Khz On-Chip Oscillator Clock (Foco-S)
175
Sub Clock (Fc)
176
CPU Clock and Peripheral Function Clocks
177
CPU Clock and BCLK
177
Peripheral Function Clocks (F1, Foco40M, Foco-F, Foco-S, Fc32, Fc, Main Clock)
177
Clock Output Function
179
System Clock Protection Function
179
Oscillator Stop/Restart Detect Function
180
Operation When CM27 Bit Is 0 (Oscillator Stop Detect Reset)
180
Operation When CM27 Bit Is 1 (Oscillator Stop/Restart Detect Interrupt)
181
Using the Oscillator Stop/Restart Detect Function
182
Interrupt
182
Notes on Clock Generator
183
Oscillator Using a Crystal or a Ceramic Resonator
183
Noise Countermeasure
184
CPU Clock
185
Oscillator Stop/Restart Detect Function
185
PLL Frequency Synthesizer
186
Power Control
187
Introduction
187
Registers
187
Flash Memory Control Register 0 (FMR0)
188
Flash Memory Control Register 2 (FMR2)
189
Clock
191
Normal Operating Mode
191
Low Power Mode
192
Clock Mode Transition Procedure
195
Wait Mode
198
Stop Mode
200
Entering Stop Mode
200
Exiting Stop Mode
201
Power Control in Flash Memory
202
Stopping Flash Memory
202
Reading Flash Memory
203
Reducing Power Consumption
205
Ports
205
A/D Converter
205
D/A Converter
205
Stopping Peripheral Functions
205
Switching the Oscillation-Driving Capacity
205
Notes on Power Control
206
CPU Clock
206
Wait Mode
206
Stop Mode
206
Low Current Consumption Read Mode
207
Slow Read Mode
207
10. Processor Mode
208
Introduction
208
Registers
209
Processor Mode Register 1 (PM1)
209
Program 2 Area Control Register (PRG2C)
210
Flash Memory Control Register 1 (FMR1)
211
Software Wait
212
Bus Hold
212
11. Programmable I/O Ports
213
Introduction
213
I/O Ports and Pins
214
Registers
222
NMI Digital Debounce Register (NDDR)
223
P1_7 Digital Debounce Register (P17DDR)
223
Pull-Up Control Register 0 (PUR0)
224
Pull-Up Control Register 1 (PUR1)
224
Pull-Up Control Register 2 (PUR2)
225
Port Control Register (PCR)
226
Input Threshold Select Register 0 (VLT0)
227
Input Threshold Select Register 1 (VLT1)
228
Input Threshold Select Register 2 (VLT2)
228
Pin Assignment Control Register (PACR)
229
Port Pi Register (Pi) (I = 0 to 10)
230
Port Pi Direction Register (Pdi) (I = 0 to 10)
231
Peripheral Function I/O
232
Peripheral Function I/O and Port Direction Bits
232
Priority Level of Peripheral Function I/O
232
Digital Debounce Filters
233
Unassigned Pin Handling
235
Notes on Programmable I/O Ports
236
Pin Assignment Control
236
Influence of SD
236
Input Voltage Threshold
236
12. Interrupts
237
Introduction
237
Registers
238
Processor Mode Register 2 (PM2)
240
Interrupt Control Register 1
241
S4TIC/RTCCIC, S4RIC, C0WIC,S3TIC/C0EIC, RTCTIC/C1EIC, C0RIC, C1RIC, C0TIC, C1TIC, C0FRIC, C1FRIC, C0FTIC, C1FTIC, ICOC0IC, ICOCH0IC, ICOC1IC/IICIC, ICOCH1IC/SCLDAIC, ICOCH2IC to ICOCH3IC, BTIC)
241
(INT7IC/SS0IC, INT6IC/LIN0IC, INT3IC, INT5IC, INT4IC, INT0IC to INT2IC)
242
Interrupt Source Select Register 4 (IFSR4A)
244
Interrupt Source Select Register 3 (IFSR3A)
245
Interrupt Source Select Register 2 (IFSR2A)
246
Interrupt Source Select Register (IFSR)
247
Address Match Interrupt Enable Register (AIER)
248
Address Match Interrupt Enable Register 2 (AIER2)
248
Address Match Interrupt Register I (Rmadi) (I = 0 to 3)
249
NMI Digital Debounce Register (NDDR)
250
P1_7 Digital Debounce Register (P17DDR)
250
Types of Interrupts
251
Software Interrupts
252
Undefined Instruction Interrupt
252
Overflow Interrupt
252
BRK Interrupt
252
INT Instruction Interrupt
252
Hardware Interrupts
253
Special Interrupts
253
NMI Interrupt
253
Peripheral Function Interrupts
253
Interrupts and Interrupt Vectors
254
Fixed Vector Tables
254
Relocatable Vector Tables
255
Interrupt Control
257
Maskable Interrupt Control
257
Interrupt Sequence
258
Interrupt Response Time
259
Variation of IPL When Interrupt Request Is Accepted
259
Saving Registers
260
Returning from an Interrupt Routine
261
Interrupt Priority
261
Interrupt Priority Level Select Circuit
261
Multiple Interrupts
263
INT Interrupt
263
NMI Interrupt
264
12.10 Key Input Interrupt
264
12.11 Address Match Interrupt
265
12.12 Non-Maskable Interrupt Source Discrimination
266
12.13 Notes on Interrupts
267
12.13.1 Reading Address 00000H
267
12.13.2 SP Setting
267
12.13.3 NMI Interrupt
267
12.13.4 Changing an Interrupt Source
268
12.13.5 Rewriting the Interrupt Control Register
269
12.13.6 Instruction to Rewrite the Interrupt Control Register
269
12.13.7 INT Interrupt
270
13. Watchdog Timer
271
Introduction
271
Registers
273
Voltage Monitor 2 Control Register (VW2C)
274
Count Source Protection Mode Register (CSPR)
275
Watchdog Timer Refresh Register (WDTR)
275
Watchdog Timer Start Register (WDTS)
276
Watchdog Timer Control Register (WDC)
276
Optional Function Select Area
277
Optional Function Select Address 1 (OFS1)
277
Optional Function Select Address 2 (OFS2)
278
Operations
279
Refresh Operation Period
279
Count Source Protection Mode Disabled
280
Count Source Protection Mode Enabled
281
Interrupts
282
Notes on the Watchdog Timer
283
14. Dmac
284
Introduction
284
Registers
286
Dmai Source Pointer (Sari) (I = 0 to 3)
287
Dmai Destination Pointer (Dari) (I = 0 to 3)
287
Dmai Transfer Counter (Tcri) (I = 0 to 3)
288
Dmai Control Register (Dmicon) (I = 0 to 3)
289
Dmai Source Select Register (Dmisl) (I = 0 to 3)
290
Operations
293
DMA Enabled
293
DMA Request
293
Transfer Cycles
294
DMAC Transfer Cycles
296
Single Transfer Mode
297
Repeat Transfer Mode
298
Channel Priority and DMA Transfer Timing
299
Interrupts
300
Notes on DMAC
301
Write to the DMAE Bit in the Dmicon Register (I = 0 to 3)
301
Changing the DMA Request Source
301
15. Timer a
302
Introduction
302
Registers
305
Peripheral Clock Select Register (PCLKR)
306
Clock Prescaler Reset Flag (CPSRF)
306
Timer AB Division Control Register 0 (TCKDIVC0)
307
Timer a Count Source Select Register I (Tacsi) (I = 0 to 2)
308
16-Bit Pulse Width Modulation Mode Function Select Register (PWMFS)
309
Timer a Waveform Output Function Select Register (TAPOFS)
310
Timer a Output Waveform Change Enable Register (TAOW)
311
Timer Ai Register (Tai) (I = 0 to 4)
312
Event Counter Mode
312
One-Shot Timer Mode
312
Timer Ai-1 Register (Tai1) (I = 1, 2, 4)
313
Count Start Flag (TABSR)
313
One-Shot Start Flag (ONSF)
314
Trigger Select Register (TRGSR)
315
Increment/Decrement Flag (UDF)
316
Timer Ai Mode Register (Taimr) (I = 0 to 4)
317
Operations
318
Common Operations
318
Count Source
319
Timer Mode
320
Event Counter Mode (When Not Using Two-Phase Pulse Signal Processing)
324
Event Counter Mode (When Processing Two-Phase Pulse Signal)
328
Normal Processing
331
One-Shot Timer Mode
333
Pulse Width Modulation (PWM) Mode
337
Programmable Output Mode (Timers A1, A2, and A4)
342
Interrupts
346
Notes on Timer a
347
Common Notes on Multiple Modes
347
Timer a (Timer Mode)
348
Timer a (Event Counter Mode)
348
Timer a (One-Shot Timer Mode)
348
Changing Operating Modes
348
Timer a (Pulse Width Modulation Mode)
349
Timer a (Programmable Output Mode)
350
Changing the Operating Mode
350
16. Timer B
351
Introduction
351
Registers
354
Peripheral Clock Select Register (PCLKR)
355
Clock Prescaler Reset Flag (CPSRF)
355
Timer Bi Register (Tbi) (I = 0 to 5)
356
Event Counter Mode
356
Timer Bi-1 Register (Tbi1) (I = 0 to 5)
357
Pulse Period/Pulse Width Measurement Mode Function Select Register I (Ppwfsi) (I = 1, 2)
358
Timer B Count Source Select Register I (Tbcsi) (I = 0 to 3)
359
Timer AB Division Control Register 0 (TCKDIVC0)
360
Count Start Flag (TABSR) Timer B3/B4/B5 Count Start Flag (TBSR)
361
Timer Bi Mode Register (Tbimr) (I = 0 to 5)
362
Operations
363
Common Operations
363
Timer Mode
365
Event Counter Mode
367
Pulse Period/Pulse Width Measurement Modes
370
Interrupts
375
Notes on Timer B
376
Common Notes on Multiple Modes
376
Timer B (Timer Mode)
376
Timer B (Event Counter Mode)
376
Timer B (Pulse Period/Pulse Width Measurement Modes)
377
Pulse Period Measurement Mode
377
Pulse Width Measurement Mode
377
17. Three-Phase Motor Control Timer Function
378
Introduction
378
Registers
382
Timer B2 Register (TB2)
383
Timer Ai, Ai-1 Register (Tai, Tai1) (I = 1, 2, 4)
383
Three-Phase PWM Control Register 0 (INVC0)
384
Three-Phase PWM Control Register 1 (INVC1)
386
Three-Phase Output Buffer Register I (Idbi) (I = 0, 1)
388
Dead Time Timer (DTT)
388
Timer B2 Interrupt Generation Frequency Set Counter (ICTB2)
389
Timer B2 Special Mode Register (TB2SC)
390
Position-Data-Retain Function Control Register (PDRF)
391
Port Function Control Register (PFCR)
392
Three-Phase Protect Control Register (TPRC)
392
Operations
393
Common Operations in Multiple Modes
393
Dead Time Control
394
Triangular Wave Modulation Three-Phase Mode 0
399
Triangular Wave Modulation Three-Phase Mode 1
404
Sawtooth Wave Modulation Mode
411
Interrupts
416
Timer B2 Interrupt
416
Timer A1, A2, and A4 Interrupts
416
Notes on Three-Phase Motor Control Timer Function
417
Timer a and Timer B
417
Influence of SD
417
18. Timer S
418
Introduction
418
Registers
422
Time Measurement Register J (G1Tmj) (J = 0 to 7)
424
Waveform Generation Register J (G1Poj) (J = 0 to 7)
425
Waveform Generation Control Register J (G1Pocrj) (J = 0 to 7)
426
Time Measurement Control Register J (G1Tmcrj) (J = 0 to 7)
428
Base Timer Register (G1BT)
430
Base Timer Control Register 0 (G1BCR0)
431
Base Timer Control Register 1 (G1BCR1)
432
Time Measurement Prescaler Register J (G1Tprj) (J = 6 and 7)
433
Function Enable Register (G1FE)
433
Function Select Register (G1FS)
434
Base Timer Reset Register (G1BTRR)
435
Count Source Divide Register (G1DV)
435
Waveform Output Master Enable Register (G1OER)
436
Timer S I/O Control Register 0 (G1IOR0)
437
Timer S I/O Control Register 1 (G1IOR1)
438
Interrupt Request Register (G1IR)
439
Interrupt Enable Register 0 (G1IE0)
440
Interrupt Enable Register 1 (G1IE1)
441
Operations
442
Base Timer
442
Specification
442
Time Measurement Function
450
Waveform Generation Function
454
Specification
455
I/O Port Select Function
466
Interrupts
467
IC/OC Base Timer Interrupt
468
IC/OC Channel 0 Interrupt to IC/OC Channel 3 Interrupt
468
IC/OC Interrupt 0 and IC/OC Interrupt 1
468
Notes on Timer S
469
Register Access
469
Changing the G1IR Register
469
Changing Registers Icociic (I = 0, 1)
471
Output Waveform During the Base Timer Reset with the BTS Bit
471
OUTC1_0 Pin Output During the Base Timer Reset with the G1PO0 Register
471
Interrupt Request When Selecting Time Measurement Function
471
19. Task Monitor Timer
472
Introduction
472
Registers
473
Task Monitor Timer Register (TMOS)
473
Task Monitor Timer Count Start Flag (TMOSSR)
473
Task Monitor Timer Count Source Select Register (TMOSCS)
474
Task Monitor Timer Protect Register (TMOSPR)
474
Operation
475
Interrupt
476
Notes on Task Monitor Timer
477
Register Settings
477
Reading the Timer
477
20. Real-Time Clock
478
Introduction
478
Registers
480
Real-Time Clock Second Data Register (RTCSEC)
481
Real-Time Clock Minute Data Register (RTCMIN)
482
Real-Time Clock Hour Data Register (RTCHR)
483
Real-Time Clock Day Data Register (RTCWK)
484
Real-Time Clock Control Register 1 (RTCCR1)
485
Real-Time Clock Control Register 2 (RTCCR2)
487
Real-Time Clock Count Source Select Register (RTCCSR)
489
Real-Time Clock Second Compare Data Register (RTCCSEC)
490
Real-Time Clock Minute Compare Data Register (RTCCMIN)
491
Real-Time Clock Hour Compare Data Register (RTCCHR)
492
Operations
493
Basic Operation
493
Compare Mode
496
Interrupts
502
Notes on Real-Time Clock
503
Starting and Stopping the Count
503
Register Settings (Time Data, Etc.)
503
Register Settings (Compare Data)
503
Time Reading Procedure in Real-Time Clock Mode
504
Serial Interface Uarti (I = 0 to 4)
505
Introduction
505
Registers
508
UART Clock Select Register (UCLKSEL0)
510
Peripheral Clock Select Register (PCLKR)
510
Uarti Transmit/Receive Mode Register (Uimr) (I = 0 to 4)
511
Uarti Bit Rate Register (Uibrg) (I = 0 to 4)
512
Uarti Transmit Buffer Register (Uitb) (I = 0 to 4)
512
Uarti Transmit/Receive Control Register 0 (Uic0) (I = 0 to 4)
513
Uarti Transmit/Receive Control Register 1 (Uic1) (I = 0 to 4)
515
Uarti Receive Buffer Register (Uirb) (I = 0 to 4)
516
UART2 Special Mode Register 4 (U2SMR4)
518
UART2 Special Mode Register 3 (U2SMR3)
520
UART2 Special Mode Register 2 (U2SMR2)
521
UART2 Special Mode Register (U2SMR)
522
Pin Assignment Control Register (PACR)
523
Operations
524
Clock Synchronous Serial I/O Mode
524
Continuous Receive Mode
529
Clock Asynchronous Serial I/O (UART) Mode
532
Special Mode 1 (I 2 C Mode) (UART2)
541
Special Mode 1 (I C Mode) (UART2)
541
Transmit Data
553
Special Mode 2 (UART2)
556
Special Mode 3 (IE Mode) (UART2)
560
Special Mode 4 (SIM Mode) (UART2)
562
Transmit Timing
564
Receive Timing
564
Interrupts
567
Interrupt Related Registers
567
Reception Interrupt
568
Notes on Serial Interface Uarti (I = 0 to 4)
569
Common Notes on Multiple Modes
569
Register Setting
569
Clock Synchronous Serial I/O Mode
569
Special Mode 1 (I 2 C Mode)
570
Special Mode 4 (SIM Mode)
572
Bus Interface
573
Introduction
573
Multi-Master I C-Bus Interface
574
Registers Descriptions
576
I2C0 Data Shift Register (S00)
577
I2C0 Address Register I (S0Di) (I = 0 to 2)
578
I2C0 Control Register 0 (S1D0)
579
I2C0 Clock Control Register (S20)
581
I2C0 Start/Stop Condition Control Register (S2D0)
583
I2C0 Control Register 1 (S3D0)
584
I2C0 Control Register 2 (S4D0)
588
I2C0 Status Register 0 (S10)
590
I2C0 Status Register 1 (S11)
595
Operations
596
Clock
596
Generating a Start Condition
599
Generating a Stop Condition
601
Generating a Restart Condition
602
Start Condition Overlap Protect
603
Arbitration Lost
605
Detecting Start/Stop Conditions
607
Operation after Transmitting/Receiving a Slave Address or Data
609
Timeout Detection
610
22.3.10 Data Transmit/Receive Examples
611
Initial Settings
611
Master Transmission
612
Master Reception
613
Slave Reception
614
Slave Transmission
615
Interrupts
616
Notes on Multi-Master I 2 C-Bus Interface
619
Limitation on CPU Clock
619
Register Access
619
23. Serial Bus Interface
620
Overview
620
Registers
620
SS0 Bit Counter Register (SS0BR)
621
SS0 Transmit Data Register (SS0TDR)
622
SS0 Receive Data Register (SS0RDR)
622
SS0 Control Register H (SS0CRH)
623
SS0 Control Register L (SS0CRL)
624
SS0 Mode Register (SS0MR)
625
SS0 Enable Register (SS0ER)
626
SS0 Status Register (SS0SR)
627
SS0 Mode Register 2 (SS0MR2)
629
Operations
630
Common Operations
630
Error Processing
635
Synchronous Serial Communication Mode
636
Data Transmission
639
Data Reception
641
Data Transmission/Reception
643
4-Wire Serial Bus Mode
644
Interrupts
653
Notes on Serial Bus Interface
654
SS0SR Register
654
24. LIN Module
655
Interrupt Function
656
LIN Module Associated Registers
657
LIN Wake-Up Baud Rate Select Register (LWBR)
657
LIN Baud Rate Prescaler 0 Register (LBRP0)
658
LIN Baud Rate Prescaler 1 Register (LBRP1)
658
LIN Self-Test Control Register (LSTC)
659
LIN Port Clock Control Register (LPC)
660
LIN0 Mode Register (L0MD)
661
LIN0 Break Field Setting Register (L0BRK)
662
LIN0 Space Width Setting Register (L0SPC)
663
LIN0 Wake-Up Setting Register (L0WUP)
664
LIN0 Interrupt Enable Register (L0IE)
665
LIN0 Error Detection Enable Register (L0EDE)
666
LIN0 Control Register (L0C)
668
LIN0 Transmit Control Register (L0TC)
669
LIN0 Mode Status Register(L0MST)
670
LIN0 Status Register (L0ST)
671
LIN0 Error Status Register (L0EST)
673
LIN0 Response Field Setting Register (L0RFC)
675
LIN0 ID Buffer Register (L0IDB)
677
LIN0 Checksum Buffer Register (L0CB)
678
LIN0 Data N Buffer Register (L0Dbn) (N = 1 to 8)
679
Operational Mode
680
LIN Reset Mode
681
LIN Operation Mode
681
LIN Wake-Up Mode
681
LIN Self-Test Mode
681
Operational Overview
682
Header Transmission
682
Response Transmission
683
Response Reception
684
Baud Rate Generator
685
Data Transmission and Reception
687
Data Transmission
687
Data Reception
688
Buffer Processing of Data to be Transmitted and Received Data
689
Transmission of LIN Frame
689
Reception of LIN Frame
690
Wake-Up Transmission and Reception
691
Operation of Wake-Up Transmission
691
Operation of Wake-Up Reception
691
Low Power Mode Control Using Wake-Up Reception
693
Wake-Up Collision
694
Operational Status
695
Error Status
696
Error Status Types
696
LIN Error Detection Targets
697
24.10 LIN Interrupt
698
24.11 LIN Self-Test Mode
699
24.11.1 Entry into LIN Self-Test Mode
700
24.11.2 Transmission in LIN Self-Test Mode
701
24.11.3 Reception in LIN Self-Test Mode
701
24.11.4 Exit from LIN Self-Test Mode
701
24.12 Notes on LIN Module
702
Influence of SD
702
25. CAN Module
703
CAN Sfrs
706
Cani Control Register (Cictlr) (I = 0, 1)
707
Cani Clock Select Register (Ciclkr) (I = 0, 1)
711
Cani Bit Configuration Register (Cibcr) (I = 0, 1)
712
Cani Mask Register K (Cimkrk) (I = 0, 1; K = 0 to 7)
714
Cani FIFO Received ID Compare Register N (Cifidcr0 to Cifidcr1) (I = 0, 1; N = 0, 1)
715
Cani Mask Invalid Register (Cimkivlr) (I = 0, 1)
717
Cani Mailbox Register J (Cimbj) (I = 0, 1; J = 0 to 31)
718
Cani Mailbox Interrupt Enable Register (Cimier) (I = 0, 1)
722
Cani Message Control Register (Cimctlj) (I = 0, 1; J = 0 to 31)
723
Cani Receive FIFO Control Register (Cirfcr) (I = 0, 1)
727
Cani Receive FIFO Pointer Control Register (Cirfpcr) (I = 0, 1)
730
Cani Transmit FIFO Control Register (Citfcr) (I = 0, 1)
731
Cani Transmit FIFO Pointer Control Register (Citfpcr) (I = 0, 1)
733
Cani Status Register (Cistr) (I = 0, 1)
734
Cani Mailbox Search Mode Register (Cimsmr) (I = 0, 1)
737
Cani Mailbox Search Status Register (Cimssr) (I = 0, 1)
738
Cani Channel Search Support Register (Cicssr) (I = 0, 1)
740
Cani Acceptance Filter Support Register (Ciafsr) (I = 0, 1)
741
Cani Error Interrupt Enable Register (Cieier) (I = 0, 1)
742
Cani Error Interrupt Factor Judge Register (Cieifr) (I = 0, 1)
744
Cani Receive Error Count Register (Cirecr) (I = 0, 1)
747
Cani Transmit Error Count Register (Citecr) (I = 0, 1)
748
Cani Error Code Store Register (Ciecsr) (I = 0, 1)
749
Cani Time Stamp Register (Citsr) (I = 0, 1)
751
Cani Test Control Register (Citcr) (I = 0, 1)
752
Listen-Only Mode
753
Operating Mode
755
CAN Reset Mode
756
CAN Halt Mode
757
CAN Sleep Mode
758
CAN Operation Mode (Excluding Bus-Off State)
759
CAN Operation Mode (Bus-Off State)
760
CAN Communication Speed Configuration
761
CAN Clock Configuration
761
Bit Timing Configuration
761
Bit Rate
762
Mailbox and Mask Register Structure
763
Acceptance Filtering and Masking Function
765
Reception and Transmission
768
Reception
769
Transmission
771
CAN Interrupt
772
26. A/D Converter
773
Introduction
773
Registers
775
Open-Circuit Detection Assist Function Register (AINRST)
776
A/D Register I (Adi) (I = 0 to 7)
777
Analog Pin
777
A/D Control Register 2 (ADCON2)
778
A/D Control Register 0 (ADCON0)
779
A/D Control Register 1 (ADCON1)
781
Operations
782
A/D Conversion Cycle
782
A/D Conversion Start Conditions
784
Software Trigger
784
External Trigger
784
A/D Conversion Result
785
Current Consumption Reduce Function
785
Open-Circuit Detection Assist Function
785
Operational Modes
787
One-Shot Mode
787
Repeat Mode
789
Single Sweep Mode
791
Repeat Sweep Mode 0
793
External Sensor
795
Interrupt
796
Notes on A/D Converter
797
Analog Input Pin
797
Pin Configuration
797
Register Access
797
A/D Conversion Start
797
A/D Operation Mode Change
797
State When Forcibly Terminated
798
A/D Open-Circuit Detection Assist Function
798
Detecting Completion of A/D Conversion
798
27. D/A Converter
799
Introduction
799
Registers
800
D/A0 Register (DA0)
800
D/A Control Register (DACON)
800
Operations
801
Notes on D/A Converter
802
When Not Using the D/A Converter
802
28. CRC Calculator
803
Introduction
803
Registers
804
SFR Snoop Address Register (CRCSAR)
804
CRC Mode Register (CRCMR)
805
CRC Data Register (CRCD)
805
CRC Input Register (CRCIN)
805
Operations
806
Basic Operation
806
CRC Snoop
806
Setting Procedures
807
29. Flash Memory
809
Introduction
809
Memory Map
811
Registers
812
Flash Memory Control Register 0 (FMR0)
812
Flash Memory Control Register 1 (FMR1)
815
Flash Memory Control Register 2 (FMR2)
816
Flash Memory Control Register 3 (FMR3)
817
Flash Memory Control Register 6 (FMR6)
818
Optional Function Select Area
819
Optional Function Select Address 1 (OFS1)
820
Optional Function Select Address 2 (OFS2)
821
Flash Memory Rewrite Disable Function
822
Boot Mode
822
User Boot Mode
822
User Boot Function
822
CPU Rewrite Mode
826
EW0 Mode
827
EW1 Mode
833
Operating Speed
839
Data Protect Function
839
Suspend Function
840
Software Commands
842
Read Array Command
842
Read Status Register Command
843
Program Command
844
Status Register
849
Full Status Check
850
Standard Serial I/O Mode
852
ID Code Check Function
853
Forced Erase Function
854
Standard Serial I/O Mode Disable Function
854
Standard Serial I/O Mode 1
855
Input Level
856
Standard Serial I/O Mode 2
857
29.10 Parallel I/O Mode
858
29.10.1 ROM Code Protect Function
858
29.11 Notes on Flash Memory
859
29.11.1 OFS1 Address, OFS2 Address, and ID Code Storage Address
859
29.11.2 Reading Data Flash
859
29.11.3 CPU Rewrite Mode
860
29.11.4 User Boot
862
PROM Emulation Data Flash
863
Overview
863
Registers
864
E2Dataflash Address Register (E2FA)
864
E2Dataflash Command Register (E2FI)
865
E2Dataflash Data Register (E2FD)
865
E2Dataflash Mode Register (E2FM)
866
E2Dataflash Control Register (E2FC)
867
E2Dataflash Status Register 1 (E2FS1)
867
E2Dataflash Status Register 0 (E2FS0)
868
Block Configuration
869
Operational Procedures
870
Full Status Check
873
Error Processing Procedures
873
Interrupt
874
Notes on EPROM 2 PROM Eprommulation Data Flash
875
Relation with CPU Rewrite Mode
875
CPU Clock When Rewriting
875
Clock Transition
875
31. Electrical Characteristics
876
Electrical Characteristics (J-Version, Common to 3 V and 5 V)
876
Absolute Maximum Rating
876
Recommended Operating Conditions
877
A/D Conversion Characteristics
879
D/A Conversion Characteristics
880
Flash Memory Electrical Characteristics
881
EPROM Emulation Data Flash
884
Voltage Detector and Power Supply Circuit Electrical Characteristics
885
Oscillator Electrical Characteristics
887
Electrical Characteristics (J-Version, VCC = 5 V)
888
Electrical Characteristics
888
Timing Requirements (Peripheral Functions and Others)
890
External Clock Input
890
Serial Interface
895
Serial Bus Interface
897
Electrical Characteristics (J-Version, VCC = 3 V)
901
Electrical Characteristics
901
External Clock Input
903
Serial Interface
908
Serial Bus Interface
910
External Clock Input
928
Serial Interface
933
Serial Bus Interface
935
Usage Notes
952
Notes on Noise
952
Register Settings
953
CPU Clock
959
Notes on Interrupts
964
Usage Notes
965
Changing Operating Modes
971
Usage Notes
978
Special Mode
984
Register Access
991
Revision History
1003

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