Renesas MuPD70F3551 Microcontroller Manuals

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Renesas MuPD70F3551 User Manual (2661 pages)

Preliminary Document, 32-bit Microcontroller

Brand: Renesas | Category: Microcontrollers | Size: 18 MB

Notice

2
General Precautions in the Handling of MPU/MCU Products

4
Table of Contents

5
How to Use this Manual

30
Purpose and Target Readers

30
- Special Notations
  30
- Electrical Specifications
  30
- Additional Documents
  30
Content of this Manual

31
Notation of Numbers and Symbols

32
Diagrams

33
Trademarks

33
Functional Modules Descriptions

34
- Functional Modules Abbreviation Convention
  34
- Product Specific Features
  34
Further Information

39
Chapter 1 Introduction

40
V850E2/Fx4 Product Line Overview

40
- V850E2/Fx4 Products Features
  40
Related Documents

52
Ordering Information

53
Product Name Register

54
Chapter 2 Port Functions

55
V850E2/Fx4 Port Features

55
Overview

56
- Terms
  57
- Pin Function Configuration
  58
- Pin Data Input/Output
  60
- Port Control Logic Diagram
  62
Port Group Configuration Registers

63
V850E2/Fx4 Port Group Configuration

84
- Port Register Protection Clusters
  84
- Common Port Functions
  85
- V850E2/FG4 Port Functions
  89
- V850E2/FJ4 Port Functions
  96
- V850E2/FK4 Port Functions
  106
- V850E2/FL4 Port Functions
  117
- Non-Port Input/Output Signals
  130
- Alphabetic Pin Function List
  131
- Port and Pin Functions in Stand-By Modes
  140
- Port and Pin Functions During and after Reset
  140
- Recommended Connection of Unused Pins
  141
Port Filters

143
- Port Filters Assignment
  143
- Port Filters Clock Supply
  147
- Port Filters Reset
  149
Port Filters Functional Description

150
- Analog Filters
  150
- Digital Filters
  153
- Filter Control Registers
  157
Chapter 3 CPU System Functions

161
Overview

161
Peripheral Protection Unit

163
Timing Supervision Unit

167
Memory Protection Unit (MPU)

167
CPU Access Bus Structures and Latencies

168
- CPU Subsystem Modules Access
  168
- PBUS Modules Access
  169
- PBUS Synchronizer
  171
- Module Wait Clocks Insertion
  173
CPU Subsystem

174
- Power and Clock Domain
  174
- CPU Subsystem Busses Overview
  175
- V850E2/FG4 and V850E2/FJ4 CPU Subsystem
  176
- V850E2/FK4 and V850E2/FL4 CPU Subsystem
  179
- V850E2 System Manual
  182
Data Flash Wait Cycle Control

183
Operation Modes

184
- Normal Operation Mode
  184
- Flash Programming Mode
  184
- Boundary Scan Mode
  185
Mode Pins and JP0 Connections

186
- Normal Operation Mode
  187
- Debug Mode
  188
- Flash Programming Mode
  190
- Boundary Scan Mode
  191
Address Space

192
- CPU Data Address and Physical Program Address Space
  192
- Program and Data Space
  192
V850E2/Fx4 CPU Address Map

194
- DMA Address Map
  194
- V850E2/Fx4 Memory Maps
  195
- Memory Areas
  201
Back-Up RAM (BURAM)

205
- Back-Up RAM Protection
  206
Write Protected Registers

209
Chapter 4 External Memory Controller (MEMC)

222
V850E2/Fx4 MEMC Features

222
Overview

223
- Operation Mode, Connectable Memory Types
  223
- Chip Select Output Function
  223
- Operation Setting Function
  223
- Bus Sizing Function
  223
- Data Endian Setting Function
  223
- Programmable Wait Setting Functions
  224
- External Wait Function
  224
Registers

225
Bus Cycle Type Setting Function

237
- Multiplexed Bus Mode
  237
Bus Control Function

239
Wait Functions

241
- Programmable Data Wait Function
  242
- External Wait Function
  243
- Data Setup Wait Function
  244
- Data Hold Wait Function
  245
- Address Setup Wait Function
  246
- Address Hold Wait Function
  247
- Idle Insertion Function
  248
Memory Connection Examples

249
- Multiplexed Bus Mode Connection Example
  249
Data Flow

250
- Data Flow During Byte Access
  251
Chapter 5 Interrupt Functions

261
Exceptions and Interrupts

261
- Exception Handler Switching
  263
V850E2/Fx4 Exceptions

264
- Memory Error Exceptions MEP
  264
- System Error Exceptions SYSERR
  265
- Code Flash Error Correction
  269
V850E2/Fx4 Interrupt Requests

273
External Interrupts

305
- Edge Detection Configuration
  305
- External Interrupts as Trigger and Wake-Up Signals
  306
Interrupt Controller Control Registers

307
Interrupt Acknowledgment and Restoring

317
Interrupt Operation

324
Exception Handler Address Switching Function

331
Chapter 6 DMA Controller (DMAC)

332
V850E2/Fx4 DMA Features

332
Definition of Terms

335
General

335
- DMA Controller (DMAC) Function
  335
- DMA Trigger Factor Register (DTFR) Function
  335
- DMA Access Memory Map
  336
- Prioritization of Channels
  336
- Stand-By Function
  336
DMAC Function

337
- Features
  337
- DMAC Setting Registers
  339
- Enabling or Disabling Writing Control Registers
  344
DMA Control Registers

345
DMAC Function Details

368
- DMAC Transfer Setting Flow
  368
- DMAC Transfer Modes
  370
- DMAC Channel Priority Control
  373
- Valid DMA Transfer Request Conditions
  374
- Next Address Function
  375
- Aborting/Resuming DMA Transfer
  376
- Error Response Support
  377
- Stand-By Support
  377
DTFR Function

378
- Features
  378
DTFR Control Registers

379
Chapter 7 Flash Memory

382
Code Flash Memory Overview

383
- Code Flash Memory Features
  383
- Code Flash Memory Map
  384
- Data Flash Memory Map
  386
Code Flash Memory Functional Outline

387
- Code Flash Memory Erasure and Rewrite
  390
Data Flash Memory

391
- Data Flash Memory Features
  391
- Data Flash Reading and Writing
  391
Flash Programming with Flash Programmer

392
- Programming Environment
  392
- Communication Modes
  393
- Pin Connection with Flash Programmer PG-FP5
  394
- Flash Memory Programming Control
  395
Code Flash Self-Programming

402
Flash Mask Options

410
- OPBT0 - Flash Mask Option Register 0
  411
Chapter 8 Data CRC Function a (DCRA)

412
V850E2/Fx4 DCRA Features

412
Functional Overview

414
Functional Description

415
Registers

416
- DCRA Registers Overview
  416
- DCRA Registers Details
  417
Chapter 9 Clock Controller

420
Clock Controller Overview

421
General Description of Clock Generation and Control

424
- Clock Generators
  427
- Clock Selectors
  429
Clock Generators

431
Clock Selection

444
Clock Domain Figures

464
Frequency Output Function (FOUT)

473
- FOUT Clock Divider (FOUTDIV)
  474
Clock Monitor a (CLMA)

476
- V850E2/Fx4 CLMA Features
  476
- CLMA Enable and Start-Up Options
  479
- Functional Overview
  481
- Functional Description
  482
- Clock Monitor Registers
  486
Clock Controller Registers

492
- Writing to Protected Registers
  492
- Clock Controller Registers Overview
  492
- Clock Generators Registers
  494
- Clock Selector Control Register
  511
Chapter 10 Stand-By Controller (STBC)

515
V850E2/Fx4 Stand-By Controller Features

515
Stand-By Controller Functions

519
- Stand-By Controller Signal Connections
  520
- Stand-By Modes Control
  521
- Stand-By Modes Overview
  523
- Clock Generators in Stand-By
  524
- Wake-Up
  525
- I/O Buffer Control
  533
- Mode Transitions
  534
Stand-By Mode Entry and Exit Example Flows

535
Stand-By Controller Registers

556
Chapter 11 Code Protection and Security

568
Overview

568
Flash Programmer and Self-Programming Protection

569
On-Chip Debug Interface Protection

570
- On-Chip Debug Enable Flag
  570
- On-Chip Debug ID Code
  571
- On-Chip Debug Protection Levels Summary
  571
- On-Chip Debug Control Registers
  572
Chapter 12 Reset Controller

575
Functional Overview

575
Functional Description

579
- Reset Flags
  579
- Power-On Clear Reset (POCRES)
  580
- Low-Voltage Indicator (LVI)
  581
- Very-Low-Voltage Indicator (VLVI)
  583
- External RESET
  585
- Watchdog Timers Reset (Wdtanres)
  587
- Software Reset (SWRES)
  587
- Clock Monitors Reset (Clmanres)
  587
- Debugger Reset (DBRES)
  587
Registers

588
Chapter 13 OS Timer (OSTM)

595
V850E2/Fx4 OSTM Features

595
Functional Overview

597
Functional Description

597
- Count Clock
  598
- Interrupt Request Generation
  598
- Starting and Stopping the Timer
  599
- Interval Timer Mode
  599
- Free-Run Compare Mode
  603
OS Timer Registers

605
- OS Timer Registers Overview
  605
- OS Timer Registers Details
  606
Chapter 14 Window Watchdog Timer a (WDTA)

611
V850E2/Fx4 WDTA Features

611
WDTA Start-Up Options

614
- V850E2/Fx4 Wdtan Start Modes
  615
Functional Overview

616
Functional Description

617
- WDTA after Reset Release
  618
- WDTA Trigger
  621
- Error Detection
  622
- 75% Interrupt Output
  624
- Window Function
  625
Application Hint: Evaluation of the Watchdog Status

626
WDTA Registers

627
- WDTA Registers Overview
  627
- WDTA Registers Details
  628
Chapter 15 Timer Array Unit a (TAUA)

634
V850E2/Fx4 TAUA Features

634
TAUA Input Selection

638
- TAUA0 Input Selection
  638
Functional Overview

645
- Terms
  647
Functional Description

648
General Operating Procedure

650
Operation Modes

651
Concepts of Synchronous Channel Operation

652
- Rules
  652
- Simultaneous Start and Stop of Synchronous Channel Counters
  654
Simultaneous Rewrite

655
- Introduction
  655
- How to Control Simultaneous Rewrite
  657
- Other General Rules of Simultaneous Rewrite
  658
- Types of Simultaneous Rewrite
  659
Channel Output Modes

667
Start Timing of Operating Modes

677
Tauanttoutm Output and Inttauanim Generation When Counter Starts or Restarts

679
Interrupt Generation Upon Overflow

680
- Capture Mode
  681
- Capture and One Count Mode
  682
- Count Capture Mode
  683
- Capture and Gate Count Mode
  684
Tauanttinm Edge Detection

685
Assigning DMA Window Addresses

686
Independent Channel Operation Functions

687
Independent Channel Interrupt Functions

687
- Interval Timer Function
  688
- Tauanttinm Input Interval Timer Function
  695
- Delay Count Function
  701
- One-Pulse Output Function
  706
Independent Channel Signal Measurement Functions

711
Independent Channel Real-Time Functions

754
- Real-Time Output Function Type 1
  755
- Real-Time Output Function Type 2
  762
Independent Channel Simultaneous Rewrite Functions

769
- Simultaneous Rewrite Trigger Generation Function Type 1
  770
- Simultaneous Rewrite Trigger Generation Function Type 2
  776
Independent Channel One-Phase PWM Function

782
- One-Phase PWM Output Function
  783
Other Independent Channel Functions

790
Synchronous Channel Operation Functions

811
Synchronous PWM Signal Functions Triggered at Regular Intervals

811
- PWM Output Function
  812
- Trigger Start PWM Output Function
  823
- Delay Pulse Output Function
  834
- AD Conversion Trigger Output Function Type 1
  850
Synchronous PWM Signal Functions Triggered by an External Signal

852
- One-Shot Pulse Output Function
  853
- Offset Trigger Output Function
  865
Synchronous Triangle PWM Functions

875
Synchronous Real-Time Output Functions

912
Synchronous Non-Complementary and Complementary Functions

946
Other Synchronous Channel Functions

992
- Interrupt Culling Function
  992
Registers

1001
- Tauan Registers Overview
  1001
- Tauan Prescaler Registers Details
  1003
- Tauan Control Registers Details
  1006
- Tauan Output Registers Details
  1016
- Tauan Channel Output Level Registers Details
  1022
- Tauan Simultaneous Rewrite Register Details
  1023
- Tauan DMA Window Registers
  1026
- Tauan Emulation Register
  1028
Chapter 16 Timer Array Unit B (TAUB)

1029
V850E2/Fx4 TAUB Features

1029
TAUB Input Selection

1034
- TAUB1TTIN[7:0] Input Selections
  1034
Functional Overview

1036
- Terms
  1038
Functional Description

1039
General Operating Procedure

1041
Operation Modes

1042
Concepts of Synchronous Channel Operation

1043
- Rules
  1043
- Simultaneous Start and Stop of Synchronous Channel Counters
  1045
Simultaneous Rewrite

1046
- Introduction
  1046
- How to Control Simultaneous Rewrite
  1048
- Other General Rules of Simultaneous Rewrite
  1049
- Types of Simultaneous Rewrite
  1050
Channel Output Modes

1056
Start Timing of Operating Modes

1063
- Interval Timer Mode, Judge Mode, Capture Mode, up down Count Mode
  1063
- Event Mode
  1064
- All Other Operating Modes
  1064
Taubnttoutm Toggle and Inttaubnim Generation When Counter Start Is Triggered (MD0-Bit)

1065
Taubnttinm Edge Detection

1067
Independent Channel Operation Functions

1068
Independent Channel Interrupt Functions

1068
- Interval Timer Function
  1069
- Taubnttinm Input Interval Timer Function
  1077
- One-Pulse Output Function
  1083
Independent Channel Signal Measurement Functions

1088
Independent Channel Simultaneous Rewrite Functions

1131
- Simultaneous Rewrite Trigger Generation Function Type 1
  1132
Other Independent Channel Functions

1138
- External Event Count Function
  1139
- Clock Divide Function
  1146
- Taubnttinm Input Position Detection Function
  1153
Synchronous Channel Operation Functions

1159
Synchronous PWM Signal Functions Triggered at Regular Intervals

1159
- PWM Output Function
  1160
- Delay Pulse Output Function
  1171
- AD Conversion Trigger Output Function Type 1
  1187
Synchronous PWM Signal Functions Triggered by an External Signal

1189
- One-Shot Pulse Output Function
  1190
Synchronous Triangle PWM Functions

1202
Registers

1239
- Taubn Registers Overview
  1239
- Taubn Prescaler Registers Details
  1240
- Taubn Control Registers Details
  1242
- Taubn Output Registers Details
  1252
- Taubn Channel Output Level Registers Details
  1255
- Taubn Simultaneous Rewrite Register Details
  1256
- Taubn Emulation Register
  1259
Chapter 17 Timer Array Unit C (TAUC)

1260
V850E2/Fx4 TAUC Features

1260
Functional Overview

1266
- Terms
  1267
Functional Description

1268
General Operating Procedure

1269
Operation Modes

1270
Concepts of Synchronous Channel Operation

1271
- Rules
  1271
- Simultaneous Start and Stop of Synchronous Channel Counters
  1273
Simultaneous Rewrite

1274
- Introduction
  1274
- How to Control Simultaneous Rewrite
  1275
- Other General Rules of Simultaneous Rewrite
  1276
- Types of Simultaneous Rewrite
  1277
Channel Output Modes

1281
Start Timing of Operating Modes

1286
- Interval Timer Mode
  1286
- Event Mode
  1287
Taucnttoutm Toggle and Inttaucnim Generation When Counter Start Is Triggered (MD0-Bit)

1288
Independent Channel Operation Functions

1289
Independent Channel Interrupt Functions

1289
- Interval Timer Function
  1290
Independent Channel Simultaneous Rewrite Functions

1298
- Simultaneous Rewrite Trigger Generation Function Type 1
  1299
Synchronous PWM Signal Functions Triggered at Regular Intervals

1305
- PWM Output Function
  1306
Registers

1317
- Taucn Registers Overview
  1317
- Taucn Prescaler Registers Details
  1318
- Taucn Control Registers Details
  1320
- Taucn Output Registers Details
  1325
- Taucn Channel Output Level Registers Details
  1326
- Taucn Simultaneous Rewrite Register Details
  1327
- Taucn Emulation Register
  1330
Chapter 18 Timer Array Unit J (TAUJ)

1331
V850E2/Fx4 TAUJ Features

1331
TAUJ Input Selection

1335
- TAUJ0/TAUJ1 Input Selection
  1335
Functional Overview

1341
- Terms
  1343
Functional Description

1344
General Operating Procedure

1346
Operation Modes

1347
Concepts of Synchronous Channel Operation

1348
- Rules
  1348
- Simultaneous Start and Stop of Synchronous Channel Counters
  1350
Simultaneous Rewrite

1351
- Introduction
  1351
- How to Control Simultaneous Rewrite
  1352
- Other General Rules of Simultaneous Rewrite
  1353
- Simultaneous Rewrite Procedure
  1354
Channel Output Modes

1356
Start Timing of Operating Modes

1361
- Interval Timer Mode, Capture Mode
  1361
- Other Operating Modes
  1362
Taujnttoutm Output and Inttaujnim Generation When Counter Starts or Restarts

1363
Interrupt Generation Upon Overflow

1364
- Capture Mode
  1365
- Capture and One Count Mode
  1366
- Count Capture Mode
  1367
- Capture and Gate Count Mode
  1368
Taujnttinm Edge Detection

1369
Independent Channel Operation Functions

1370
Independent Channel Interrupt Functions

1370
- Interval Timer Function
  1371
- Taujnttinm Input Interval Timer Function
  1378
Independent Channel Signal Measurement Fuctions

1384
Other Independent Channel Functions

1414
- Taujnttinm Input Position Detection Function
  1415
Synchronous PWM Signal Functions Triggered at Regular Intervals

1421
- PWM Output Function
  1422
Registers

1433
- Taujn Registers Overview
  1433
- Taujn Prescaler Registers Details
  1434
- Taujn Control Registers Details
  1437
- Taujn Output Registers Details
  1447
- Taujn Simultaneous Rewrite Register Details
  1450
- Taujn Emulation Register
  1452
Chapter 19 Real-Time Clock (RTCA)

1453
V850E2/Fx4 RTCA Features

1453
Functional Overview

1456
Functional Description

1457
- Operation Modes
  1458
- Clock Counter Format
  1458
- Fixed Interval Interrupt Function
  1459
- Alarm Interrupt Function
  1460
- Clock Error Correction
  1461
Registers

1465
- RTCA Registers Overview
  1465
- RTCA Control Registers Details
  1467
- RTCA Sub-Counter Registers Details
  1471
- RTCA Clock Counter and Buffer Registers Details
  1475
- RTCA Special Counter and Buffer Registers Details
  1490
- RTCA Alarm Setting Registers Details
  1494
- RTCA Emulation Register Details
  1497
Procedures for Setup, Writing and Reading

1498
- Initial Setting of the RTCA
  1498
- Updating Clock Counters
  1500
- Reading Clock Counters
  1501
- Reading Rtcansrbu
  1504
- Writing to Rtcansubu
  1505
- Writing to Rtcanscmp
  1506
Timing Diagrams

1507
Chapter 20 Motor Control

1510
Basic Structure of Motor Control

1510
V850E2/Fx4 Timer Motor Control Function (TAPA) Features

1512
TAPA0 Hi-Z Control Input Selection

1515
Functional Overview

1517
- Block Diagram
  1517
- Peak and Valley Interrupts - Peak and Valley of Timer Counter
  1518
Registers

1519
- Registers Overview
  1519
- Registers Details
  1520
Basic Functions

1525
Three-Phase PWM Output with Dead Time

1537
- Functional Overview
  1537
- Configuration
  1537
- Operation Example
  1540
- Setup Flow
  1549
- Example of Setting up Operation Functions
  1551
- Registers
  1558
High-Accuracy Triangle PWM Output with Dead Time

1564
- Functional Overview
  1564
- Configuration
  1565
- Operation Example
  1568
- Setup Flow
  1581
- Example of Setting up Operation Functions
  1583
- Registers
  1591
Delay Pulse Output with Dead Time

1603
- Functional Overview
  1603
- Configuration
  1603
- Operation Example
  1606
- Setup Flow
  1612
- Example of Setting up Operation Functions
  1615
- Registers
  1622
Chapter 21 Encoder Timer

1628
Basic Structure of Encoder Timer

1628
V850E2/Fx4 Encoder Timer (ENCA) Features

1630
ENCA Functional Overview

1633
- Block Diagram
  1634
- Preliminary Knowledge for Understanding Basic Specifications
  1635
ENCA Control Registers

1636
ENCA Functional Description

1647
- Timer Counter Operation
  1647
- Up/Down Control of Timer Counter
  1649
- Timer Counter Clear Control by Encoder Input
  1653
- Functions of Encanccr0
  1654
- Functions of Encanccr1
  1655
ENCA Setting Sequences

1658
- Encoder Timer Setting Procedure
  1658
A/D Trigger Encoder Capture

1661
- Functional Overview
  1661
- Configuration
  1661
- Operation Example
  1662
- Setup Flow
  1663
- Example of Setting up Operation Functions
  1664
- Registers
  1666
Synchronized Timer Operation

1668
- Functional Overview
  1668
- Configuration
  1668
- Operation Example
  1669
- Setup Flow
  1670
- Setting up Operation Functions
  1670
- Registers
  1671
Trigger Pulse Width Measurement

1673
- Functional Overview
  1673
- Configuration
  1673
- Operation Example
  1675
- Setup Flow
  1678
- Example of Setting up Operation Functions
  1681
- Registers
  1684
Chapter 22 PWM Diagnostic

1690
PWM Diagnostic Functional Overview

1690
- Basic Concept and Definitions
  1690
- PWM Generation
  1691
- Channel-To-Channel Delay
  1692
- A/D Converter Trigger Delay
  1693
- Synchronous PWM Groups Multiplexer and A/D Converter Control
  1694
- A/D Converter Conversion Result Memory Transfer
  1696
- Diagnostic Value Evaluation
  1696
PWM Delay (DLYA)

1698
- DLYA Features
  1698
- PWM Delay (DLYA) Bypass Control
  1702
- Functional Overview
  1704
- Registers
  1705
- Procedure for Setup
  1710
- Timing Diagrams
  1710
PWM Diagnostic Timing and Trigger Generation (PMCA)

1711
- Features
  1711
- Connections
  1714
- Functional Overview
  1721
- Registers
  1723
- Procedures for Setup, Writing and Reading
  1727
Chapter 23 Asynchronous Serial Interface E (URTE)

1728
V850E2/Fx4 Urten Features

1728
Functional Overview

1733
Configuration

1734
URTE Registers

1735
Interrupt Request Signals

1751
Operation

1753
- Data Formats
  1753
- BF Transmission/Reception Format
  1755
- BF Transmission
  1757
- BF Reception
  1758
- Transmission Data Consistency Check
  1760
- Urten Transmission
  1761
- Continuous Transmission Procedure
  1762
- Urten Reception
  1764
- Reception Errors
  1766
- Parity Types and Operations
  1767
- Digital Receive Data Noise Filter
  1768
Baud Rate Generator

1769
Chapter 24 LIN Master Controller (LMA)

1770
V850E2/Fx4 Lman Features

1770
LIN Master Scheduler Counters (CNTA)

1776
- Cntam Registers
  1776
Functional Overview

1778
Functional Description

1780
- UART through Mode
  1780
- UART Buffer Mode
  1781
- LIN Master Modes
  1787
- Automatic Checksum Function
  1799
- Scheduler
  1800
Lman Registers

1805
- Lman Registers Overview
  1805
- Lman Registers Details
  1807
Chapter 25 CAN Controller (FCN)

1822
V850E2/Fx4 FCN Features

1822
FCN0 and FCN1 Connection

1827
CAN Baudrate and Time Quanta

1829
Features

1830
- Overview of Functions
  1830
- Configuration
  1832
Internal Registers of CAN Controller

1833
- CAN Controller Configuration
  1833
- CAN Controller Registers Overview
  1835
- Register Bit Configuration
  1837
Bit Set/Clear Function

1842
Control Registers

1844
- CAN Controller Global Registers
  1844
- CAN Channel Registers
  1853
- Message Buffer Registers
  1875
CAN Controller Initialization

1884
- Initialization of CAN Controller
  1884
- Initialization of Message Buffer
  1884
- Redefinition of Message Buffer
  1884
- Transition from Initialization Mode to Operation Mode
  1886
Message Reception

1887
- Receive Data Read
  1888
- Receive History List Function
  1889
- Mask Function
  1891
- Multi Buffer Receive Block Function
  1893
- Remote Frame Reception
  1894
Message Transmission

1896
- Transmit History List Function
  1898
- Automatic Block Transmission (ABT)
  1900
- Transmission Abort Process
  1902
- Remote Frame Transmission
  1903
Power Saving Modes

1904
- CAN Controller Sleep Mode
  1904
- CAN Controller Stop Mode
  1907
- Example of Using Power Saving Modes
  1908
Interrupt Function

1909
Diagnosis Functions and Special Operational Modes

1910
- Receive-Only Mode
  1910
- Single-Shot Mode
  1911
- Self-Test Mode
  1912
- Receive/Transmit Operation in each Operation Mode
  1913
Time Stamp Function

1914
Baudrate Settings

1915
- Baudrate Setting Conditions
  1915
- Clock Prescaler and Baudrate Generator Settings
  1919
Operation of the CAN Controller

1921
- Initialization
  1921
- Message Transmission
  1927
- Message Reception
  1941
- Power Save Modes
  1946
Chapter 26 Diagnostic CAN Controller (DCN)

1953
V850E2/Fx4 DCN Features

1953
Diagnostic CAN Controller (DCN) Baudrate and Time Quanta

1956
Introduction

1957
Overview of Functions

1959
Architecture

1960
- CPU Interface
  1961
- Global Module Control
  1961
- CAN Interrupt Generator
  1961
- Message Control (MSG Ctrl)
  1961
- Arbitration Logic
  1962
- RXONLY_CH CAN Machine
  1962
- DIAG_CH CAN Machine
  1963
Module Initialisation and Control

1964
Module Interrupts

1985
Message Reception of RXONLY Channel

1989
- Principal Reception Process
  1989
- Reception History
  1989
- Reception of Remote Frames
  1990
Message Transmission

1990
- Receive-Only Mode
  1991
Operational Modes of RXONLY_CH

1993
- Mirror Mode
  1996
- Mirror Mode with TIF
  1998
Transitions for Buffer Assignment

1999
Register Description

2002
- Register Bit Configuration
  2002
- DCN Global Registers
  2010
- DCN Module Registers
  2016
- DCN Message Buffers Registers
  2033
Chapter 27 Clocked Serial Interface G (CSIG)

2039
V850E2/Fx4 CSIG Features

2039
- Data Consistency Check
  2043
Functional Overview

2044
Functional Description

2046
- Master/Slave Mode
  2046
- Master/Slave Connections
  2047
- Transmission Clock Selection
  2049
- Data Transfer Modes
  2050
- Data Length Selection
  2051
- Serial Data Direction Select Function
  2053
- Communication in Slave Mode
  2054
- CSIG Interrupts
  2055
- Handshake Function
  2057
- Loop-Back Mode
  2060
- Error Detection
  2061
CSIG Control Registers

2064
Operating Procedure Example

2076
Chapter 28 Clocked Serial Interface H (CSIH)

2078
V850E2/Fx4 CSIH Features

2078
- Data Consistency Check
  2082
Functional Overview

2083
Functional Description

2085
- Operating Modes (Master/Slave)
  2086
- Master/Slave Connections
  2087
- Chip Selection (CS) Features
  2089
- The Job Concept
  2091
- Chip Select Timing Details
  2092
- Transmission Clock Selection
  2093
- CSIH Buffer Memory
  2094
- Data Transfer Modes
  2096
- Data Length Selection
  2097
- Serial Data Direction Selection
  2100
- Communication in Slave Mode
  2101
- CSIH Interrupt Requests
  2102
- Handshake Function
  2110
- Error Detection
  2113
- Loop-Back Mode
  2122
CSIH Control Registers

2123
- CSIH Registers Details
  2124
Operating Procedures

2147
- Procedures in Direct Access Mode
  2147
- Procedures in Transmit-Only Buffer Mode
  2152
- Procedures in Dual Buffer Mode
  2156
- Procedures in FIFO Mode
  2162
Chapter 29 I2C Interface (IICB)

2166
V850E2/Fx4 IICB Features

2166
I2C Interface Port Settings

2168
Functional Overview

2169
C Bus Mode Functions

2171
- Pin Configuration
  2171
I 2 C Bus Definition

2172
- Start Condition
  2173
- Addresses
  2173
- Extension Code
  2174
- Transfer Direction Specification
  2174
- Acknowledge (ACK)
  2175
- Data
  2176
- Stop Condition
  2176
- Wait State
  2177
- Arbitration
  2179
Registers

2180
Operation

2204
- Single Transfer Mode
  2204
- Continuous Transfer Mode
  2209
- Arbitration
  2214
- Entering and Exiting Wait State
  2215
- Extension Code
  2220
Interrupt Request Signals

2221
- Single Transfer Mode
  2222
- Continuous Transfer Mode
  2225
Interrupt Outputs and Statuses

2231
Setting Sequence

2285
- Single Master Environment
  2285
- Multi-Master Environment
  2289
Chapter 30 Flexray TM (FLX)

2297
V850E2/Fx4 Flxn Features

2297
E-Ray Overview

2300
- Conventions
  2300
- Definition
  2300
- References
  2300
- Terms and Abbreviations
  2300
- Functional Overview
  2301
- Block Diagram
  2303
- Host CPU Interface Timing
  2305
- Reset Timing
  2305
Programmer's Model

2306
- Register Map
  2306
- E-Ray Registers
  2311
- Special Registers
  2316
- Interrupt Registers
  2323
- CC Control Registers
  2344
- CC Status Registers
  2368
- Message Buffer Control Registers
  2385
- Message Buffer Status Registers
  2391
- Identification Registers
  2404
- Input Buffer
  2406
- Output Buffer
  2415
Functional Description

2426
- Communication Cycle
  2426
- Communication Modes
  2428
- Clock Synchronization
  2429
- Error Handling
  2431
- Communication Controller States
  2433
- Network Management
  2448
- Filtering and Masking
  2448
- Transmit Process
  2451
- Receive Process
  2454
- FIFO Function
  2456
- Message Handling
  2458
- Message RAM
  2468
- Module Interrupt
  2477
Appendix

2479
- Assignment of Flexray Configuration Parameters
  2479
Cautions

2481
Chapter 31 Random Number Generator a (RNGA)

2489
V850E2/Fx4 RNGA Features

2489
Functional Overview

2491
Functional Description

2491
- RNGA Status
  2491
- RNGA Start and Reset
  2491
Registers

2492
- Registers Overview
  2492
- Registers Details
  2492
Chapter 32 Key Return Function (KR)

2493
V850E2/Fx4 KR Features

2493
Functional Overview

2495
Functional Description

2496
- Interrupt Request Krntikr
  2496
Registers

2497
- Key Return Function Registers Overview
  2497
- Key Return Function Registers Details
  2497
Chapter 33 A/D Converter a (ADCA)

2498
V850E2/Fx4 ADCA Features

2498
H/W Trigger Expansion

2502
- Adcan H/W Trigger Selection
  2502
- Adcan H/W Trigger Edge Selection
  2503
- ADCA0 H/W Trigger Selections
  2504
- ADCA1 H/W Trigger Selections
  2509
Functional Overview

2511
Cautions

2513
Functional Description

2513
- Basic Operation
  2515
- Clock Usage
  2516
- Channels and Channel Groups
  2516
- A/D Conversion Modes
  2518
- Starting A/D Conversion (Start Trigger Modes)
  2521
- Stopping A/D Conversion
  2523
- Stand-By Mode
  2525
- Pausing and Resuming A/D Conversion (ADCHALT Mode)
  2525
- Resolution, Sampling and Conversion Times
  2526
- Interrupt Generation
  2527
- Storage of A/D Conversion Result
  2528
- Result Check Functions
  2531
- Channel S&H Function
  2533
- Self-Diagnosis Functions
  2540
- Discharge Function
  2547
- Buffer Amplifier Function
  2548
- Stabilization Control
  2548
Registers

2549
- ADCA Registers Overview
  2549
- Control Registers Details
  2551
- Conversion Status Registers
  2562
- S/W Trigger Registers Details
  2566
- ADCA Conversion Result Registers Details
  2568
- A/D Conversion Result Upper/Lower Limit Comparison Registers Details
  2575
- Diagnose Functions Registers
  2579
- Emulation Register
  2582
Chapter 34 Voltage Comparator (VCPC)

2583
V850E2/Fx4 VCPC Features

2583
Overview

2586
- Description
  2586
- Stand-By Mode
  2588
Voltage Comparator Registers

2589
Chapter 35 On-Chip Debug Unit (OCD)

2592
V850E2/Fx4 On-Chip Debug Features

2592
- Modules Behaviour During Emulation Break
  2592
- Signal Masking
  2594
Functional Overview

2594
Emulation Break Control

2597
Connection with On-Chip Debug Emulator

2598
Cautions on Using On-Chip Debugging

2598
Chapter 36 Boundary Scan

2599
Outline

2599
JTAG Interface

2599
Entering Boundary Scan Mode

2599
Boundary Scan Features

2600
Boundary Scan Applicable Pins

2600
DID - Boundary Scan ID Register

2601
Chapter 37 Power Supply

2602
Power Supply Pins Naming

2602
Power Supply Schemes

2603
- V850E2/Fx4-M1 and -M2 Products
  2603
- V850E2/FG4 Power Supply Scheme
  2605
- V850E2/FJ4 Power Supply Scheme
  2606
- V850E2/FK4 Power Supply Scheme
  2607
- V850E2/FL4 Power Supply Scheme
  2608
Power-Up and down Procedures

2610
- Power Sequencer
  2612
- Initial Power-Up and Final Power-Down
  2614
- DEEPSTOP Entry and Wake-Up
  2615
- Other Power Supplies
  2619
Revision History

2621
Revision History Rev. 0.04

2624
Revision History Rev. 1.00

2626
Revision History Rev. 1.01

2630
Revision History Rev. 1.02

2631
Revision History Rev. 1.03

2633
Index

2635

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Renesas MuPD70F3551 Microcontroller Manuals

Renesas MuPD70F3551 User Manual (2661 pages)

Table of Contents

Notice

General Precautions in the Handling of MPU/MCU Products

Table of Contents

How to Use this Manual

Purpose and Target Readers

Content of this Manual

Notation of Numbers and Symbols

Diagrams

Trademarks

Functional Modules Descriptions

Further Information

Chapter 1 Introduction

V850E2/Fx4 Product Line Overview

Related Documents

Ordering Information

Product Name Register

Chapter 2 Port Functions

V850E2/Fx4 Port Features

Overview

Port Group Configuration Registers

V850E2/Fx4 Port Group Configuration

Port Filters

Port Filters Functional Description

Chapter 3 CPU System Functions

Overview

Peripheral Protection Unit

Timing Supervision Unit

Memory Protection Unit (MPU)

CPU Access Bus Structures and Latencies

CPU Subsystem

Data Flash Wait Cycle Control

Operation Modes

Mode Pins and JP0 Connections

Address Space

V850E2/Fx4 CPU Address Map

Back-Up RAM (BURAM)

Write Protected Registers

Chapter 4 External Memory Controller (MEMC)

V850E2/Fx4 MEMC Features

Overview

Registers

Bus Cycle Type Setting Function

Bus Control Function

Wait Functions

Memory Connection Examples

Data Flow

Chapter 5 Interrupt Functions

Exceptions and Interrupts

V850E2/Fx4 Exceptions

V850E2/Fx4 Interrupt Requests

External Interrupts

Interrupt Controller Control Registers

Interrupt Acknowledgment and Restoring

Interrupt Operation

Exception Handler Address Switching Function

Chapter 6 DMA Controller (DMAC)

V850E2/Fx4 DMA Features

Definition of Terms

General

DMAC Function

DMA Control Registers

DMAC Function Details

DTFR Function

DTFR Control Registers

Chapter 7 Flash Memory

Code Flash Memory Overview

Code Flash Memory Functional Outline

Data Flash Memory

Flash Programming with Flash Programmer

Code Flash Self-Programming

Flash Mask Options

Chapter 8 Data CRC Function a (DCRA)

V850E2/Fx4 DCRA Features

Functional Overview

Functional Description

Registers

Chapter 9 Clock Controller