Renesas mPD70F3377A Manuals

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Renesas mPD70F3377A User Manual (994 pages)

32-bit Single-Chip

Brand: Renesas | Category: Microcontrollers | Size: 18 MB

Table of Contents
6
Chapter 1 Introduction

18
General

18
Features Summary

19
Description

22
- Internal Units
  26
- Structure of the Manual
  27
Ordering Information

28
Chapter 2 Pin Functions

32
Overview

32
- Description
  33
- Terms
  37
- Noise Elimination
  37
Port Group Configuration Registers

38
- Overview
  38
- Pin Function Configuration
  39
- Pin Data Input/Output
  45
- Configuration of Pull-Up Resistors
  47
- Open Drain Configuration
  48
Port Buffers Diagrams

49
Port Type Diagrams

52
- Port Type C
  52
- Port Type C-U
  53
- Port Type D0
  53
- Port Type D0-U
  54
- Port Type D1
  54
- Port Type D1-U
  55
- Port Type D1-UI
  56
- Port Type D3-UI
  57
- Port Type D1A
  58
- Port Type D1O1-UI
  59
- Port Type D2
  60
- Port Type E01-U
  61
- Port Type E10-U
  62
- Port Type E10-UI
  63
- Port Type E11-U
  64
- Port Type E11-UI
  65
- Port Type E21-U
  66
- Port Type Ex0-U
  67
- Port Type Ex1-U
  68
- Port Type Ex1-UI
  69
- Port Type Ex2-U
  70
- Port Type F010X-U
  71
- Port Type F010X-UI
  72
- Port Type F100X-U
  73
- Port Type F1010-U
  74
- Port Type F101X-U
  75
- Port Type F1100O0-U
  76
- Port Type F1100O1-U
  77
- Port Type F1100-U
  78
- Port Type F1110-UI
  79
- Port Type F113X-UI
  80
- Port Type F1X10-UI
  81
- Port Type F3X1X-UI
  82
- Port Type F1Xx0O1-U
  83
- Port Type Fx010-U
  84
- Port Type Fx01X-U
  85
- Port Type Fx103-UI
  86
- Port Type Fx10X-U
  87
- Port Type Fx10X-UI
  88
- Port Type Fx110-U
  89
- Port Type Fx120-UFI
  90
- Port Type Fx123-UFI
  91
- Port Type Fx12X-UFI
  92
- Port Type Fx13X-U
  93
- Port Type Fx210-U
  94
- Port Type Fx2X0-U
  95
- Port Type Fxx10-U
  96
- Port Type Fxx1X-U
  97
- Port Type Fxx2X-U
  98
Port Group Configuration

99
- Port Group Configuration Lists
  99
- Alphabetic Pin Function List
  106
- Port Group 0
  114
- Port Group 1 (V850ES/FG3, V850ES/FJ3, V850ES/FK3)
  116
- Port Group 2 (V850ES/FK3)
  117
- Port Group 3
  119
- Port Group 4
  121
- Port Group 5
  122
- Port Group 6 (V850ES/FJ3, V850ES/FK3)
  124
- Port Group 7
  128
- Port Group 8 (V850ES/FJ3, V850ES/FK3)
  130
- Port Group 9
  131
- Port Group 12 (V850ES/FJ3, V850ES/FK3)
  136
- Port Group 15 (V850ES/FK3)
  137
- Port Group CD (V850ES/FJ3, V850ES/FK3)
  138
- Port Group CM
  139
- Port Group CS (V850ES/FF3, V850ES/FG3, V850ES/FJ3, V850ES/FK3)
  140
- Port Group CT (V850ES/FF3, V850ES/FG3, V850ES/FJ3, V850ES/FK3)
  141
- Port Group DL
  142
Noise Elimination

144
- Analog Filtered Inputs
  144
- Digitally Filtered Inputs
  145
Pin Functions in Reset and Power Save Modes

148
Recommended Connection of Unused Pins

149
Package Pins Assignment

150
Chapter 3 CPU System Functions

155
Overview

155
- Description
  156
CPU Register Set

157
- General Purpose Registers (R0 to R31)
  158
- System Register Set
  159
Operation Modes

166
- Normal Operation Mode
  166
- Flash Programming Mode
  166
- On-Chip Debug Mode
  167
Address Space

167
- CPU Address Space and Physical Address Space
  167
- Program and Data Space
  169
Memory

171
- Memory Areas
  171
- Recommended Use of Data Address Space
  175
Write Protected Registers

176
- Write Protection Control Registers
  178
Chapter 4 Clock Generator

179
Overview

179
- Description
  180
- Clock Monitor
  184
- Power Save Modes Overview
  185
- Start Conditions
  186
Clock Generator Registers

187
- General Clock Generator Registers
  189
- PLL Control Registers
  199
- SSCG Control Registers
  202
- Stand-By Control Registers
  205
- Prescaler3 Control Registers
  207
- Clock Monitor Control Registers
  208
- Selector Control Registers
  209
Option Bytes

215
- Option Byte 0000 007A H
  216
- Option Byte 0000 007B H
  217
Clock Generator Operation

218
- Overview of Clock Operation Control Settings
  218
- Operation State Transitions
  219
- Power Save Modes Description
  222
- Available Clocks in Power Save Modes
  239
- Power Save Mode Activation
  241
- Controlling the PLL
  243
- Watch Dog Timer Clock
  243
- CLKOUT Function
  243
- Operation of Prescaler3
  244
- Operation of the Clock Monitor
  245
Chapter 5 Interrupt Controller (INTC)

248
Features

248
Non-Maskable Interrupts

257
- Operation
  260
- Restore
  261
- Non-Maskable Interrupt Status Flag (NP)
  262
- NMI Control
  262
Maskable Interrupts

263
- Operation
  263
- Restore
  265
- Priorities of Maskable Interrupts
  266
- Xxicn - Maskable Interrupt Control Registers
  270
- Imrm - Interrupt Mask Registers
  275
- ISPR - In-Service Priority Register
  279
- Maskable Interrupt Status Flag (ID)
  280
- External Maskable Interrupts
  280
External Interrupts Edge Detection Configuration

280
Software Exception

286
- Operation
  286
- Restore
  287
- Exception Status Flag (EP)
  288
Exception Trap

289
- Illegal Opcode Definition
  289
- Debug Trap
  290
Multiple Interrupt Processing Control

292
Interrupt Response Time

294
Periods in Which Interrupts Are Not Acknowledged

295
Chapter 6 Key Interrupt Function

296
Function

296
Control Register

297
Cautions

297
Chapter 7 Flash Memory

298
Code Flash Memory Overview

300
- Code Flash Memory Features
  300
- Code Flash Memory Mapping
  301
- Code Flash Memory Functional Outline
  303
- Code Flash Memory Erasure and Rewrite
  306
Data Flash Memory

307
- Data Flash Memory Features
  307
- Data Flash Memory Map
  308
- Data Flash Control Register
  309
- Data Flash Reading
  309
- Data Flash Writing
  310
Flash Programming with Flash Programmer

311
- Programming Environment
  311
- Communication Mode
  312
- Pin Connection with Flash Programmer PG-FP5
  314
- Flash Memory Programming Control
  316
Code Flash Self-Programming

321
Variable Reset Vector

329
Flash Mask Options

330
Device Information

332
- PRDSELL Register - Product Selection Code Register
  332
- PRDSELH Register - Product Selection Code Register
  333
Chapter 8 Data Protection and Security

334
Overview

334
N-Wire Debug Interface Protection

334
Flash Programmer and Self-Programming Protection

336
Chapter 9 Bus and Memory Control (BCU, MEMC)

339
Overview

339
Description

340
- Memory Blocks and Chip Select Signals
  342
- Peripheral I/O Area
  343
- NPB Access Timing
  345
- Bus Properties
  346
- Boundary Operation Conditions
  347
- Initialization for Access to External Devices
  348
- Bus Hold Function
  349
- Pin Status
  351
Registers

352
- BCU Registers
  352
- Memory Controller Registers
  356
Configuration of Memory Access

359
- Wait Function
  359
- Idle State Insertion
  360
External Devices Interface Timing

361
- Writing to External Devices
  361
- Reading from External Devices
  364
Data Access Order

367
- Access to 8-Bit Data Busses
  367
- Access to 16-Bit Data Busses
  370
Chapter 10 DMA Function (DMA Controller)

373
Features

373
Configuration

374
Registers

375
Transfer Targets

386
Transfer Modes

386
Transfer Types

387
DMA Channel Priorities

388
Time Related to DMA Transfer

388
DMA Transfer Start Factors

389
DMA Abort Factors

390
End of DMA Transfer

390
Operation Timing

391
Cautions

395
Chapter 11 16-Bit Timer/Event Counter AA

400
Features

400
Function Outline

401
Configuration

401
Input Selection Registers

408
Control Registers

412
Operation

425
Chapter 12 16-Bit Timer/Event Counter AB

468
Features

468
Function Outline

469
Configuration

469
Control Registers

476
Operation

486
Chapter 13 16-Bit Interval Timer M

519
Features

519
Configuration

520
Timer M Registers

521
Operation

523
- Interval Timer Mode
  523
- Cautions
  524
Chapter 14 Timer AA/AB Synchronous Operation

525
Chapter 15 Watch Timer Functions

527
Functions

527
Configuration

528
Control Registers

529
Operation

531
- Operation as Watch Timer
  531
- Operation as Interval Timer
  531
- Cautions
  532
Chapter 16 Watchdog Timer 2

533
Functions

533
Configuration

534
Control Registers

535
Watchdog Timer Operation

538
Watchdog Timer Operation in Power Save Mode

538
Chapter 17 Asynchronous Serial Interface (UARTD)

539
Features

540
Configuration

541
UARTD Registers

544
Interrupt Request Signals

554
Operation

555
- Data Format
  555
- SBF Transmission/Reception Format
  557
- SBF Transmission
  559
- SBF Reception
  559
- Data Consistency Check
  561
- UART Transmission
  563
- Continuous Transmission Procedure
  564
- UART Reception
  566
- Reception Errors
  567
- Parity Types and Operations
  568
- Receive Data Noise Filter
  569
Baud Rate Generator

570
Cautions

577
Chapter 18 Clocked Serial Interface (CSIB)

578
Features

578
Configuration

579
CSIB Control Registers

581
Operation

588
Output Pins

600
Operation Flow

601
Chapter 19 I 2 C Bus (IIC)

608
Features

608
I 2 C Pin Configuration

608
Configuration

609
IIC Registers

613
I 2 C Bus Mode Functions

630
- Pin Functions
  630
I 2 C Bus Definitions and Control Methods

631
- Start Condition
  631
- Addresses
  632
- Transfer Direction Specification
  633
- Acknowledge Signal (ACK)
  633
- Stop Condition
  634
- Wait Signal (WAIT)
  635
C Interrupt Request Signals (Intiicn)

637
Interrupt Request Signal (Intiicn)

655
Address Match Detection Method

656
Error Detection

656
Extension Code

657
Arbitration

658
Wakeup Function

659
Cautions

660
Communication Operations

661
- Master Operation 1
  661
- Master Operation 2
  662
- Slave Operation
  663
Timing of Data Communication

667
Chapter 20 CAN Controller (CAN)

674
Features

675
- Overview of Functions
  676
- Configuration
  677
CAN Protocol

678
- Frame Format
  678
- Frame Types
  679
- Data Frame and Remote Frame
  679
- Error Frame
  686
- Overload Frame
  687
Functions

688
- Determining Bus Priority
  688
- Bit Stuffing
  688
- Multi Masters
  689
- Multi Cast
  689
- CAN Sleep Mode/Can Stop Mode Function
  689
- Error Control Function
  689
- Baud Rate Control Function
  696
Connection with Target System

699
Internal Registers of CAN Controller

700
- CAN Module Register and Message Buffer Addresses
  700
- CAN Controller Configuration
  701
- CAN Registers Overview
  702
- Register Bit Configuration
  712
Bit Set/Clear Function

715
Control Registers

717
CAN Controller Initialization

753
Message Reception

757
- Receive Data Read
  758
- Receive History List Function
  759
- Mask Function
  761
- Multi Buffer Receive Block Function
  762
- Remote Frame Reception
  763
Message Transmission

764
- Transmit History List Function
  766
- Automatic Block Transmission (ABT)
  768
- Transmission Abort Process
  770
- Remote Frame Transmission
  771
Power Saving Modes

772
- CAN Sleep Mode
  772
- CAN Stop Mode
  775
- Example of Using Power Saving Modes
  776
Interrupt Function

777
Diagnosis Functions and Special Operational Modes

778
- Receive-Only Mode
  778
- Single-Shot Mode
  779
- Self-Test Mode
  780
- Receive/Transmit Operation in each Operation Mode
  781
Time Stamp Function

782
Baud Rate Settings

783
- Baud Rate Setting Conditions
  783
- Representative Examples of Baud Rate Settings
  787
Operation of CAN Controller

791
Chapter 21 A/D Converter (ADC)

817
Functions

817
Configuration

819
ADC Registers

821
Operation

835
- Basic Operation
  835
- Trigger Mode
  836
- Operation Modes
  838
- Power-Fail Compare Mode
  843
Cautions

849
How to Read A/D Converter Characteristics Table

851
Chapter 22 Motor Control Function

856
Functional Overview

856
Configuration

857
Control Registers

861
Operation

873
Chapter 23 Power Supply Scheme

916
Overview

916
Description

917
On-Chip Voltage Regulators

919
Chapter 24 Low-Voltage Detector

920
Functions

920
Configuration

921
Registers

922
Operation

926
Chapter 25 On-Chip Debug Unit

930
Functional Outline

930
- Debug Functions
  930
Controlling the N-Wire Interface

933
N-Wire Enabling Methods

935
Connection to N-Wire Emulator

937
- KEL Connector
  937
Restrictions and Cautions on On-Chip Debug Function

941
Chapter 26 Reset

942
Overview

942
- General Reset Performance
  942
- Reset at Power-On
  945
- External RESET
  947
- Reset by Watchdog Timer 2
  948
- Reset by Clock Monitor
  948
- Reset by Low-Voltage Detector
  948
Reset Registers

949
Appendix A Special Function Registers

950
CAN Registers

950
Other Special Function Registers

954
Appendix B Registers Access Times

971
Timer AA

972
Timer AB

974
Motor Control Function

976
Timer M

977
Watchdog Timer 2

978
A/D Converter

978
I2C Bus

979
Asynchronous Serial Interface (UARTD)

979
Clocked Serial Interface (CSIB)

979
CAN Controller

980
All Other Registers

980
Revision History

981
Index

983

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Renesas mPD70F3377A User Manual (994 pages)

Table of Contents

Chapter 1 Introduction

General

Features Summary

Description

Ordering Information

Chapter 2 Pin Functions

Overview

Port Group Configuration Registers

Port Buffers Diagrams

Port Type Diagrams

Port Group Configuration

Noise Elimination

Pin Functions in Reset and Power Save Modes

Recommended Connection of Unused Pins

Package Pins Assignment

Chapter 3 CPU System Functions

Overview

CPU Register Set

Operation Modes

Address Space

Memory

Write Protected Registers

Chapter 4 Clock Generator

Overview

Clock Generator Registers

Option Bytes

Clock Generator Operation

Chapter 5 Interrupt Controller (INTC)

Features

Non-Maskable Interrupts

Maskable Interrupts

External Interrupts Edge Detection Configuration

Software Exception

Exception Trap

Multiple Interrupt Processing Control

Interrupt Response Time

Periods in Which Interrupts Are Not Acknowledged

Chapter 6 Key Interrupt Function

Function

Control Register

Cautions

Chapter 7 Flash Memory

Code Flash Memory Overview

Data Flash Memory

Flash Programming with Flash Programmer

Code Flash Self-Programming

Variable Reset Vector

Flash Mask Options

Device Information

Chapter 8 Data Protection and Security

Overview

N-Wire Debug Interface Protection

Flash Programmer and Self-Programming Protection

Chapter 9 Bus and Memory Control (BCU, MEMC)

Overview

Description

Registers

Configuration of Memory Access

External Devices Interface Timing

Data Access Order

Chapter 10 DMA Function (DMA Controller)

Features

Configuration

Registers

Transfer Targets

Transfer Modes

Transfer Types

DMA Channel Priorities

Time Related to DMA Transfer

DMA Transfer Start Factors

DMA Abort Factors

End of DMA Transfer

Operation Timing

Cautions

Chapter 11 16-Bit Timer/Event Counter AA

Features

Function Outline