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MIPS MIPS32 74Kf manual available for free PDF download: Programming Manual
MIPS MIPS32 74Kf Programming Manual (156 pages)
Brand:
MIPS
| Category:
Computer Hardware
| Size: 1 MB
Table of Contents
Table of Contents
3
Chapter 1: Introduction
11
Chapters of this Manual
12
Conventions
12
74K™ Core Features
13
A Brief Guide to the 74K™ Core Implementation
14
1: Notes on Pipeline Overview Diagram (Figure 1.1)
14
Figure 1.1 Overview of the 74K™ Pipeline
14
2: Branches and Branch Delays
17
3: Loads and Load-To-Use Delays
18
4: Queues, Resource Limits and Consequences
19
Chapter 2: Initialization and Identity
21
Probing Your CPU - Config CP0 Registers
21
Table 2.1: Roles of Config Registers
21
1: the Config Register
22
Figure 2.1: Fields in the Config Register
22
2: the Config1-2 Registers
23
Figure 2.2: Fields in the Config1 Register
23
Figure 2.3: Fields in the Config2 Register
23
3: the Config3 Register
24
Figure 2.4: Config3 Register Format
24
4: the Config6 Register
25
Figure 2.5: Config6 Register Format
25
5: CPU-Specific Configuration - Config7
26
Prid Register - Identifying Your CPU Type
26
Figure 2.6 Fields in the Prid Register
26
Table 2.2: 74K™® Core Releases and Prid[Revision] Fields
26
Chapter 3: Memory Map, Caching, Reads, Writes and Translation
29
The Memory Map
29
Table 3.1 Basic MIPS32® Architecture Memory Map
29
Fixed Mapping Option
30
Reads, Writes and Synchronization
30
1: Read/Write Ordering and Cache/Memory Data Queues in the 74K™ Core
30
Table 3.2 Fixed Memory Mapping
30
2: the "Sync" Instruction in 74K™ Family Cores
31
3: Write Gathering and "Write Buffer Flushing" in 74K™ Family Cores
32
Caches
32
1: the L2 Cache Option
32
2: Cacheability Options
33
3: Uncached Accelerated Writes
34
4: the Cache Instruction and Software Cache Management
34
Figure 3.1 Fields in the Encoding of a Cache Instruction
34
Table 3.3 Cache Code Values
34
5: Cache Instructions and CP0 Cache Tag/Data Registers
35
Table 3.4 Operations on a Cache Line Available with the Cache Instruction
36
6: L1 Cache Instruction Timing
37
7: L2 Cache Instruction Timing
37
8: Cache Management When Writing Instructions - the "Synci" Instruction
37
Table 3.1 Caches and Their CP0 Cache Tag/Data Registers
37
9: Cache Aliases
38
10: Cache Locking
39
11: Cache Initialization and Tag/Data Registers
39
Figure 3.2 Fields in the Taglo Registers
39
12: L23Taglo Regiser
40
13: L23Datalo Register
40
14: L23Datahi Register
40
Figure 3.3 L23Taglo Register Format
40
Figure 3.4 L23Datalo Register Format
40
Table 3.5 L23Datalo Register Field Description
40
15: Taglo Registers in Special Modes
41
16: Parity Error Exception Handling and the Cacheerr Register
41
Figure 3.5 L23Datahi Register Format
41
Figure 3.6 Fields in the Cacheerr Register
41
Table 3.6 L23Datahi Register Field Description
41
17: Errctl Register
42
Bus Error Exception
43
Figure 3.7 Fields in the Errctl Register
43
Scratchpad Memory/Spram
44
Figure 3.8: SPRAM (Scratchpad RAM) Configuration Information in Taglo
45
Common Device Memory Map
46
Figure 3-9 Fields in the Cdmmbase Register
46
The TLB and Translation
47
1: a TLB Entry
47
Figure 3.10 Fields in the Access Control and Status (ACSR) Register
47
2: Live Translation and Micro-Tlbs
48
3: Reading and Writing TLB Entries: Index, Random and Wired
48
Figure 3.11 Fields in a 74K™ Core TLB Entry
48
4: Reading and Writing TLB Entries - Entrylo0-1, Entryhi and Pagemask Registers
49
Figure 3.12 Fields in the Entryhi and Pagemask Registers
49
5: TLB Initialization and Duplicate Entries
50
Figure 3.13 Fields in the Entrylo0-1 Registers
50
6: TLB Exception Handlers - Badvaddr, Context, and Contextconfig Registers
51
Figure 3.14: Fields in the Context Register When Config3Ctxtc=0 and Config3Sm=0
51
Figure 3.15: Fields in the Context Register When Config3Ctxtc=1 or Config3Sm=1
52
Figure 3.16: Fields in the Contextconfig Register
53
Table 3.7: Recommended Contextconfig Values
53
Chapter 4: Programming the 74K™ Core in User Mode
55
User-Mode Accessible "Hardware Registers
55
Prefetching Data
56
Using "Synci" When Writing Instructions
56
The Multiplier
57
Table 4.1 Hints for "Pref" Instructions
57
Tuning Software for the 74K™ Family Pipeline
58
1: Cache Delays and Mitigating Their Effect
58
2: Branch Delay Slot
59
Tuning Floating-Point
59
Branch Misprediction Delays
60
Load Delayed by (Unrelated) Recent Store
60
Minimum Load-Miss Penalty
60
Data Dependency Delays
61
Table 4.2 Register → Eager Consumer Delays
62
Table 4.3: Producer → Register Delays
63
1: more Complicated Dependencies
64
Advice on Tuning Instruction Sequences (Particularly DSP)
65
Multiply/Divide Unit and Timings
65
Chapter 5: Kernel-Mode (OS) Programming and Release 2 of the MIPS32® Architecture
67
Hazard Barrier Instructions
67
MIPS32® Architecture Release 2 - Enhanced Interrupt System(S)
68
1: Traditional MIPS® Interrupt Signalling and Priority
69
Figure 5.1 Fields in the Intctl Register
69
2: VI Mode - Multiple Entry Points, Interrupt Signalling and Priority
70
3: External Interrupt Controller (EIC) Mode
70
Exception Entry Points
71
1: Summary of Exception Entry Points
72
Figure 5.2 Fields in the Ebase Register
72
Shadow Registers
73
Figure 5.3 Fields in the Srsctl Register
73
Table 5.1: All Exception Entry Points
73
Figure 5.4 Fields in the Srsmap Register
74
Saving Power
75
The Hwrena Register - Control User Rdhwr Access
75
Figure 5.5 Fields in the Hwrena Register
75
Chapter 6: Floating Point Unit
77
Data Representation
77
Basic Instruction Set
78
Figure 6.1: How Floating Point Numbers Are Stored in a Register
78
Floating Point Loads and Stores
79
Setting up the FPU and the FPU Control Registers
79
1: IEEE Options
79
2: FPU "Unimplemented" Exceptions (and How to Avoid Them)
79
3: FPU Control Register Maps
80
Figure 6.2 Fields in the FIR Register
80
Table 6.1 FPU (Co-Processor 1) Control Registers
80
Figure 6.3 Floating Point Control/Status Register and Alternate Views
81
FPU Pipeline and Instruction Timing
82
Figure 6.4: Overview of the FPU Pipeline
83
1: FPU Register Dependency Delays
84
2: Delays Caused by Long-Latency Instructions Looping in the M1 Stage
84
3: Delays on FP Load and Store Instructions
84
4: Delays When Main Pipeline Waits for FPU to Decide Not to Take an Exception
84
Table 6.2: Long-Latency FP Instructions
84
5: Delays When Main Pipeline Waits for FPU to Accept an Instruction
85
6: Delays on Mfc1/Mtc1 Instructions
85
7: Delays Caused by Dependency on FPU Status Register Fields
85
8: Slower Operation in MIPS I™ Compatibility Mode
85
Chapter 7: The MIPS32® DSP ASE
87
Features Provided by the MIPS® DSP ASE
87
The DSP ASE Control Register
88
Figure 7.1 Fields in the Dspcontrol Register
88
1: DSP Accumulators
89
Software Detection of the DSP ASE
89
DSP Instructions
90
1: Hints in Instruction Names
90
2: Arithmetic - 64-Bit
91
3: Arithmetic - Saturating And/Or SIMD Types
91
4: Bit-Shifts - Saturating And/Or SIMD Types
91
5: Comparison and "Conditional-Move" Operations on SIMD Types
91
6: Conversions to and from SIMD Types
92
7: Multiplication - SIMD Types with Result in GP Register
92
8: Multiply Q15S from Paired-Half and Accumulate
93
9: Load with Register + Register Address
93
10: Dspcontrol Register Access
93
Table 7.1 Mask Bits for Instructions Accessing the Dspcontrol Register
93
11: Accumulator Access Instructions
94
12: Dot Products and Building Blocks for Complex Multiplication
94
13: Other DSP ASE Instructions
95
Macros and Typedefs for DSP Instructions
95
Almost Alphabetically-Ordered Table of DSP ASE Instructions
96
Table 7.2 DSP Instructions in Alphabetical Order
96
DSP ASE Instruction Timing
100
Chapter 8: 74K™ Core Features for Debug and Profiling
102
EJTAG On-Chip Debug Unit
102
1: Debug Communications through JTAG
103
2: Debug Mode
103
Table 8.1 JTAG Instructions for the EJTAG Unit
103
3: Exceptions in Debug Mode
104
4: Single-Stepping
104
5: the "Dseg" Memory Decode Region
104
Table 8.2: EJTAG Debug Memory Region Map ("Dseg")
105
6: EJTAG CP0 Registers, Particularly Debug
106
Figure 8.1 Fields in the EJTAG CP0 Debug Register
107
7: the DCR (Debug Control) Memory-Mapped Register
108
Figure 8.2 Exception Cause Bits in the Debug Register
108
Figure 8.3: Debug Register - Exception-Pending Flags
108
Figure 8.4 Fields in the Memory-Mapped DCR (Debug Control) Register
109
8: the Debugvectoraddr Memory-Mapped Register
110
9: JTAG-Accessible Registers
110
Figure 8.5 Fields in the Memory-Mapped DCR (Debug Control) Register
110
Figure 8.6 Ifields in the JTAG-Accessible Implementation Register
110
Figure 8.7 Fields in the JTAG-Accessible EJTAG_CONTROL Register
111
Table 8.3 Fields in the JTAG-Accessible EJTAG_CONTROL Register
111
10: Fast Debug Channel
112
Figure 8.8 Fast Debug Channel
113
Figure 8.9 Fields in the FDC Access Control and Status (FDACSR) Register
113
Table 8.4 FDC Register Mapping
113
Figure 8.10: Fields in the FDC Config (FDCFG) Register
114
Figure 8.11 Fields in the FDC Status (FDSTAT) Register
114
11: EJTAG Breakpoint Registers
115
Figure 8.12 Fields in the FDC Receive (FDRX) Register
115
Figure 8.13 Fields in the FDC Transmit (Fdtxn) Registers
115
Figure 8.14 Fields in the IBS/DBS (EJTAG Breakpoint Status) Registers
116
12: Understanding Breakpoint Conditions
117
Figure 8.15 Fields in the Hardware Breakpoint Control Registers (Ibcn, Dbcn)
117
13: Imprecise Debug Breaks
118
14: PC Sampling with EJTAG
118
15: JTAG-Accessible and Memory-Mapped Pdtrace TCB Registers
119
Table 8.5 Mapping TCB Registers in Drseg
119
Pdtrace™ Instruction Trace Facility
121
1: 74K Core-Specific Fields in Pdtrace™ JTAG-Accessible Registers
121
Figure 8.16 Fields in the TCBCONTROLE Register
122
Table 8.6 Fields in the TCBCONTROLA Register
122
Table 8.7 Fields in the TCBCONTROLB Register
122
2: CP0 Registers for the Pdtrace™ Logic
123
Figure 8.17: Fields in the TCBCONFIG Register
123
Figure 8.18: Fields in the Tracecontrol Register
123
Figure 8.19 Fields in the Tracecontrol2 Register
123
Figure 8.20 Fields in the Tracecontrol3 Register
123
3: JTAG Triggers and Local Control through Traceibpc/Tracedbpc
125
Figure 8.21 Fields in the Traceibpc/Tracedbpc Registers
125
4: Usertracedata1 Reg and Usertracedata2 Reg
126
5: Summary of When Trace Happens
126
CP0 Watchpoints
128
1: the Watchlo0-3 Registers
128
2: the Watchhi0-3 Registers
128
Figure 8.22 Fields in the Watchlo0-3 Register
128
Figure 8.23 Fields in the Watchhi0-3 Register
128
Performance Counters
129
Figure 8.24 Fields in the Perfctl0-3 Register
129
1: Reading the Event Table
130
Table 8.8: Performance Counter Event Codes in the Perfctl0-3[Event] Field
131
Appendix A: References
135
Appendix B: CP0 Register Summary and Reference
137
Table B.1 Register Index by Name
137
Table B.2 CP0 Registers by Number
138
B.1: Miscellaneous CP0 Register Descriptions
140
Table B.3 CP0 Registers Grouped by Function
140
B.1.1: Status Register
141
Figure B.1 Fields in the Status Register
141
Table B.4 Encoding Privilege Level in Status[Um,Sm]
142
B.1.2: the Userlocal Register
143
B.1.3: Exception Control: Cause and EPC Registers
143
B.1.3.1: the Cause Register
143
Figure B.2 Fields in the Cause Register
143
Table B.5 Values Found in Cause[Exccode]
144
B.1.4: the EPC Register
145
B.1.5: Count and Compare
145
B.2: Registers for CPU Configuration
145
B.2.1: the Config7 Register
145
Table B.6: Fields in the Config7 Register
146
B.3: Registers for Cache Diagnostics
148
B.3.1: Different Views of Itaglo/Dtaglo
148
Figure B.3 Fields in the Taglo-WST Register
148
B.3.2: Dual (Virtual and Physical) Tags in the 74K Core D-Cache - Dtaghi Register
149
B.3.3: Pre-Decode Information in the I-Cache - the Itaghi Register
149
Figure B.4 Fields in the Taglo-DAT Register
149
Figure B.5 Fields in the Dtaghi Register
149
Figure B.6 Fields in the Itaghi Register
149
B.3.4: the Ddatalo, Idatahi and Idatalo Registers
150
B.3.5: the Errorepc Register
150
Appendix C: MIPS® Architecture Quick-Reference Sheet(S)
151
C.1: General Purpose Register Numbers and Names
151
C.2: User-Level Changes with Release 2 of the MIPS32® Architecture
151
C.2.1: Release 2 of the MIPS32® Architecture - New Instructions for User-Mode
151
Table C.1 Conventional Names of Registers with Usage Mnemonics
151
C.2.2: Release 2 of the MIPS32® Architecture - Hardware Registers from User Mode
152
Table C.2 Release 2 of the MIPS32® Architecture - New Instructions
152
C.3: FPU Changes in Release 2 of the MIPS32® Architecture
153
Appendix D: Revision History
155
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