Micrel KSZ8441HL Manuals

Manuals and User Guides for Micrel KSZ8441HL. We have 1 Micrel KSZ8441HL manual available for free PDF download: Manual

Micrel KSZ8441HL Manual (194 pages)

IEEE 1588v2, Precision Time Protocol-Enabled, 10/100Mbs, Ethernet End-Point Connection with 8- or 16-Bit Hoist Bus Interface

Brand: Micrel | Category: Recording Equipment | Size: 2 MB

Table of Contents
5
Acronyms
15
Pin Configuration
17
Pin Description
18
Strapping Options
24
Functional Description
25
Phy (Physical) Block
26
- 100BASE-TX Transmit
  26
- 100BASE-TX Receive
  26
- Scrambler/De-Scrambler (100BASE-TX Only)
  26
- PLL Clock Synthesizer (Recovery)
  26
- 100BASE-FX Operation
  26
- 100BASE-FX Signal Detection
  27
100BASE-FX Far-End Fault
27
- 10BASE-T Transmit
  27
- 10BASE-T Receive
  27
- MDI/MDI-X Auto Crossover
  27
Figure 3. Auto-Negotiation and Parallel Operation
29
Auto-Negotiation
29
Linkmd ® Cable Diagnostics
30
- Access
  30
- Usage
  30
- On-Chip Termination Resistors
  30
Loopback Support
31
MAC (Media Access Controller) Block
32
- MAC Operation
  32
- Inter-Packet Gap (IPG)
  32
- Back-Off Algorithm
  32
- Late Collision
  32
- Legal Packet Size
  32
- Flow Control
  32
- Half-Duplex Backpressure
  32
Table 2. MAC Address Filtering Scheme
33
Address Filtering Function
33
Queue Management Unit (QMU)
34
IEEE 1588 Precision Time Protocol (PTP) Block
40
IEEE 1588 PTP Clock Types
41
IEEE 1588 PTP One-Step or Two-Step Clock Operation
41
- One-Step Clock Operation
  41
- Two-Step Clock Operation
  41
IEEE 1588 PTP Best Master Clock Selection
41
IEEE 1588 PTP System Time Clock
42
IEEE 1588 PTP Message Processing
45
- IEEE 1588 PTP Ingress Packet Processing
  45
- IEEE 1588 PTP Egress Packet Processing
  45
IEEE 1588 PTP Event Triggering and Timestamping
46
General Purpose and IEEE 1588 Input/Output (GPIO)
48
Table 12. KSZ8441 Device Clocks
59
Device Clocks
59
GPIO and IEEE 1588 Related Clocking
59
Power
60
Power Management
62
Figure 17. Interface and Register Mapping
70
Device Registers
70
Table 18. Mapping of Functional Areas Within the Address Space
71
Register Map of CPU Accessible I/O Registers
72
- I/O Registers
  72
Internal I/O Register Space Mapping for General Control and Configuration (0X000 - 0X0Ff)
73
Internal I/O Register Space Mapping for Host Interface Unit (0X100 - 0X16F)
76
Internal I/O Register Space Mapping for the QMU (0X170 - 0X1Ff)
78
Internal I/O Register Space Mapping for PTP Trigger Output (12 Units, 0X200 - 0X3Ff)
80
Internal I/O Register Space Mapping for PTP Event Timestamp Input (12 Units, 0X400 - 0X5Ff)
88
Internal I/O Register Space Mapping for PTP 1588 Clock and Global Control (0X600 - 0X7Ff)
98
Chip ID and Enable Register (0X000 - 0X001): CIDER
100
Register Bit Definitions
100
- Internal I/O Registers Space Mapping for General Control and Configuration (0X000 - 0X0Ff)
  100
General Global Control Register 1 (0X002 - 0X003): GGCR1
101
0X004 - 0X00D: Reserved
101
General Global Control Register 7 (0X00E - 0X00F): GGCR7
102
MAC Address Register 1 (0X010 - 0X011): MACAR1
102
MAC Address Register 2 (0X012 - 0X013): MACAR2
102
MAC Address Register 3 (0X014 - 0X015): MACAR3
102
0X016 - 0X025: Reserved
103
Indirect Access Data Register 1 (0X026 - 0X027): IADR1
103
0X028- 0X02B: Reserved
103
Indirect Access Data Register 4 (0X02C - 0X02D): IADR4
103
Indirect Access Data Register 5 (0X02E - 0X02F): IADR5
103
Indirect Access Control Register (0X030 - 0X031): IACR
103
Power Management Control and Wake-Up Event Status (0X032 - 0X033): PMCTRL
104
Power Management Event Enable Register (0X034 - 0X035): PMEE
104
Go Sleep Time Register (0X036 - 0X037): GST
105
Clock Tree Power down Control Register (0X038 - 0X039): CTPDC
105
0X03A - 0X04B: Reserved
105
PHY 1 and MII Basic Control Register (0X04C - 0X04D): P1MBCR
106
PHY 1 and MII Basic Status Register (0X04E - 0X04F): P1MBSR
108
PHY 1 PHYID Low Register (0X050 - 0X051): PHY1ILR
109
PHY 1 PHYID High Register (0X052 - 0X053): PHY1IHR
109
PHY 1 Auto-Negotiation Advertisement Register (0X054 - 0X055): P1ANAR
109
PHY 1 Auto-Negotiation Link Partner Ability Register (0X056 - 0X057): P1ANLPR
110
0X058 - 0X065: Reserved
110
PHY 1 Special Control and Status Register (0X066 - 0X067): P1PHYCTRL
111
0X068 - 0X06B: Reserved
111
Port 1 Control Register 1 (0X06C - 0X06D): P1CR1
111
0X06E - 0X07B: Reserved
111
Port 1 PHY Special Control/Status, Linkmd
112
- (0X07C - 0X07D): P1SCSLMD
  112
Port 1 Control Register 4 (0X07E - 0X07F): P1CR4
113
0X082 - 0X0D5: Reserved
115
Input and Output Multiplex Selection Register (0X0D6 - 0X0D7): IOMXSEL
115
Configuration Status and Serial Bus Mode Register (0X0D8 - 0X0D9): CFGR
116
0X0Da - 0X0Db: Reserved
116
Port 1 Auto-Negotiation Next Page Transmit Register (0X0Dc - 0X0Dd): P1ANPT
116
Port 1 Auto-Negotiation Link Partner Received Next Page Register (0X0De - 0X0Df): P1ALPRNP
117
Port 1 EEE and Link Partner Advertisement Register (0X0E0 - 0X0E1): P1EEEA
118
Port 1 EEE Wake Error Count Register (0X0E2 - 0X0E3): P1EEEWEC
119
Port 1 EEE Control/Status and Auto-Negotiation Expansion Register (0X0E4 - 0X0E5): P1EEECS
119
Port 1 LPI Recovery Time Counter Register (0X0E6): P1LPIRTC
120
Buffer Load to LPI Control 1 Register (0X0E7): BL2LPIC1
120
0X0E8 - 0X0F1: Reserved
120
PCS EEE Control Register (0X0F2 - 0Xf3): PCSEEEC
121
Empty TXQ to LPI Wait Time Control Register (0X0F4 - 0X0F5): ETLWTC
121
Buffer Load to LPI Control 2 Register (0X0F6 - 0X0F7): BL2LPIC2
121
0X0F8 - 0X0Ff: Reserved
121
Internal I/O Register Space Mapping for Interrupts, BIU, and Global Reset (0X100 - 0X1Ff)
122
0X100 - 0X107: Reserved
122
Chip Configuration Register (0X108 - 0X109): CCR
122
0X10A - 0X10F: Reserved
122
Host MAC Address Registers: MARL, MARM and MARH
123
Host MAC Address Register Low (0X110 - 0X111): MARL
123
Host MAC Address Register Middle (0X112 - 0X113): MARM
123
Host MAC Address Register High (0X114 - 0X115): MARH
123
0X116 - 0X121: Reserved
123
EEPROM Control Register (0X122 - 0X123): EEPCR
124
Memory bist Info Register (0X124 - 0X125): MBIR
124
Global Reset Register (0X126 - 0X127): GRR
125
0X128 - 0X129: Reserved
125
Wake-Up Frame Control Register (0X12A - 0X12B): WFCR
125
0X12C - 0X12F: Reserved
126
Wake-Up Frame 0 CRC0 Register (0X130 - 0X131): WF0CRC0
126
Wake-Up Frame 0 CRC1 Register (0X132 - 0X133): WF0CRC1
126
Wake-Up Frame 0 Byte Mask 0 Register (0X134 - 0X135): WF0BM0
127
Wake-Up Frame 0 Byte Mask 1 Register (0X136 - 0X137): WF0BM1
127
Wake-Up Frame 0 Byte Mask 2 Register (0X138 - 0X139): WF0BM2
127
Wake-Up Frame 0 Byte Mask 3 Register (0X13A - 0X13B): WF0BM3
127
0X13C - 0X13F: Reserved
127
Wake-Up Frame 1 CRC0 Register (0X140 - 0X141): WF1CRC0
127
Wake-Up Frame 1 CRC1 Register (0X142 - 0X143): WF1CRC1
128
Wake-Up Frame 1 Byte Mask 0 Register (0X144 - 0X145): WF1BM0
128
Wake-Up Frame 1 Byte Mask 1 Register (0X146 - 0X147): WF1BM1
128
Wake-Up Frame 1 Byte Mask 2 Register (0X148 - 0X149): WF1BM2
128
Wake-Up Frame 1 Byte Mask 3 Register (0X14A - 0X14B): WF1BM3
128
0X14C - 0X14F: Reserved
128
Wake-Up Frame 2 CRC0 Register (0X150 - 0X151): WF2CRC0
129
Wake-Up Frame 2 CRC1 Register (0X152 - 0X153): WF2CRC1
129
Wake-Up Frame 2 Byte Mask 0 Register (0X154 - 0X155): WF2BM0
129
Wake-Up Frame 2 Byte Mask 1 Register (0X156 - 0X157): WF2BM1
129
Wake-Up Frame 2 Byte Mask 2 Register (0X158 - 0X159): WF2BM2
129
Wake-Up Frame 2 Byte Mask 3 Register (0X15A - 0X15B): WF2BM3
130
0X15C - 0X15F: Reserved
130
Wake-Up Frame 3 CRC0 Register (0X160 - 0X161): WF3CRC0
130
Wake-Up Frame 3 CRC1 Register (0X162 - 0X163): WF3CRC1
130
Wake-Up Frame 3 Byte Mask 0 Register (0X164 - 0X165): WF3BM0
130
Wake-Up Frame 3 Byte Mask 1 Register (0X166 - 0X167): WF3BM1
130
Wake-Up Frame 3 Byte Mask 2 Register (0X168 - 0X169): WF3BM2
131
Wake-Up Frame 3 Byte Mask 3 Register (0X16A - 0X16B): WF3BM3
131
0X16C - 0X16F: Reserved
131
Internal I/O Registers Space Mapping for the Queue Management Unit (QMU) (0X170 - 0X1Ff)
132
Transmit Control Register (0X170 - 0X171): TXCR
132
Transmit Status Register (0X172 - 0X173): TXSR
133
Receive Control Register 1 (0X174 - 0X175): RXCR1
133
Receive Control Register 2 (0X176 - 0X177): RXCR2
134
TXQ Memory Information Register (0X178 - 0X179): TXMIR
135
0X17A - 0X17B: Reserved
135
Receive Frame Header Status Register (0X17C - 0X17D): RXFHSR
135
Receive Frame Header Byte Count Register (0X17E - 0X17F): RXFHBCR
136
TXQ Command Register (0X180 - 0X181): TXQCR
136
RXQ Command Register (0X182 - 0X183): RXQCR
137
TX Frame Data Pointer Register (0X184 - 0X185): TXFDPR
138
RX Frame Data Pointer Register (0X186 - 0X187): RXFDPR
138
0X188 - 0X18B: Reserved
138
RX Duration Timer Threshold Register (0X18C - 0X18D): RXDTTR
139
RX Data Byte Count Threshold Register (0X18E - 0X18F): RXDBCTR
139
Internal I/O Registers Space Mapping for Interrupt Registers (0X190 - 0X193)
139
Interrupt Enable Register (0X190 - 0X191): IER
140
Interrupt Status Register (0X192 - 0X193): ISR
141
0X194 - 0X19B: Reserved
142
MAC Address Hash Table Register 0 (0X1A0 - 0X1A1): MAHTR0
143
MAC Address Hash Table Register 1 (0X1A2 - 0X1A3): MAHTR1
143
Internal I/O Registers Space Mapping for the Queue Management Unit (QMU) (0X19C - 0X1B9)
143
RX Frame Count & Threshold Register (0X19C - 0X19D): RXFCTR
143
TX Next Total Frames Size Register (0X19E - 0X19F): TXNTFSR
143
MAC Address Hash Table Register 2 (0X1A4 - 0X1A5): MAHTR2
144
MAC Address Hash Table Register 3 (0X1A6 - 0X1A7): MAHTR3
144
0X1A8 - 0X1Af: Reserved
144
Flow Control Low Water Mark Register (0X1B0 - 0X1B1): FCLWR
144
Flow Control High Water Mark Register (0X1B2 - 0X1B3): FCHWR
144
Flow Control Overrun Water Mark Register (0X1B4 - 0X1B5): FCOWR
144
0X1B6 - 0X1B7: Reserved
145
RX Frame Count Register (0X1B8 - 0X1B9): RXFC
145
0X1Ba - 0X1Ff: Reserved
145
Internal I/O Registers Space Mapping for Trigger Output Units (12 Units, 0X200 - 0X3Ff)
145
Trigger Error Register (0X200 - 0X201): TRIG_ERR
145
Trigger Active Register (0X202 - 0X203): TRIG_ACTIVE
145
Trigger Done Register (0X204 - 0X205): TRIG_DONE
146
Trigger Enable Register (0X206 - 0X207): TRIG_EN
146
Trigger Software Reset Register (0X208 - 0X209): TRIG_SW_RST
146
Trigger Output Unit 12 Output PPS Pulse Width Register (0X20A - 0X20B): TRIG12_PPS_WIDTH
146
0X20C - 0X21F: Reserved
147
Trigger Output Unit 1 Target Time in Nanoseconds Low-Word Register (0X220 - 0X221): TRIG1_TGT_NSL
147
Trigger Output Unit 1 Target Time in Nanoseconds High-Word Register (0X222 - 0X223): TRIG1_TGT_NSH
147
Trigger Output Unit 1 Target Time in Seconds Low-Word Register (0X224 - 0X225): TRIG1_TGT_SL
147
Trigger Output Unit 1 Target Time in Seconds High-Word Register (0X226 - 0X227): TRIG1_TGT_SH
147
Trigger Output Unit 1 Configuration and Control Register 1 (0X228 - 0X229): TRIG1_CFG_1
148
Trigger Output Unit 1 Configuration and Control Register 2 (0X22A - 0X22B): TRIG1_CFG_2
149
Trigger Output Unit 1 Configuration and Control Register 3 (0X22C - 0X22D): TRIG1_CFG_3
149
Trigger Output Unit 1 Configuration and Control Register 4 (0X22E - 0X22F): TRIG1_CFG_4
149
Trigger Output Unit 1 Configuration and Control Register 5 (0X230 - 0X231): TRIG1_CFG_5
150
Trigger Output Unit 1 Configuration and Control Register 6 (0X232 - 0X233): TRIG1_CFG_6
150
Trigger Output Unit 1 Configuration and Control Register 7 (0X234 - 0X235): TRIG1_CFG_7
150
Trigger Output Unit 1 Configuration and Control Register 8 (0X236 - 0X237): TRIG1_CFG_8
150
0X238 - 0X23F: Reserved
150
Trigger Output Unit 2 Target Time and Output Configuration/Control Registers (0X240 - 0X257)
151
Trigger Output Unit 2 Configuration and Control Register 1 (0X248 - 0X249): TRIG2_CFG_1
151
0X258 - 0X25F: Reserved
151
Trigger Output Unit 3 Target Time and Output Configuration/Control Registers (0X260 - 0X277)
151
0X278 - 0X27F: Reserved
151
Trigger Output Unit 4 Target Time and Output Configuration/Control Registers (0X280 - 0X297)
151
0X298 - 0X29F: Reserved
151
Trigger Output Unit 5 Target Time and Output Configuration/Control Registers (0X2A0 - 0X2B7)
151
0X2B8 - 0X2Bf: Reserved
151
Trigger Output Unit 6 Target Time and Output Configuration/Control Registers (0X2C0 - 0X2D7)
151
0X2F8 - 0X2Ff: Reserved
152
Trigger Output Unit 8 Target Time and Output Configuration/Control Registers (0X300 - 0X317)
152
0X318 - 0X31F: Reserved
152
Trigger Output Unit 9 Target Time and Output Configuration/Control Registers (0X320 - 0X337)
152
0X338 - 0X33F: Reserved
152
Trigger Output Unit 10 Target Time and Output Configuration/Control Registers (0X340 - 0X357)
152
0X358 - 0X35F: Reserved
152
Trigger Output Unit 11 Target Time and Output Configuration/Control Registers (0X360 - 0X377)
152
0X378 - 0X37F: Reserved
152
Trigger Output Unit 12 Target Time and Output Configuration/Control Registers (0X380 - 0X397)
152
Timestamp Ready Register (0X400 - 0X401): TS_RDY
153

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