Maxim Integrated DS1886 Manuals

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Maxim Integrated DS1886 Manual (92 pages)

SFP and PON ONU Controller with Digital LDD Interface

Brand: Maxim Integrated | Category: Controller | Size: 3 MB

General Description
1
Applications
1
Features
1
Table of Contents
2
Absolute Maximum Ratings
10
Recommended Operating Conditions
10
DC Electrical Characteristics
10
DAC Electrical Characteristics
11
Analog Voltage Monitoring Characteristics
11
Digital Thermometer Characteristics
11
AC Electrical Characteristics
12
Startup Timing Characteristics
12
3-Wire Digital Interface Specification
12
I 2 C AC Electrical Characteristics
13
Nonvolatile Memory Characteristics
13
Typical Operating Characteristics
14
Pin Configuration
15
Pin Description
15
Block Diagram
16
Typical Operating Circuit-GPON ONU
17
Typical Operating Circuit-10G PON ONU
18
Detailed Description
19
Monitors and Fault Detection
19
Monitors
19
Figure 1A. ADC Channel Only for TXP When BURST_MODE = 1 in Table 02H, Register 89H
19
Figure 1B. ADC Channel
19
Table 1. Acronyms
19
ADC Monitors and Alarms
20
Alarms and Warnings
20
ADC Timing
20
Table 2. ADC Default Monitor Full-Scale Ranges
20
Right-Shifting ADC Result
21
Differential RSSI Input
21
Figure 2. ADC Round-Robin Timing
21
Figure 3. RSSI Differential Input for High-Side RSSI
21
Laser Bias and Laser Power through TXMON
22
Enhanced RSSI Monitoring (Dual Range Functionality)
22
APD Mode
22
Figure 4. Laser Bias (TXB) and Laser Power (TXP) Monitoring through TXMON
22
Figure 5. RSSI in APD Mode
22
PIN Mode
23
Low-Voltage Operation
23
Figure 6. RSSI in PIN Mode
23
Table 3. RSSI Hysteresis Threshold Values
23
Table 4. RSSI Configuration Registers
23
Power-On Analog (POA)
24
Figure 7. Low-Voltage Hysteresis Example
24
Delta-Sigma Output and Reference
25
Figure 9. Delta-Sigma Output
25
Figure 8. Recommended Shunt Reference and RC Filter for DAC Output
25
Digital I/O Pins
26
Los, Losout
26
Rsel
26
Txd, Txdout
26
IN1, TXF, Transmit Fault (TXFOUT) Output
26
Figure 10. TXFOUT and TXDOUT Logic Diagram
26
Figure 11. RSEL Logic Diagram
26
Die Identification
27
Figure 12A. TXFOUT Nonlatched Operation
27
Figure 12B. TXFOUT Latched
27
Figure 12C. TXFOUT During Power-On
27
DS1886 Master Communication Interface
28
3-Wire Master Interface
28
Protocol
28
Figure 13. 3-Wire Interface Timing Diagram
28
Table 5. 3-Wire Transaction Detail
28
3-Wire Slave Register Map and DS1886 Corresponding Location
29
3-Wire Master Flowchart
29
Table 6. 3-Wire Register Map and DS1886 Corresponding Location
29
Figure 14. 3-Wire Flowchart
30
3-Wire Power-On Reset
31
Figure 15. MAX3710 Brownout Detection Flowchart
31
DS1886 with MAX3710 Operating Modes
32
Open Loop Mode, DPC_EN = 0, APC_EN = 0
32
APC Loop Mode, DPC_EN = 0, APC_EN = 1
32
Dual Closed-Loop Mode, DPC_EN = 1, APC_EN = 1
32
Table 7. DS1886 LUT Functions in Open Loop, APC Loop, and Dual Closed-Loop Modes
32
BIAS, MODULATION, SET_2XAPC, TXCTRL5 Luts
33
Table 8. DS1886 LUT Memory Map for 5-Row Table (Temperature Values Indicated in °C)
33
Table 9. DS1886 LUT Memory Map for 5-Row Table (TINDEX Values Indicated in Hex)
33
MODULATION Value
34
BIAS Value
34
Figure 16. Offset LUT
34
Figure 17. MODULATION LUT (Open Loop and APC Mode)
34
Figure 18. BIAS LUT (Open Loop)
34
Table 10. Temperature Resolution for Offsets
34
Power Leveling
35
Manual MAX3710 Operations
35
I 2 C Communication
35
I 2 C Definition
35
Table 11A. Power Leveling Details (When DS1863_MODE = 0, Default)
35
Table 11B. Power Leveling Details (When DS1863_MODE = 1)
35
Figure 19. I 2 C Timing Diagram
36
I 2 C Protocol
37
Figure 20. Example I 2 C Timing
37
Memory Organization
38
Figure 21. Memory Organization
39
Register Descriptions
40
A2H Lower Memory Register Map
40
A2H Table 01H Register Map
40
A2H Table 02H Register Map
41
A2H Table 04H Register Map
42
A2H Table 05H Register Map
42
A2H Table 06H Register Map
42
A2H Table 08H Register Map
43
A2H Table 09H Register Map
43
Auxiliary A0H Memory Register Map
43
A2H Lower Memory Register Descriptions
44
A2H Lower Memory, Register 00H-01H: TEMP ALARM HI
44
A2H Lower Memory, Register 04H-05H: TEMP WARN HI
44
A2H Lower Memory, Register 02H-03H: TEMP ALARM lo
44
A2H Lower Memory, Register 06H-07H: TEMP WARN lo
44
A2H Lower Memory, Register 08H-09H: V
45
CC Alarm Hi
45
A2H Lower Memory, Register 0Ch-0Dh: V
45
CC Warn Hi
45
A2H Lower Memory, Register 10H-11H: TXB ALARM HI
45
A2H Lower Memory, Register 14H-15H: TXB WARN HI
45
A2H Lower Memory, Register 18H-19H: TXP ALARM HI
45
A2H Lower Memory, Register 1Ch-1Dh: TXP WARN HI
45
A2H Lower Memory, Register 20H-21H: RSSI ALARM HI
45
A2H Lower Memory, Register 24H-25H: RSSI WARN HI
45
A2H Lower Memory, Register 0Ah-0Bh: V
46
CC Alarm lo
46
A2H Lower Memory, Register 0Eh-0Fh: V
46
CC Warn lo
46
A2H Lower Memory, Register 12H-13H: TXB ALARM lo
46
A2H Lower Memory, Register 16H-17H: TXB WARN lo
46
A2H Lower Memory, Register 1Ah-1Bh: TXP ALARM lo
46
A2H Lower Memory, Register 1Eh-1Fh: TXP WARN lo
46
A2H Lower Memory, Register 22H-23H: RSSI ALARM lo
46
A2H Lower Memory, Register 26H-27H: RSSI WARN lo
46
A2H Lower Memory, Register 28H-37H: EMPTY
47
A2H Lower Memory, Register 38H-5Fh: EE
47
A2H Lower Memory, Register 60H-61H: TEMP VALUE
47
A2H Lower Memory, Register 62H-63H: VCC VALUE
48
A2H Lower Memory, Register 64H-65H: TXB VALUE
48
A2H Lower Memory, Register 66H-67H: TXP VALUE
48
A2H Lower Memory, Register 68H-69H: RSSI VALUE
48
A2H Lower Memory, Register 6Ah-6Dh: RESERVED
48
A2H Lower Memory, Register 6Eh: STATUS
49
A2H Lower Memory, Register 6Fh: UPDATE
50
A2H Lower Memory, Register 70H: ALARM 3
51
A2H Lower Memory, Register 71H: ALARM 2
52
A2H Lower Memory, Register 72H-73H: RESERVED
52
A2H Lower Memory, Register 74H: WARN 3
53
A2H Lower Memory, Register 75H: WARN 2
54
A2H Lower Memory, Register 76H-7Ah: RESERVED
54
A2H Lower Memory, Register 7Bh-7Eh: PASSWORD ENTRY (PWE)
55
A2H Lower Memory, Register 7Fh: TBL SEL
55
A2H Table 01H Register Descriptions
56
A2H Table 01H, Register 80H-Bfh: EEPROM
56
A2H Table 01H, Register C0H-F7H: EEPROM
56
A2H Table 01H, Register F8H: ALARM en 3
57
A2H Table 01H, Register F9H: ALARM en 2
58
A2H Table 01H, Register Fah-Fbh: RESERVED
58
A2H Table 01H, Register Fch: WARN en 3
59
A2H Table 01H, Register Fdh: WARN en 2
60
A2H Table 01H, Register Feh-Ffh: RESERVED or EE
60
A2H Table 02H Register Descriptions
61
A2H Table 02H, Register 80H: MODE
61
A2H Table 02H, Register 81H: Temperature Index (TINDEX)
62
A2H Table 02H, Register 82H-83H: MODULATION VALUE
62
A2H Table 02H, Register 84H: RESERVED
62
A2H Table 02H, Register 85H: APC VALUE
63
A2H Table 02H, Register 86H-87H: SET_IBIAS VALUE
63
A2H Table 02H, Register 88H: DACFS
63
A2H Table 02H, Register 89H: CNFGA
64
A2H Table 02H, Register 8Ah: CNFGB
65
A2H Table 02H, Register 8Bh: CNFGC
66
A2H Table 02H, Register 8Ch: RESERVED
66
A2H Table 02H, Register 8Dh: CNFGD
67
A2H Table 02H, Register 8Eh: RIGHT-SHIFT 1 (RSHIFT 1 )
67
A2H Table 02H, Register 8Fh: RIGHT-SHIFT (RSHIFT )
68
A2H Table 02H, Register 90H-91H: XOVER COARSE
68
A2H Table 02H, Register 92H-93H: V
69
CC Scale
69
A2H Table 02H, Register 94H-95H: TXB SCALE
69
A2H Table 02H, Register 96H-97H: TXP SCALE
69
A2H Table 02H, Register 98H-99H: RSSI FINE SCALE
69
A2H Table 02H, Register 9Ah-9Bh: RESERVED
69
A2H Table 02H, Register 9Ch-9Dh: RSSI COARSE SCALE
69
A2H Table 02H, Register 9Eh-9Fh: RESERVED
69
A2H Table 02H, Register A0H-A1H: XOVER FINE
70
A2H Table 02H, Register A2H-A3H: V
70
CC Offset
70
A2H Table 02H, Register A4H-A5H: TXB OFFSET
70
A2H Table 02H, Register A6H-A7H: TXP OFFSET
70
A2H Table 02H, Register A8H-A9H: RSSI FINE OFFSET
70
A2H Table 02H, Register Aah-Abh: RESERVED
70
A2H Table 02H, Register Ach-Adh: RSSI COARSE OFFSET
70
A2H Table 02H, Register Aeh-Afh: INTERNAL TEMP OFFSET
71
A2H Table 02H, Register B0H-B3H: PW1
71
A2H Table 02H, Register B4H-B7H: PW2
72
A2H Table 02H, Register B8H-Bfh: EMPTY
72
A2H Table 02H, Register C0H: PW_ENA
73
A2H Table 02H, Register C1H: PW_ENB
74
A2H Table 02H, Register C2H-C6H: RESERVED
75
A2H Table 02H, Register C7H: TBLSELPON
75
A2H Table 02H, Register C8H-C9H: DAC VALUE
75
A2H Table 02H, Register Cah: INCBYTE
76
A2H Table 02H, Register Cbh: TXCTRL5 DPC
76
A2H Table 02H, Register Cch: IMODMAX
76
A2H Table 02H, Register Cdh: IBIASMAX
77
A2H Table 02H, Register Ceh: DEVICE ID
77
A2H Table 02H, Register Cfh: DEVICE VER
77
A2H Table 02H, Register D0H-Dfh: EMPTY
78
A2H Table 02H, Register E0H: RXCTRL1
78
A2H Table 02H, Register E1H: RXCTRL2
78
A2H Table 02H, Register E2H: SETCML
79
A2H Table 02H, Register E3H: SETLOSH
79
A2H Table 02H, Register E4H: TXCTRL1
79
A2H Table 02H, Register E5H: TXCTRL2
80
A2H Table 02H, Register E6H: TXCTRL3
80
A2H Table 02H, Register E7H: TXCTRL4
80
A2H Table 02H, Register E8H: TXCTRL5 APC OL
81
A2H Table 02H, Register E9H: TXCTRL6
81
A2H Table 02H, Register Eah: TXCTRL7
81
A2H Table 02H, Register Ebh: RESERVED
82
A2H Table 02H, Register Ech: SETLOSH_3945
82
A2H Table 02H, Register Edh: SETLOSL_3945
82
A2H Table 02H, Register Eeh: SETLOSTIMER_3945
83
A2H Table 02H, Register Efh: 3WSET
83
A2H Table 02H, Register F0H: 3WCTRL
84
A2H Table 02H, Register F1H: ADDRESS
84
A2H Table 02H, Register F2H: WRITE
85
A2H Table 02H, Register F3H: READ
85
A2H Table 02H, Register F4H: TXSTAT2
85
A2H Table 02H, Register F5H: TXSTAT1
86
A2H Table 02H, Register F6H: DPCSTAT
86
A2H Table 02H, Register F7H: RXSTAT
86
A2H Table 02H, Register F8H-Ffh: RESERVED
86
A2H Table 04H Register Descriptions
87
A2H Table 04H, Register 80H-A7H: MODULATION or TXCTRL5 LUT
87
A2H Table 04H, Register A8H-Efh: EMPTY
87
A2H Table 04H, Register F0H-F7H: MOD MAX LUT
87
A2H Table 04H, Register F8H-Ffh: MOD OFFSET or SET_IMOD LUT
88
A2H Table 06H Register Descriptions
88
A2H Table 06H, Register 80H-A7H: BIAS or SET_IBIAS
88
A2H Table 06H, Register A8H-Efh: EMPTY
89
A2H Table 06H, Register F0H-F7H: BIAS MAX LUT
89
A2H Table 06H, Register F8H-Ffh: BIAS OFFSET or APC LUT
89
A2H Table 08H Register Descriptions
90
A2H Table 08H, Register 80H-F7H: EMPTY
90
A2H Table 08H, Register F8H-Ffh: INCBYTE
90
A2H Table 09H Register Descriptions
90
A2H Table 09H, Register 80H-F7H: EMPTY
90
A2H Table 09H, Register F8H-Ffh: DAC OFFSET LUT
90
Auxiliary Memory A0H Register Description
91
Auxiliary Memory A0H, Register 00H-Ffh: EEPROM
91
Applications Information
91
Power-Supply Decoupling
91
Layout Considerations
91
SDA and SCL Pullup Resistors
91
Ordering Information
91
Package Information
91
Revision History
92

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