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HMS39C7092
MagnaChip HMS39C7092 Manuals
Manuals and User Guides for MagnaChip HMS39C7092. We have
1
MagnaChip HMS39C7092 manual available for free PDF download: User Manual
MagnaChip HMS39C7092 User Manual (197 pages)
32Bit Embedded Flash MCU
Brand:
MagnaChip
| Category:
Control Unit
| Size: 1.93 MB
Table of Contents
Table of Contents
3
Chapter 1
13
Introduction
13
General Description
14
Figure 1.1 Package Outline
14
Feature
15
Figure 1.2 HMS39C7092 Block Diagram
15
Pin Descriptions
16
Table 1.1 Pin Descriptions
16
Table 1.1 Pin Descriptions (Continued)
17
Table 1.1 Pin Descriptions (Continued)
18
Table 1.1 Pin Descriptions (Continued)
19
Table 1.1 Pin Descriptions (Continued)
20
Operation Mode Description
21
Table 1.2 HMS39C7092 Operation Modes
21
Table 1.3 Pin Assignment by Mode
22
Table 1.3 Pin Assignment by Mode (Continued)
23
Table 1.3 Pin Assignment by Mode (Continued)
24
Memory Map
25
Figure 1.3 HMS39C7092 Memory Map
25
Figure 1.4 Memory Map of Mode 3
25
Figure 1.5 Memory Map of When Mode 4 and Mode 5
26
Figure 1.6 Memory Map of Mode 6 and Mode 7
26
Chapter 2
27
ARM7TDMI Core
27
General Description
28
Feature
28
Core Block Diagram
29
Figure 2.1 ARM7TDMI Core Block Diagram
29
Instruction Set
30
ARM Instruction
30
Figure 2.2 ARM Instruction Set Formats
30
Table 2.1 the ARM Instruction Set
31
Figure 2.3 Register Organization in ARM State
32
Figure 2.4 THUMB Instruction Set Formats
33
THUMB Instruction
33
Table 2.2 THUMB Instruction Set Opcodes
34
Figure 2.5 Register Organization in THUMB State
35
Figure 2.6 Mapping of THUMB State Registers Onto ARM State Registers
35
Figure 2.7 Program Status Register Format
36
Table 2.3 Condition Code Summary
36
The Program Status Registers
36
The Condition Code Flags
37
The Control Bits
37
Table 2.4 PSR Mode Bit Values
38
ARM Instructions
39
Chapter 3
41
BUS Controller
41
Overview
42
Features
42
Figure 3.1 Block Diagram of the Bus Controller
42
Pin Configuration
43
Table 3.1 Bus Controller Pins
43
Bus Controller Registers
44
Table 3.2 BUS Controller Register Map
44
Configuration Registers
45
Operation
46
Area Division
46
Figure 3.2 Access Area Map for each Operating Mode
46
Area Division
47
Chip Select Signals
47
Basic Bus Interface
48
Byte Lane Write Control
48
Figure 3.3 Access Size and Data Alignment Control (8-Bit Access Area)
48
Overview
48
Figure 3.4 Access Size and Data Alignment Control (16-Bit Access Area)
49
Table 3.3 Byte Lane Condition by A0
49
Basic Bus Control Signal Timing
50
Figure 3.5 Bus Control Signal Write Timing for 16-Bit, 1-Wait (Word Access)
50
Figure 3.6 Bus Control Signal Read Timing for 16-Bit, 1-Wait (Word Access)
50
Figure 3.7 Bus Control Signal Write Timing for 16-Bit, 1-Wait (Half-Word Access)
51
Figure 3.8 Bus Control Signal Read Timing for 16-Bit, 1-Wait (Half-Word Access)
51
Figure 3.10 Bus Control Signal Read Timing for 16-Bit, 1-Wait (Byte Access)
52
Figure 3.9 Bus Control Signal Write Timing for 16-Bit, 1-Wait (Byte Access)
52
Figure 3.11 Bus Control Signal Write Timing for 16-Bit, 2-Wait (Word Access)
53
Figure 3.12 Bus Control Signal Read Timing for 16-Bit, 2-Wait (Word Access)
53
Figure 3.13 Bus Control Signal Write Timing for 16-Bit, 2-Wait (Half-Word Access)
54
Figure 3.14 Bus Control Signal Read Timing for 16-Bit, 2-Wait (Half-Word Access)
54
Figure 3.15 Bus Control Signal Write Timing for 16-Bit, 2-Wait (Byte Access)
55
Figure 3.16 Bus Control Signal Read Timing for 16-Bit, 2-Wait (Byte Access)
55
Figure 3.17 Example of Wait State Insertion Timing
56
Wait Control
56
Bus Arbiter
57
Figure 3.18 Example of External Bus Master Operation
58
Chapter 4
59
MCU Controller
59
General Description
60
Pin Function Description
60
Table 4.1 Pin Function Descriptions
60
Register Description
61
Register Memory Map
61
Table 4.2 Memory Map of the MCU Controller
61
Table 4.3 MCU Controller Initial Values in each Mode
61
PINMUX Register
62
MCU Device Code Register (0X0900_002C Read Only)
66
Chapter 5
67
Power Management Unit
67
General Description
68
Figure 5.1 PMU Block Diagram
68
Operation Modes
69
Introduction
69
Reset and Operation Modes
69
Figure 5.2 Reset and Power Management State Machine
70
Power Management Unit Register Map
71
Table 5.1 Register Map of the PMU
71
Register Description
72
Signal Timing Diagram
75
Figure 5.3 Power on Reset Timing Diagram
75
Figure 5.4 Watch Dog Timer Overflow Timing Diagram
75
Power on Reset
75
Watch Dog Timer Overflow
75
Figure 5.5 Soft Reset (from WDT) Timing Diagram
76
Figure 5.6 Soft Reset (from PMU) Timing Diagram
76
Soft-Reset
76
Chapter 6
77
The Interrupt Controller
77
About the Interrupt Controller
78
Figure 6.1 Interrupt Control Flow Diagram
78
Interrupt Control
79
Interrupt Sources
79
Table 6.1 Interrupt Controller Default Setting Value
79
Interrupt Controller Registers
81
Table 6.2 Memory Map of the Interrupt Controller
81
Table 6.3 Interrupt Source Trigger Mode
82
Chapter 7
85
Watchdog Timer
85
General Description
86
Figure 7.1 Watchdog Timer Module Block Diagram
86
Watchdog Timer Introduction
87
Watchdog Timer Operation
88
Figure 7.2 Operation in the Watchdog Timer Mode
88
Figure 7.3 Operation in the Interval Timer Mode
89
Timing of Setting and Clearing the Overflow Flag
89
Watchdog Timer Memory Map
90
Table 7.1 Memory Map of the Watchdog Timer APB Peripheral
90
Watchdog Timer Register Descriptions
91
Table 7.2 Internal Counter Clock Sources
92
Examples of Register Setting
94
Figure 7.4 Interrupt Clear in the Interval Timer Mode
94
Interval Timer Mode
94
Figure 7.5 Interrupt Clear in the Watchdog Timer Mode with Reset Disable
95
Watchdog Timer Mode with Internal Reset Disable
95
Figure 7.6 Interrupt Clear in the Watchdog Timer Mode with Power-On Reset
96
Watchdog Timer Mode with Power-On Reset
96
Figure 7.7 Interrupt Clear in the Watchdog Timer Mode with Manual Reset
97
Watchdog Timer Mode with Manual Reset
97
Chapter 8
99
The General Purpose Timer
99
About the General Purpose Timer Unit
100
Figure 8.1 General-Purpose Timer Unit Module Block Diagram
100
General Purpose Timer Unit Introduction
101
General Purpose Timer Unit Memory Map
102
Register Assignment
102
Table 8.1 Timer Global Control Register Map
102
Table 8.2 Timer Channel Control Register Map
102
Table 8.3 Timer Channel Starting Address
102
General Purpose Timer Unit Register Descriptions
103
Timer Global Control Registers
103
Timer Channel Control Registers
104
General Purpose Timer Unit Operation
108
Figure 8.2 Free-Running Counter Operation
109
Free Running Mode
109
Figure 8.3 Periodic Counter Operation
110
Compare Match Mode
111
Figure 8.4 Example of 0 Output/1 Output
111
Figure 8.5 Example of Toggle Output
112
Figure 8.6 Compare Match Signal Output Timing
112
Figure 8.7 Input Capture Operation
113
Input Capture Mode
113
Figure 8.8 Synchronized Operation Example
114
Synchronized Clear and Write Mode
114
Figure 8.9 PWM Mode Operation Example 1
115
PWM Mode
115
PWM Mode Operation
115
Figure 8.10 PWM Mode Operation Example 2
116
Figure 8.11 Reset-Synchronized PWM Mode Operation Example
117
Chapter 9
119
UART (Universal Asynchronous Receiver/Transmitter)
119
General Description
120
Flash MCU(HMS39C7092)
120
Figure 9.1 TOP BLOCK Diagram
120
Features
121
Signal Description
121
Table 9.1 Signal Descriptions
121
Internal Block Diagram
122
Figure 9.2 Internal UART Diagram
122
Registers Description
123
Table 9.2 UART Register Address Map (0X1500 in UART1)
123
Table 9.3 UART Register Reset Values
123
Table 9.4A Divisor Values for each Baud Rate (Clk=33Mhz)
127
Table 9.4B Divisor Values for each Baud Rate (Clk=36.864Mhz)
127
Table 9.4C Divisor Values for each Baud Rate (Clk=50Mhz)
127
Table 9.5 Interrupt Control Functions
132
UART Operations
134
FIFO Interrupt Mode Operation
134
FIFO Polled Mode Operation
135
Register Summary
136
Table 9.6 Summary of Registers
136
Chapter 10
137
GPIO (General Purpose Input Output)
137
General Description
138
Figure 10.1 GPIO Block Diagram and PADS Connections (Example for Port a and Port B)
138
GPIO Registers
139
Register Memory Map
139
Table 10.1 GPIO Register Memory Map
139
Register Description
140
Functional Description
141
Chapter 11
143
On-Chip SRAM
143
General Description
144
Function Description
144
Chapter 12
145
On-Chip Flash Memory
145
General Description
146
Features
146
Table 12.1 Operating Mode
147
Block Diagram
148
Figure 12.1 Block Diagram of Flash Memory
148
Table 12.2 Signal Description of Figure 12.1(BUS Interface)
149
Flash Memory Register Description
150
Table 12.3 Flash Memory Registers
150
Table 12.4 Control Register
152
Table 12.5 Erase Sector Register
153
Table 12.6 FMPR (Status & Power Register)
154
On-Board Programming Mode
155
12.5.1 Boot Mode
155
Figure 12.2 System Configuration When Using On-Board Boot Mode
155
Figure 12.3 Boot Mode Execution Procedure
156
12.5.2 User Program Mode
158
Figure 12.4 User Mode Execution Procedure
158
Flash Memory Programming/Erasing
160
Program & Program-Verify Mode
160
Figure 12.5 Flash Program & Program Verify Sequence
161
12.6.2 Pre-Program & Pre-Program Verify Mode
162
Figure 12.6 Flash Pre-Program & Pre-Program Verify Sequence
163
12.6.3 Erase & Erase Verify Mode
164
Figure 12.7 Flash Erase & Erase Verify Sequence
165
12.6.4 Erase Algorithm
166
Figure 12.8 Flash Erase Algorithm
166
Flash Memory PROM Mode
167
12.7.1 PROM Mode Setting
167
Table 12.7 FR_SEL Value for Access to Internal Register
167
Table 12.8 Setting for Register Read/Write
167
12.7.2 Memory Map
168
12.7.3 PROM Mode Operation
168
Table 12.9 Erase Sector Register
168
12.7.4 Timing Diagram and AC/DC Characteristics
169
Figure 12.9 Timing Diagram of Read
169
Table 12.10 Setting for Flash PROM Read/Write
169
Figure 12.10 Timing Diagram of Pre-Program/Program
170
Figure 12.11 Timing Diagram of Erase
170
Figure 12.12 Timing Diagram of Pre-Program/Program Verify
171
Figure 12.13 Timing Diagram of Erase Verify
171
Table 12.11 DC Characteristics
172
Table 12.12 AC Characteristics
172
Chapter 13
173
A/D Converter
173
Overview
174
Features
174
Figure 13.1 Block Diagram of A/D Converter
174
Pin Configuration
175
Table 13.1 A/D Converter Pins
175
A/D Converter Registers
176
Register Descriptions
176
Table 13.2 Summarizes the A/D Converterís Registers
176
Operation
179
Figure 13.2 A/D Converter Operation
179
Interrupts
180
Usage Notes
181
Figure 13.3 Example of Analog Input Circuit
182
Figure 13.4 A/D Converter Accuracy Definitions (1)
182
Figure 13.5 A/D Converter Accuracy Definitions (2)
183
Example
184
Chapter 14
186
Electrical Characteristics
186
Absolute Maximum Ratings
187
Recommended Operating Conditions
187
Table 14.1 Absolute Maximum Ratings
187
Table 14.2 Recommended Operating Conditions
187
DC Characteristics
188
Table 14.3 DC Characteristics
188
Table 14.4 IO Circuits with Pull-Ups
188
Table 14.5 IO Circuits with Pull-Downs
188
AC Characteristics
189
Table 14.6 Clock Timing
189
Table 14.7 Control Signal Timing
189
Table 14.8 Bus Timing (Units: Ns)
190
AD Conversion Characteristics
191
Table 14.9 Operating Conditions of the AD Conversion
191
Table 14.10 Electrical Characteristics of the AD Converter
191
Operational Timing
192
14.5.1 Clock Timing
192
14.5.2 Reset Timing
192
Figure 14.1 the Settling Time of the Crystal Oscillator
192
Figure 14.2 Reset Input Timing
192
14.5.3 Bus Timing
193
Figure 14.3 the Write Timing Diagram of the Bus Controller
193
Figure 14.4 the Read Timing Diagram of the Bus Controller
193
Figure 14.5 Basic Bus Cycle with External Wait State
194
Figure 14.6 Bus Release Mode Timing
194
A-1 Package Dimension
197
Appendix
197
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