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GD32A513
GigaDevice Semiconductor GD32A513 Manuals
Manuals and User Guides for GigaDevice Semiconductor GD32A513. We have
1
GigaDevice Semiconductor GD32A513 manual available for free PDF download: User Manual
GigaDevice Semiconductor GD32A513 User Manual (673 pages)
Arm Cortex-M33 32-bit MCU
Brand:
GigaDevice Semiconductor
| Category:
Computer Hardware
| Size: 9 MB
Table of Contents
Table of Contents
2
List of Figures
16
List of Tables
22
System and Memory Architecture
25
Arm ® Cortex ® -M33 Processor
25
Figure 1-1. the Structure of the Cortex
25
System Architecture
26
Table 1-1. Bus Interconnection Matrix
26
Memory Map
28
Figure 1-2. Series System Architecture of GD32A513 Series
28
Table 1-2. Memory Map of GD32A513 Devices
29
On-Chip SRAM Memory
32
Figure 1-3. ECC Decoder
33
On-Chip Flash Memory
34
Boot Mode
34
System Configuration Controller
34
System Configuration Registers
35
System Configuration Register 0 (SYSCFG_CFG0)
35
System Configuration Register 1 (SYSCFG_CFG1)
35
EXTI Sources Selection Register 0 (SYSCFG_EXTISS0)
36
EXTI Sources Selection Register 1 (SYSCFG_EXTISS1)
37
EXTI Sources Selection Register 2 (SYSCFG_EXTISS2)
38
EXTI Sources Selection Register 3 (SYSCFG_EXTISS3)
40
System Configuration Register 2 (SYSCFG_CFG2)
41
System Status Register (SYSCFG_STAT)
42
System Configuration Register 3 (SYSCFG_CFG3)
43
TIMER Input Source Select Register (SYSCFG_TIMERINSEL)
44
Device Electronic Signature
46
Memory Density Information
46
Unique Device ID (96 Bits)
47
Flash Memory Controller (FMC)
49
Overview
49
Characteristics
49
Function Overview
49
Flash Memory Architecture
49
Table 2-1. Base Address and Size for 384 KB Flash Memory
50
Table 2-2. Base Address and Size for 256 KB Flash Memory
50
Table 2-3. Base Address and Size for 128KB Flash Memory
51
Table 2-4. 64KB Flash Base Address and Size for Flash Memory
52
Error Checking and Correcting (ECC)
53
Read Operations
54
Table 2-5. the Relation between WSCNT and AHB Clock Frequency When LDO Is 1.1V
54
Dual Bank Architecture with Read-While-Write (RWW) Capability
55
Unlock the Fmc_Ctlx Register
55
Page Erase
56
Mass Erase
57
Figure 2-1. Process of Page Erase Operation
57
Main Flash Programming
58
Figure 2-2. Process of Mass Erase Operation
58
Main Flash Fast Programming
60
Figure 2-3. Process of Word Program Operation
60
Figure 2-4. Process of Fast Programming Operation
61
Check Blank Command
63
OTP Programming
63
Shared RAM
63
Data Flash Operation
64
Emulated EEPROM
65
Option Bytes 0 Erase
66
Option Bytes Programming
66
Option Bytes Description
67
Table 2-6. Option Bytes 0
68
Table 2-7. Option Bytes 1 (384K Flash or 256K Flash)
69
Table 2-8. Option Bytes 1 (128K Flash)
70
Table 2-9. Option Bytes 1 (64K Flash)
71
Erase / Program Protection
72
Table 2-10. OB_BK0WP Bit for Pages Protected
73
Table 2-11. OB_BK1WP Bit for Pages Protected
73
Table 2-12. OB_DFWP Bit for Pages Protected (EFALC: Except 0X3 / 0Xc / 0Xe)
74
Table 2-13. OB_DFWP Bit for Pages Protected (EFALC: 0X3 / 0Xc / 0Xe)
74
Security Protection
75
Error Description
75
Table 2-14. OB_EPWP Bit for Protected
75
Table 2-15. PGSERR Conditions
76
Table 2-16. PGAERR Conditions
77
Table 2-17. PGERR Conditions
77
Table 2-18. WPERR Conditions
77
Register Definition
78
Wait State Register (FMC_WS)
78
ECC Control and Status Register (FMC_ECCCS)
79
Unlock Key Register 0 (FMC_KEY0)
81
Status Register 0 (FMC_STAT0)
81
Control Register 0 (FMC_CTL0)
82
Address Register 0 (FMC_ADDR0)
84
Option Byte Unlock Key Register (FMC_OBKEY)
84
Unlock Key Register 1 (FMC_KEY1)
85
Status Register 1 (FMC_STAT1)
85
Control Register 1 (FMC_CTL1)
86
Address Register 1 (FMC_ADDR1)
88
EEPROM Counter Register (FMC_EPCNT)
88
Option Byte Status Register (FMC_OBSTAT)
89
Erase / Program Protection Register 0 (FMC_WP0)
90
Erase / Program Protection Register 1 (FMC_WP1)
90
Option Byte 1 Control and Status Register (FMC_OB1CS)
90
Product ID Register (FMC_PID)
91
Power Management Unit (PMU)
93
Overview
93
Characteristics
93
Function Overview
93
Figure 3-1. Power Supply Overview
93
Backup Domain
94
VDD
95
Figure 3-2. Waveform of the por / PDR
95
Figure 3-3. Waveform of the BOR
96
Figure 3-5. Waveform of the OVD Threshold
96
Figure 3-4. Waveform of the LVD Threshold
97
Power Domain
98
Power Saving Modes
98
Table 3-1. Power Saving Mode Summary
100
Register Definition
101
Control Register (PMU_CTL)
101
Control and Status Register (PMU_CS)
102
Backup Registers (BKP)
105
Overview
105
Characteristics
105
Function Overview
105
RTC Clock Calibration
105
Tamper Detection
105
Register Definition
107
Backup Data Register X (Bkp_Datax) (X= 0
107
RTC Signal Output Control Register (BKP_OCTL)
107
Tamper Pin Control Register (BKP_TPCTL)
108
Tamper Control and Status Register (BKP_TPCS)
109
Reset and Clock Unit (RCU)
111
Reset Control Unit (RCTL)
111
Overview
111
Function Overview
111
Clock Control Unit (CCTL)
112
Overview
112
Figure 5-1. the System Reset Circuit
112
Figure 5-2. Clock Tree
113
Characteristics
114
Function Overview
114
Figure 5-3. HXTAL Clock Source
114
Figure 5-4. HXTAL Clock Source in Bypass Mode
115
Table 5-1. Clock Source Select
117
Table 5-2. Core Domain Voltage Selected in Deep-Sleep Mode
118
Register Definition
119
Control Register (RCU_CTL)
119
Configuration Register 0 (RCU_CFG0)
121
Interrupt Register (RCU_INT)
124
APB2 Reset Register (RCU_APB2RST)
127
APB1 Reset Register (RCU_APB1RST)
129
AHB Enable Register (RCU_AHBEN)
131
APB2 Enable Register (RCU_APB2EN)
132
APB1 Enable Register (RCU_APB1EN)
134
Backup Domain Control Register (RCU_BDCTL)
136
Reset Source /Clock Register (RCU_RSTSCK)
137
AHB Reset Register (RCU_AHBRST)
140
Configuration Register 1 (RCU_CFG1)
142
Configuration Register 2 (RCU_CFG2)
143
Voltage Key Register (RCU_VKEY)
144
Deep-Sleep Mode Voltage Register (RCU_DSV)
145
Interrupt / Event Controller (EXTI)
146
Overview
146
Characteristics
146
Interrupts Function Overview
146
Table 6-1. NVIC Exception Types in Cortex ® -M33
147
Table 6-2. Interrupt Vector Table
147
External Interrupt and Event (EXTI) Block Diagram
150
External Interrupt and Event Function Overview
150
Figure 6-1. Block Diagram of EXTI
150
Table 6-3. EXTI Source
151
Register Definition
153
Interrupt Enable Register (EXTI_INTEN)
153
Event Enable Register (EXTI_EVEN)
153
Rising Edge Trigger Enable Register (EXTI_RTEN)
154
Falling Edge Trigger Enable Register (EXTI_FTEN)
154
Software Interrupt Event Register (EXTI_SWIEV)
154
Pending Register (EXTI_PD)
155
Trigger Selection Controller (TRIGSEL)
156
Overview
156
Characteristics
156
Function Overview
156
Internal Connect
157
Figure 7-1. TRIGSEL Main Composition Example
157
Table 7-1. Trigger Input Bit Fields Selection
157
Table 7-2. TRIGSEL Input and Output Mapping
159
Register Definition
162
Trigger Selection for EXTOUT0 Register (TRIGSEL_EXTOUT0)
162
Trigger Selection for EXTOUT1 Register (TRIGSEL_EXTOUT1)
163
Trigger Selection for ADC0 Register (TRIGSEL_ADC0)
164
Trigger Selection for ADC1 Register (TRIGSEL_ADC1)
164
Trigger Selection for DAC Register (TRIGSEL_DAC)
165
Trigger Selection for TIMER0_ITI Register (TRIGSEL_TIMER0IN)
165
Trigger Selection for TIMER0_BRKIN Register (TRIGSEL_TIMER0BRKIN)
166
Trigger Selection for TIMER7_ITI Register (TRIGSEL_TIMER7IN)
167
Trigger Selection for TIMER7_BRKIN Register (TRIGSEL_TIMER7BRKIN)
168
Trigger Selection for TIMER19_ITI Register (TRIGSEL_TIMER19IN)
169
Trigger Selection for TIMER19_BRKIN Register (TRIGSEL_TIMER19BRKIN)
170
Trigger Selection for TIMER20_ITI Register (TRIGSEL_TIMER20IN)
171
Trigger Selection for TIMER20_BRKIN Register (TRIGSEL_TIMER20BRKIN)
172
Trigger Selection for TIMER1_ITI Register (TRIGSEL_TIMER1IN)
173
Trigger Selection for MFCOM Register (TRIGSEL_MFCOM)
174
Trigger Selection for CAN0 Register (TRIGSEL_CAN0)
175
Trigger Selection for CAN1 Register (TRIGSEL_CAN1)
176
General-Purpose and Alternate-Function I/Os (GPIO and AFIO)
177
Overview
177
Characteristics
177
Function Overview
177
Figure 8-1. Basic Structure of a General-Pupose I/O
178
Table 8-1. GPIO Configuration Table
178
GPIO Pin Configuration
179
External Interrupt/Event Lines
179
Alternate Functions (AF)
179
Additional Functions
179
Input Configuration
180
Output Configuration
180
Figure 8-2. Basic Structure of Input Configuration
180
Figure 8-3. Basic Structure of Output Configuration
180
Analog Configuration
181
Alternate Function (AF) Configuration
181
Figure 8-4. Basic Structure of Analog Configuration
181
Figure 8-5. Basic Structure of Alternate Function Configuration
181
GPIO Locking Function
182
GPIO Single Cycle Toggle Function
182
Register Definition
183
Port Control Register (Gpiox_Ctl, X=A
183
Port Output Mode Register (Gpiox_Omode, X=A
185
Port Output Speed Register (Gpiox_Ospd, X=A
186
Port Pull-Up/Down Register (Gpiox_Pud, X=A
188
Port Input Status Register (Gpiox_Istat, X=A
190
Port Output Control Register (Gpiox_Octl, X=A
190
Port Bit Operate Register (Gpiox_Bop, X=A
190
Port Configuration Lock Register (Gpiox_Lock, X=A
191
Alternate Function Selected Register 0 (Gpiox_Afsel0, X=A
192
Alternate Function Selected Register 1 (Gpiox_Afsel1, X=A
193
Bit Clear Register (Gpiox_Bc, X=A
194
Port Bit Toggle Register (Gpiox_Tg, X=A
195
Multi-Function Communication Interface (MFCOM)
196
Overview
196
Characteristics
196
Block Diagram
196
Figure 9-1. MFCOM Block Diagram
196
Function Overview
197
Clocking and Resets
197
Shifter
197
Figure 9-2. Shifter Microarchitecture
198
Table 9-1. Mode of Shifter
198
Timer
199
Pin
201
Interrupts and DMA Requests
202
Triggers
202
Table 9-2. MFCOM Interrupts and DMA Requests
202
Typical Configuration of Application
203
Register Definition
213
Control Register (MFCOM_CTL)
213
Pin Data Register (MFCOM_PINDATA)
213
Shifter Status Register (MFCOM_SSTAT)
214
Shifter Error Register (MFCOM_SERR)
214
Timer Status Register (MFCOM_TMSTAT)
215
Shifter Status Interrupt Enable Register (MFCOM_SSIEN)
216
Shifter Error Interrupt Enable Register (MFCOM_SEIEN)
216
Timer Status Interrupt Enable Register (MFCOM_TMSIEN)
217
Shifter Status DMA Enable Register (MFCOM_SSDMAEN)
217
Shifter Control X Register (Mfcom_Sctlx)
218
Shifter Configuration X Register (Mfcom_Scfgx)
219
Shifter Buffer X Register (Mfcom_Sbufx)
220
Shifter Buffer X Bit Swapped Register (Mfcom_Sbufbisx)
221
Shifter Buffer X Byte Swapped Register (Mfcom_Sbufbysx)
221
Shifter Buffer X Bit Byte Swapped Register (Mfcom_Sbufbbsx)
221
Timer Control X Register (Mfcom_Tmctlx)
222
Timer Configuration X Register (Mfcom_Tmcfgx)
223
Timer Compare X Register (Mfcom_Tmcmpx)
225
CRC Calculation Unit (CRC)
227
Overview
227
Characteristics
227
Figure 10-1. Block Diagram of CRC Calculation Unit
227
Function Overview
228
Register Definition
229
Data Register (CRC_DATA)
229
Free Data Register (CRC_FDATA)
229
Control Register (CRC_CTL)
230
Initialization Data Register (CRC_IDATA)
230
Polynomial Register (CRC_POLY)
231
Direct Memory Access Controller (DMA)
232
Overview
232
Characteristics
232
Block Diagram
233
Function Overview
233
DMA Operation
233
Figure 11-1. Block Diagram of DMA
233
Table 11-1. DMA Transfer Operation
234
Peripheral Handshake
235
Figure 11-2. Handshake Mechanism
235
Arbitration
236
Address Generation
236
Circular Mode
236
Memory to Memory Mode
236
Channel Configuration
236
Interrupt
237
Table 11-2. Interrupt Events
237
DMA Request Mapping
238
Figure 11-3. DMA Interrupt Logic
238
Register Definition
239
Interrupt Flag Register (DMA_INTF)
239
Interrupt Flag Clear Register (DMA_INTC)
240
Channel X Control Register (Dma_Chxctl)
240
Channel X Counter Register (Dma_Chxcnt)
242
Channel X Peripheral Base Address Register (Dma_Chxpaddr)
243
Channel X Memory Base Address Register (Dma_Chxmaddr)
243
DMA Request Multiplexer (DMAMUX)
245
Overview
245
Characteristics
245
Block Diagram
246
Function Overview
246
Figure 12-1. Block Diagram of DMAMUX
246
DMAMUX Signals
247
DMAMUX Request Multiplexer
247
Table 12-1. DMAMUX Signals
247
Figure 12-2. Synchronization Mode
248
Figure 12-3. Event Generation
249
DMAMUX Request Generator
250
Channel Configurations
250
Interrupt
251
DMAMUX Mapping
251
Table 12-2. Interrupt Events
251
Table 12-3. Request Multiplexer Input Mapping
252
Table 12-4. Trigger Input Mapping
254
Table 12-5. Synchronization Input Mapping
255
Register Definition
256
Request Multiplexer Channel X Configuration Register (Dmamux_Rm_Chxcfg)
256
Request Multiplexer Channel Interrupt Flag Register (DMAMUX_RM_INTF)
257
Request Multiplexer Channel Interrupt Flag Clear Register (DMAMUX_RM_INTC)
257
Request Generator Channel X Configuration Register (Dmamux_Rg_Chxcfg)
258
Request Generator Interrupt Flag Register (DMAMUX_RG_INTF)
259
Request Generator Interrupt Flag Clear Register (DMAMUX_RG_INTC)
259
Debug (DBG)
261
Introduction
261
JTAG/SW Function Overview
261
Switch JTAG or SW Interface
261
Pin Assignment
261
JTAG Daisy Chained Structure
262
Debug Reset
262
JEDEC-106 ID Code
262
Debug Hold Function Overview
262
Debug Support for Power Saving Mode
262
Table 13-1. Pin Assignment
262
Debug Support for TIMER, I2C, WWDGT and FWDGT
263
Registers Definition
264
ID Code Register (DBG_ID)
264
Control Register (DBG_CTL)
264
Analog-To-Digital Converter (ADC)
267
Overview
267
Characteristics
267
Pins and Internal Signals
268
Figure 14-1. ADC Module Block Diagram
268
Table 14-1. ADC Internal Input Signals
268
Table 14-2. ADC Input Pins Definition
268
Function Overview
269
Foreground Calibration Function
269
ADC Clock
270
ADC Enable
270
Routine Sequence
270
Operation Modes
270
Figure 14-2. Single Operation Mode
270
Figure 14-3. Continuous Operation Mode
271
Figure 14-4. Scan Operation Mode, Continuous Disable
272
Figure 14-5. Scan Operation Mode, Continuous Enable
272
Conversion Result Threshold Monitor
273
Figure 14-6. Discontinuous Operation Mode
273
Data Storage Mode
274
Sample Time Configuration
274
Figure 14-7. Data Storage Mode of 12-Bit Resolution
274
Figure 14-8. Data Storage Mode of 10-Bit Resolution
274
Figure 14-9. Data Storage Mode of 8-Bit Resolution
274
Figure 14-10. Data Storage Mode of 6-Bit Resolution
274
External Trigger Configuration
275
DMA Request
275
ADC Internal Channels
275
Table 14-3. External Trigger Source for Routine Sequence
275
Programmable Resolution (DRES)
276
Table 14-4. T CONV Timings Depending on Resolution
276
On-Chip Hardware Oversampling
277
Figure 14-11. 20-Bit to 16-Bit Result Truncation
277
Figure 14-12. Numerical Example with 5-Bits Shift and Rounding
277
ADC Sync Mode
278
Table 14-5. Maximum Output Results for N and M (Grayed Values Indicates Truncation)
278
Free Mode
279
Figure 14-13. ADC Sync Block Diagram
279
Table 14-6. ADC Sync Mode Table
279
Routine Parallel Mode
280
Routine Follow-Up Fast Mode
280
Figure 14-14. Routine Parallel Mode on 16 Channels
280
Routine Follow-Up Slow Mode
281
Figure 14-15. Routine Follow-Up Fast Mode on 1 Channel in Continuous Operation Mode
281
Figure 14-16. Routine Follow-Up Slow Mode on 1 Channel
281
ADC Interrupts
282
Register Definition
283
Status Register (ADC_STAT)
283
Control Register 0 (ADC_CTL0)
284
Control Register 1 (ADC_CTL1)
286
Sample Time Register 0 (ADC_SAMPT0)
287
Sample Time Register 1 (ADC_SAMPT1)
288
Watchdog High Threshold Register 0 (ADC_WDHT0)
289
Watchdog Low Threshold Register 0 (ADC_WDLT0)
289
Routine Sequence Register 0 (ADC_RSQ0)
290
Routine Sequence Register 1 (ADC_RSQ1)
290
Routine Sequence Register 2 (ADC_RSQ2)
291
Routine Data Register (ADC_RDATA)
292
Oversample Control Register (ADC_OVSAMPCTL)
292
Watchdog 1 Channel Selection Register (ADC_WD1SR)
294
Watchdog Threshold Register 1 (ADC_WDT1)
294
Digital-To-Analog Converter (DAC)
296
Overview
296
Characteristics
296
Figure 15-1. DAC Block Diagram
296
Function Overview
297
DAC Enable
297
DAC Output Buffer
297
DAC Data Configuration
297
Table 15-1. DAC I/O Description
297
Table 15-2. DAC Triggers and Outputs Summary
297
DAC Trigger
298
DAC Conversion
298
DAC Noise Wave
298
Table 15-3. Triggers of DAC
298
DAC Output Voltage
299
DMA Request
299
Figure 15-2. DAC LFSR Algorithm
299
Figure 15-3. DAC Triangle Noise Wave
299
Register Definition
301
Dacx Control Register 0 (DAC_CTL0)
301
Dacx Software Trigger Register (DAC_SWT)
302
Dacx_Out0 12-Bit Right-Aligned Data Holding Register (DAC_OUT0_R12DH)
303
Dacx_Out0 12-Bit Left-Aligned Data Holding Register (DAC_OUT0_L12DH)
303
Dacx_Out0 8-Bit Right-Aligned Data Holding Register (DAC_OUT0_R8DH)
304
Dacx_Out0 Data Output Register (DAC_OUT0_DO)
304
Dacx Status Register 0 (DAC_STAT0)
305
Watchdog Timer (WDGT)
306
Free Watchdog Timer (FWDGT)
306
Overview
306
Characteristics
306
Function Overview
306
Figure 16-1. Free Watchdog Block Diagram
307
Table 16-1. Min/Max FWDGT Timeout Period at 40Khz (IRC40K)
308
Register Definition
309
Window Watchdog Timer (WWDGT)
313
Overview
313
Characteristics
313
Function Overview
313
Figure 16-2. Window Watchdog Timer Block Diagram
313
Figure 16-3. Window Watchdog Timing Diagram
314
Table 16-2. Min-Max Timeout Value at 50 Mhz
315
Register Definition
316
Real-Time Clock (RTC)
318
Overview
318
Characteristics
318
Function Overview
318
RTC Reset
319
RTC Reading
319
Figure 17-1. Block Diagram of RTC
319
RTC Configuration
320
RTC Flag Assertion
320
Figure 17-2. RTC Second and Alarm Waveform Example (RTC_PSC = 3, RTC_ALRM = 2)
321
Figure 17-3. RTC Second and Overflow Waveform Example (RTC_PSC= 3)
321
Register Definition
322
RTC Interrupt Enable Register (RTC_INTEN)
322
RTC Control Register (RTC_CTL)
322
RTC Prescaler High Register (RTC_PSCH)
323
RTC Prescaler Low Register (RTC_PSCL)
324
RTC Divider High Register (RTC_DIVH)
324
RTC Divider Low Register (RTC_DIVL)
324
RTC Counter High Register (RTC_CNTH)
325
RTC Counter Low Register (RTC_CNTL)
325
RTC Alarm High Register (RTC_ALRMH)
326
RTC Alarm Low Register (RTC_ALRML)
326
Timer
327
Table 18-1. Timers (Timerx) Are Divided into Three Sorts
327
Advanced Timer (Timerx, X=0, 7, 19, 20)
328
Overview
328
Characteristics
328
Block Diagram
329
Function Overview
329
Figure 18-1. Advanced Timer Block Diagram
329
Table 18-2. Advanced Timer Channel Description
329
Figure 18-2. Timing Chart of Internal Clock Divided by 1
330
Figure 18-3. Timing Chart of PSC Value Change from 0 to 2
331
Figure 18-4. Timing Chart of up Counting Mode, PSC=0/2
332
Figure 18-5. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
333
Figure 18-6. Timing Chart of down Counting Mode, PSC=0/2
334
Figure 18-7. Timing Chart of down Counting Mode, Change Timerx_Car on the Go
334
Figure 18-8. Timing Chart of Center-Aligned Counting Mode
336
Figure 18-9. Repetition Counter Timing Chart of Center-Aligned Counting Mode
337
Figure 18-10. Repetition Counter Timing Chart of up Counting Mode
337
Figure 18-11. Repetition Counter Timing Chart of down Counting Mode
338
Figure 18-12. Channel 0 Input Capture Principle
339
Figure 18-13. Multi Mode Channel 0 Input Capture Principle
339
Figure 18-14. Channel Output Compare Principle (When Mchxmsel = 2'00, X=0, 1, 2, 3)
340
Figure 18-15. Channel Output Compare Principle (When Mchxmsel = 2'01, X=0, 1, 2, 3)
340
Figure 18-16. Channel Output Compare Principle (with Complementary Output When Mchxmsel = 2'11, X=0,1,2,3)
341
Figure 18-17. Output-Compare under Three Modes
343
Figure 18-18. EAPWM Timechart
344
Figure 18-19. CAPWM Timechart
344
Table 18-3.The Composite PWM Pulse Width
345
Figure 18-20. Channel X Output PWM with (Chxval < Chxcomval_Add)
346
Figure 18-21. Channel X Output PWM with (Chxval = Chxcomval_Add)
346
Figure 18-22. Channel X Output PWM with (Chxval > Chxcomval_Add)
346
Figure 18-23. Channel X Output PWM with Chxval or Chxcomval_Add Exceeds CARL
347
Figure 18-24. Channel X Output PWM Duty Cycle Changing with Chxcomval_Add
347
Figure 18-25. Four Channels Outputs in Composite PWM Mode
348
Figure 18-26. Chx_O Output with a Pulse in Edge-Aligned Mode (Chxompsel≠2'B00)
349
Figure 18-27. Chx_O Output with a Pulse in Center-Aligned Mode (Chxompsel≠2'B00)
349
Table 18-4. Complementary Outputs Controlled by Parameters (Mchxmsel =2'B11)
351
Figure 18-28. Channel Output Complementary PWM with Dead-Time Insertion
352
Figure 18-29. Break Function Diagram
353
Figure 18-30. Output Behavior of the Channel in Response to a Break (the Break High Active)
354
Figure 18-31. Counter Behavior with CI0FE0 Polarity Non-Inverted in Mode 2
355
Table 18-5. Counting Direction in Different Quadrature Decoder Mode
355
Figure 18-32. Counter Behavior with CI0FE0 Polarity Inverted in Mode 2
356
Figure 18-33. Hall Sensor Is Used for BLDC Motor
356
Figure 18-34. Hall Sensor Timing between Two Timers
357
Figure 18-35. Restart Mode
358
Table 18-6. Examples of Slave Mode
358
Figure 18-36. Pause Mode
359
Figure 18-37. Event Mode
359
Figure 18-38. Single Pulse Mode Timerx_Chxcv=0X04, Timerx_Car=0X99
360
Figure 18-39. TIMER0 Master/Slave Mode Example
361
Figure 18-40. Triggering TIMER0 with Enable Signal of TIMER1
362
Figure 18-41. Triggering TIMER0 and TIMER1 with Timer1'S CI0 Input
363
Registers Definition (Timerx, X=0, 7, 19, 20)
364
General Level0 Timer (Timerx, X=1)
422
Overview
422
Characteristics
422
Block Diagram
422
Figure 18-42. General Level 0 Timer Block Diagram
422
Function Overview
423
Figure 18-43. Timing Chart of Internal Clock Divided by 1
424
Figure 18-44. Timing Chart of PSC Value Change from 0 to 2
425
Figure 18-45. Timing Chart of up Counting Mode, PSC=0/2
426
Figure 18-46. Timing Chart of up Counting, Change Timerx_Car on the Go
426
Figure 18-47. Timing Chart of down Counting Mode, PSC=0/2
427
Figure 18-48. Timing Chart of down Counting Mode, Change Timerx_Car on the Go
428
Figure 18-49. Timing Chart of Center-Aligned Counting Mode
429
Figure 18-50. Channels Input Capture Principle
430
Figure 18-51. Channel Output Compare Principle (X=0,1,2,3)
431
Figure 18-52. Output-Compare under Three Modes
432
Figure 18-53. EAPWM Timechart
433
Figure 18-54. CAPWM Timechart
433
Table 18-7. Counting Direction in Different Quadrature Decoder Mode
434
Figure 18-55. Counter Behavior with CI0FE0 Polarity Non-Inverted in Mode 2
435
Figure 18-56. Counter Behavior with CI0FE0 Polarity Inverted in Mode 2
435
Table 18-8. Examples of Slave Mode
435
Figure 18-57. Restart Mode
436
Figure 18-58. Pause Mode
436
Figure 18-59. Event Mode
437
Figure 18-60. Single Pulse Mode Timerx_Chxcv = 0X04, Timerx_Car=0X99
438
Registers Definition (Timerx, X=1)
439
Basic Timer (Timerx, X=5, 6)
462
Overview
462
Characteristics
462
Block Diagram
462
Function Overview
462
Figure 18-61. Basic Timer Block Diagram
462
Figure 18-62. Timing Chart of Internal Clock Divided by 1
463
Figure 18-63. Timing Chart of PSC Value Change from 0 to 2
463
Figure 18-64. Timing Chart of up Counting Mode, PSC=0/2
464
Figure 18-65. Timing Chart of up Counting Mode, Change Timerx_Car on the Go
465
Registers Definition (Timerx, X=5, 6)
466
Universal Synchronous/Asynchronous Receiver /Transmitter (USART)
471
Overview
471
Characteristics
471
Function Overview
472
Table 19-1. Description of USART Important Pins
472
USART Frame Format
473
Figure 19-1. USART Module Block Diagram
473
Figure 19-2. USART Character Frame (8 Bits Data and 1 Stop Bit)
473
Baud Rate Generation
474
Table 19-2. Configuration of Stop Bits
474
USART Transmitter
475
Figure 19-3. USART Transmit Procedure
475
USART Receiver
476
Use DMA for Data Buffer Access
477
Figure 19-4. Oversampling Method of a Receive Frame Bit (OSB=0)
477
Figure 19-5. Configuration Step When Using DMA for USART Transmission
478
Hardware Flow Control
479
Figure 19-6. Configuration Step When Using DMA for USART Reception
479
Figure 19-7. Hardware Flow Control between Two Usarts
479
Multi-Processor Communication
480
Figure 19-8. Hardware Flow Control
480
LIN Mode
481
Synchronous Mode
482
Figure 19-9. Break Frame Occurs During Idle State
482
Figure 19-10. Break Frame Occurs During a Frame
482
Irda SIR ENDEC Mode
483
Figure 19-11. Example of USART in Synchronous Mode
483
Figure 19-12. 8-Bit Format USART Synchronous Waveform (CLEN=1)
483
Figure 19-13. Irda SIR ENDEC Module
484
Figure 19-14. Irda Data Modulation
484
Half-Duplex Communication Mode
485
Figure 19-15. ISO7816-3 Frame Format
485
Figure 19-16. USART Receive FIFO Structure
488
Table 19-3. USART Interrupt Requests
488
Figure 19-17. USART Interrupt Mapping Diagram
490
Figure 20-1. I2C Module Block Diagram
510
Table 20-1. Definition of I2C-Bus Terminology (Refer to the I2C Specification of Philips Semiconductors)
511
Figure 20-2. Data Validation
512
Figure 20-3. START and STOP Signal
513
Figure 20-4. I2C Communication Flow with 10-Bit Address (Master Transmit)
513
Figure 20-5. I2C Communication Flow with 7-Bit Address (Master Transmit)
514
Figure 20-6. I2C Communication Flow with 7-Bit Address (Master Receive)
514
Figure 20-7. I2C Communication Flow with 10-Bit Address (Master Receive When HEAD10R=0)
514
Figure 20-8. I2C Communication Flow with 10-Bit Address (Master Receive When HEAD10R=1)
514
Figure 20-9. Data Hold Time
515
Figure 20-10. Data Setup Time
516
Table 20-2. Data Setup Time and Data Hold Time
517
Figure 20-11. Data Transmission
518
Figure 20-12. Data Reception
518
Table 20-3. Communication Modes to be Shut down
518
Figure 20-13. I2C Initialization in Slave Mode
521
Figure 20-14. Programming Model for Slave Transmitting When SS=0
522
Figure 20-15. Programming Model for Slave Transmitting When SS=1
523
Figure 20-16. Programming Model for Slave Receiving
524
Figure 20-17. I2C Initialization in Master Mode
525
Figure 20-18. Programming Model for Master Transmitting (N<=255)
526
Figure 20-19. Programming Model for Master Transmitting (N>255)
527
Figure 20-20. Programming Model for Master Receiving (N<=255)
528
Figure 20-21. Programming Model for Master Receiving (N>255)
529
Table 20-4. Smbus with PEC Configuration
531
Figure 20-22. Smbus Master Transmitter and Slave Receiver Communication Flow
533
Figure 20-23. Smbus Master Receiver and Slave Transmitter Communication Flow
533
Table 20-5. I2C Error Flags
534
Table 20-6. I2C Interrupt Events
534
Figure 21-1. Block Diagram of SPI
551
Table 21-1. SPI Signal Description
551
Figure 21-2. SPI Timing Diagram in Normal Mode
552
Table 21-2. Quad-SPI Signal Description
552
Figure 21-3. SPI Timing Diagram in Quad-SPI Mode (CKPL=1, CKPH=1, LF=0)
553
Table 21-3. NSS Function in Slave Mode
553
Table 21-4. NSS Function in Master Mode
554
Table 21-5. SPI Operating Modes
554
Figure 21-4. a Typical Full-Duplex Connection
556
Figure 21-5. a Typical Simplex Connection (Master: Receive, Slave: Transmit)
556
Figure 21-6. a Typical Simplex Connection (Master: Transmit Only, Slave: Receive)
556
Figure 21-7. a Typical Bidirectional Connection
556
Figure 21-8. Timing Diagram of TI Master Mode with Discontinuous Transfer
558
Figure 21-9. Timing Diagram of TI Master Mode with Continuous Transfer
559
Figure 21-10. Timing Diagram of TI Slave Mode
559
Figure 21-11. Timing Diagram of NSS Pulse with Continuous Transmit
560
Figure 21-12. Timing Diagram of Quad Write Operation in Quad-SPI Mode
561
Figure 21-13. Timing Diagram of Quad Read Operation in Quad-SPI Mode
562
Figure 21-14. Block Diagram of I2S
565
Table 21-6. SPI Interrupt Requests
565
Figure 21-15. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
566
Figure 21-16. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
567
Figure 21-17. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
567
Figure 21-18. I2S Phillips Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
567
Figure 21-19. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
567
Figure 21-20. I2S Phillips Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
567
Figure 21-21. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
568
Figure 21-22. I2S Phillips Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
568
Figure 21-23. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
568
Figure 21-24. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
568
Figure 21-25. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
569
Figure 21-26. MSB Justified Standard Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
569
Figure 21-27. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
569
Figure 21-28. MSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
569
Figure 21-29. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
569
Figure 21-30. MSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
569
Figure 21-31. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
570
Figure 21-32. LSB Justified Standard Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
570
Figure 21-33. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
570
Figure 21-34. LSB Justified Standard Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
570
Figure 21-35. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
571
Figure 21-36. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
571
Figure 21-37. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
571
Figure 21-38. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
571
Figure 21-39. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
571
Figure 21-40. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
572
Figure 21-41. PCM Standard Short Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
572
Figure 21-43. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=0)
572
Figure 21-44. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=0, CKPL=1)
572
Figure 21-45. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=0)
573
Figure 21-46. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=10, CHLEN=1, CKPL=1)
573
Figure 21-47. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=0)
573
Figure 21-48. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=01, CHLEN=1, CKPL=1)
573
Figure 21-49. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=0)
573
Figure 21-50. PCM Standard Long Frame Synchronization Mode Timing Diagram (DTLEN=00, CHLEN=1, CKPL=1)
574
Figure 21-51. Block Diagram of I2S Clock Generator
574
Table 21-7. I2S Bitrate Calculation Formulas
574
Figure 21-52. I2S Initialization Sequence
575
Table 21-8. Audio Sampling Frequency Calculation Formulas
575
Table 21-9. Direction of I2S Interface Signals for each Operation Mode
575
Figure 21-53. I2S Master Reception Disabling Sequence
578
Table 21-10. I2S Interrupt
580
Figure 22-1. CMP Block Diagram
593
Table 22-1. CMP Inputs and Outputs Summary
593
Figure 22-2. CMP Hysteresis
595
Figure 22-3. the CMP Outputs Signal Blanking
596
Figure 23-1. CAN Module Block Diagram
601
Table 23-1. Mailbox Descriptor with 64 Byte Payload
602
Table 23-2. Data Bytes for DLC
604
Table 23-3. Mailbox Rx CODE
604
Table 23-4. Mailbox Tx CODE
605
Table 23-5. Mailbox Size
607
Table 23-6. Rx FIFO Descriptor
608
Table 23-7. Mailbox Arbitration Value(32 Bit) When Local Priority Disabled
617
Table 23-8. Mailbox Arbitration Value(35 Bit) When Local Priority Enabled
618
Table 23-9. Rx Mailbox Matching
624
Table 23-10. Rx FIFO Matching
625
Figure 23-2. Transmitter Delay
632
Figure 23-3. CAN Bit Time
635
Table 23-11. Interrupt Events
638
Bus off
644
Bit Recessive Error
647
Bit Dominant Error
647
Form Error
647
Stuff Error
647
Borf
647
Brerr
648
Bderr
648
Crcerr
648
Twerrif
648
Rwerrif
648
Msx
650
Can_Stat
650
Ms6_Rfw
650
Ms7_Rfo
650
Can_Ctl2
651
Table 23-12. Rx FIFO Filter Element Number
652
Can_Pn_Ctl0
661
Table 24-1. List of Abbreviations Used in Register
670
Table 24-2. List of Terms
670
Table 25-1. Revision History
672
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