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DAS-429PCI/Mx
Excalibur DAS-429PCI/Mx Manuals
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Excalibur DAS-429PCI/Mx manual available for free PDF download: User Manual
Excalibur
DAS-429PCI/Mx
User Manual
Excalibur DAS-429PCI/Mx User Manual (74 pages)
Multi-channel ARINC 429 Test and Simulation Board for PCI Systems
Brand:
Excalibur
| Category:
Computer Hardware
| Size: 0.6 MB
Table of Contents
Table of Contents
4
Introduction
9
Overview
9
DAS-429Pci/MX Block Diagram
10
Installation
11
Software Installation
11
Board Installation
11
Chapter 1
12
Memory Structure
12
DAS-429Pci/MX Memory Structure
12
PCI Configuration Space Header
13
PCI Configuration Registers
14
Vendor Identification Register (VID)
14
Device Identification Register (DID)
14
PCI Command Register
15
PCI Status Register (PCISTS)
16
Revision Identification Register (RID)
17
Class Code Register (CLCD)
17
Cache Line Size Register (CALN)
18
Latency Timer Register (LAT)
18
Header Type Register (HDR)
19
Built-In Self-Test Register (BIST)
19
Base Address Registers (BADR)
20
Expansion ROM Base Address Register (XROM)
22
Interrupt Line Register (INTLN)
22
Interrupt Pin Register (INTPIN)
23
Minimum Grant Register (MINGNT)
23
Maximum Latency Register (MAXLAT)
23
PCI Global Interrupt Registers
24
PCI Interrupt Status Register
24
PCI Interrupt Control Register
24
Module Operation
26
Chapter 2
27
Module General Operation
27
Module Memory Map
28
Figure 2-1 Module M429R4T2 Memory Map
28
Global Registers
29
Global Software Reset Register
29
Figure 2-2 Global Registers Memory Map
29
Global Interrupt Reset Register
29
Global Interrupt Reset Register
30
Global Interrupt Status Register
30
Module Control Registers
31
Figure 2-3 Module Control Registers Map
31
Start/Stop Register
32
Firmware Revision Register
33
Module Status Register
33
Channel Interrupt Register
34
Receiver Data Storage Mode Register
34
Interrupt Status Busy Register
35
Module ID Register
35
Reset Time Tag Register
35
Receiver Merge Mode Control Registers
36
Receiver Merge Start Pointer
36
Receiver Merge End Pointer
36
Receiver Merge Current Pointer
36
Receiver Merge Filter Table Start Address
36
Receiver Merge Word Count
36
Receiver Merge Buffer Wraparound Register
37
Receiver Merge Word Count Trigger Register
37
Receiver Merge Interval Count Trigger Register
37
Receiver Merge Label Trigger Register
38
Receiver Merge Configuration Register
38
Receiver Merge Interrupt Condition Register
39
Receiver Merge Status Register
39
Transmit Mode
40
Chapter 3 Transmit Channel Control Register Block Maps
41
Channel 2 Control Register Block Map
41
Channel 5 Control Register Block Map
41
Figure 3-1 Channel 2 Control Register Block Map
41
Figure 3-2 Channel 5 Control Register Block Map
41
Transmit Channel Control Registers
42
Channel X Configuration Register
42
Channel X Transmit Instruction Stack Pointer
42
Channel X Transmit Instruction Counter
43
Channel X Transmit Loop Counter
43
Channel X Transmit Current Word Register
43
Channel X Transmit Current Loop Register
43
Channel X Interrupt Condition Register
44
Channel X Status Register
44
Transmit Instruction Stack
45
Control Word Definition
46
Word Count
46
Interword Delay
46
Transmit Data Pointer
46
Transmit Data Block Format
47
Receive/ Monitor Mode
48
Chapter 4 General Information
49
Sequential Mode
49
Look-Up Table Mode
49
Merge Mode
50
Sequential/Merge Mode Operation
50
Receive Buffer Storage Sequence
50
Receive Data Word Format
51
Time Tag Word Description
52
Figure 4-4 Time Tag Word Description
52
Receive Sequential Mode Filter Table Diagram
53
Figure 4-5 Receive Sequential Mode Filter Table
53
Receive Sequential Mode Status Word
54
Receive Merge Mode Status Word
54
Look-Up Table Mode Operation
55
Receive Look-Up Table Storage Sequence
55
Receive Look-Up Table Mode Diagram
55
Receive Look-Up Table Status/Control Word
56
Receive Channel Control Register Block Maps
57
Channel 0 Control Register Block Map
57
Figure 4-7 Channel 0 Control Register Block Map
57
Channel 1 Control Register Block Map
58
Figure 4-8 Channel 1 Control Register Block Map
58
Channel 3 Control Register Block Map
59
Figure 4-9 Channel 3 Control Register Block Map
59
Channel 4 Control Register Block Map
60
Figure 4-10 Channel 4 Control Register Block Map
60
Receive Channel Control Registers
61
Channel X Configuration Register
61
Channel X Receive Data Start Pointer
62
Channel X Receive Data End Pointer
62
Channel X Receive Data Current Pointer
62
Channel X Receive Look-Up Table Start Address
62
Channel X Receive Filter Table Start Address
62
Channel X Receive Data Word Count Register
63
Channel X Receive Buffer Wraparound Register
63
Channel X Receive Data Word Counter Trigger Register
63
Channel X Receive Interval Counter Trigger Register
63
Channel X Receive Label Trigger Register
64
Channel X Interrupt Condition Register
64
Channel X Status Register
65
Mechanical and Electrical Specifications
66
Board Layout
66
Figure 5-1 DAS-429Pci/MX Board Layout
66
Chapter 5
67
LED Indicators
67
Connectors
67
Connector J1 Layout
67
Figure 5-2 Connector J1 Layout (Front View)
67
Connector J1 Pin Assignments
68
Table 5-1 Connector J1 Pin Assignments
68
Connector J1 Communication I/O Signals Description
69
Table 5-2 Connector J1 Communication I/O Signals Description
69
PCI Bus Edge Connector Pinout
70
Table 5-3 PCI Bus Edge Connector Pinout
70
Power Requirements
71
Ordering Information
72
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