Digital Electronics Corporation VT240 Series Manuals

Manuals and User Guides for Digital Electronics Corporation VT240 Series. We have 1 Digital Electronics Corporation VT240 Series manual available for free PDF download: Technical Manual

Digital Electronics Corporation VT240 Series Technical Manual

Digital Electronics Corporation VT240 Series Technical Manual (318 pages)

Brand: Digital Electronics Corporation | Category: Touch terminals | Size: 7 MB

Table of Contents
5
Introduction
17
Physical Description
21
- System Box (VS240)
  21
Appendix E Video Logic Write Mode Programmingoverview

22
- System Introduction
  21
  - Genera 1
    21
- VT240 Series Terminal Block Diagram
  22
- VT240 Series Video Terminals
  22
- Display Capabilities
  23
  - Display Characteristics
    24
  - Text Capabilities
    24
  - Graphics Capabilities L-S
    25
- Keyboard (LK201)
  23
- Monitor
  23
- Operating Modes
  26
  - VT100 Mode
    26
  - VT200 Mode, Seven-Bit Controls
    26
  - VT200 Mode, Eight-Bit Controls
    26
- S Regis Mode
  27
  - 4010/4014 Mode
    27
Chapter 2 Controls, Indicators, and Connectors

29
- General
  29
- System Box (VS240)
  29
System Box Controls, Indicators, and Connectors

29
- Monochrome Monitor (VR201)
  30
VR201 Monitor Controls, Indicators, and Connectors

31
- Color Monitor (VR241)
  32
  - VR241 Monitor Controls, Indicators, and Connectors (Front and Rear)
    32
- Keyboard (LK201) 2-S
  33
  - Main Keypad
    33
  - Editing Keypad
    33
  - Auxiliary Keypad
    33
  - Top-Row Function Keys
    33
- Visual Indicators
  33
  - Audible Indicators
    33
Main Keypad

35
- Auxiliary Keypad
  36
Editing Keypad

36
- Audible Keyclick
  39
- Connector Cable
  40
- Operating States
  41
  - Set-Up
    41
  - Local
    42
  - On-Line
    42
Input Port)

42
- System Overview
  41
- System Architecture
  43
  - VT240 Series Terminal System Block Diagram
    43
  - System Interaction in Set-Up
    46
System Interaction in Local (Printer Port Inactive)

47
System Interaction in On-Line (Printer Port as Inactive or Input Port)

49
- System Interaction in On-Line
  51
- System Interaction in On-Line (Printer Port as Inactive or Output Port)
  51
- CPU Logic
  55
- Cpu Logic
  56
- Major Circuits/Components
  56
  - Central Processor Unit
    56
  - Mode Register
    56
  - Control Gates
    56
  - Address Latch
    56
  - Memory Access Decode
    56
  - Read Only Memory (ROM)
    56
- O Buffer
  56
  - I/O Decode
    56
  - CPU Block Diagram
    57
Mode Reg I Ster

58
Random Access Memory (RAM) Block Diagram

74
RAM Devices Array

75
Transacti on

95
- Signal Descriptions
  89
Genera 1

101
Input Port

106
Output Port

107
- Communication/Modem (Comm/Modem) Control
  108
- Comm/Modem Control Definition of Integral Modem
  112
- Communication Multiplexer (Comm Mux)
  112
- Printer Interface (I/F)
  112
- Comm Mux Block Diagram
  113
- Printer Interface (I/F) Block Diagram
  113
- EIA Host Interface (I/F)
  114
- Rna Interface (I/F)
  114
- Block Diagram
  115
- Integral Modem Option Connector (J5)
  116
- Integral Modem Option Connector (J5) Pinout
  116
- Schematic Reference Information
  117
System Communication Logic Signal Descriptions

117
- Signal Descriptions
  117
System Communication Logic Schematic References

125
General

127
- VT240-Series Terminal System Block Diagram
  127
- Video Logic
  127
- Major Circuits/Components
  128
  - Character Processor (CP)
    128
    
    Video Logic Block Diagram
    129
  - Graphics Processor
    133
    
    Character Processor (CP) Memory Block Diagram
    134
    
    Video Access Block Diagram
    136
    
    Graphics Processor Block Diagram
    139
    
    PD7220 GDC Block Diagram
    139
    
    PD7220 Graphics Display Controller (GDC) Addresses
    140
  - Timing and Control Circuits
    148
    
    Clock Generator
    148
    
    BEN and STOP Gates
    148
    
    ROM Address Counter
    148
    
    Timing Signal Generator
    148
    
    Read-Modify-Write (RMW) Generator
    148
    
    BLANK Generator
    148
  - Bit Map Addressing Circuit
    155
    
    Bit Map Addressing Circuit Block Diagram
    155
    
    Plane and Byte Select Block Diagram
    156
    
    Address Select
    157
    
    Plane and Byte Select
    157
  - High/Low (Hi/Lo) Byte Select
    158
  - Address Select Block Diagram
    158
  - Row/Column Mux Block Diagram
    159
  - Hi/La Byte Select Block Diagram
    159
  - Bit Map Write Enable
    160
  - Bit Map Write Enable Block Diagram
    160
  - Pattern Select Block Diagram
    162
- 8085A-2 Microprocessor Device Internal Block Diagram
  
  131
  - 8085A-2 Microprocessor Device
    133
  - Circuits
    133
PD7220 GDC Commands Summary

142
PD7220 GDC Timing Diagram: CPU/CP Read Transaction

145
- PD7220 GDC Timing Diagram: Display Timing
  145
- PD7220 GDC Timing Diagram: Video Sync Signals
  146
PD7220 GDC Timing Diagram: Video DMA Write Transaction

148
- Timing and Control Block Diagram Circuits
  149
- Clock Generator Block Diagram
  149
- BEN and STOP Gates Block Diagram
  151
- ROM Address Counter Block Diagram
  151
- Timing Signal Generator Block Diagram
  151
- Read-Modify-Write (RMW) Generator Block Diagram
  152
- BLANK Generator Block Diagram
  153
- Mode Select Block Diagram
  154
- Pattern Select
  
  163
  - Logic Unit Block Diagram
    164
  - Write Data Select Block Diagram
    165
  - Bit Map Block Diagram
    166
  - Output Map Block Diagram
    170
  - Video Output Map (VOM) Addressing
    171
  - Digital-To-Analog (D/A) Block Diagram
    172
  - Video Logic Signal Description
    174
- Logic Unit
  
  178
  - Write Data Select
    178
    
    Bit Map
    183
    
    Video Logic Schematic References
    188
Genera 1

191
LK201 Keyboard

191
- Physical Description
  192
  - Keyboard Cable Connections
    193
- Functional Description
  194
  - Keyboard Operation Overview
    194
    
    LK201 Keyboard Block Diagram
    194
    
    Control of Audio Transducer and Indicators
    195
  - Keyboard Firmware Functions
    195
    
    Instructions
    195
    
    Functions Changed by CPU Instructions
    196
    
    Firmware Functions Changed by CPU Instructions
    196
- Detailed Keyboard Circuit Description
  196
  - Keyboard Matrix Scanning
    196
  - Matrix Scanning Block Diagram
    197
Keyboard Matrix

199
- LK201-AA Keyboard Layout
  202
- Audio Transducer Control Circuit
  204
- Indicator (LED) Control Circuit
  204
- Beeper Control Circuit
  205
- Indicator (LED) Control Circuit
  205
- Keyboard Communication
  206
  - Keyboard Transmit Mode
    206
  - Keyboard Receive Mode
    206
  - Keyboard Transmit and Receive Character
    206
- Hardware Keyboard Identification (ID)
  207
- Keyboard Programming
  207
Test Mode

211
- Reset Signal for 81351 Microprocessor
  207
- Modes
  
  213
  - Autorepeat
    213
  - Special Considerations Regarding Down/Up Mode
    215
  - Autorepeat Rates
    215
  - Keyboard Peripherals
    216
    
    Aud I
    216
    
    Indicators (Leds)
    216
  - Keyboard-To-System Module Protocol
    217
    
    Special Code Transmission
    217
  - System Module to Keyboard Protocol
    219
    
    Commands
    220
    
    Parameters
    220
    
    Peripheral Commands
    220
    
    Mode Set Commands
    220
System Module to Keyboard Protocol

220
- Peripheral Commands in Hexidecimal
  223
- Audio Volume Parameter
  224
- Indicator (LED) Layout
  224
- Indicator (LED) Parameter
  224
- Set Main Array to Autorepeat Example
  227
- Set Main Array to Down/Up Example
  227
- Special Considerations
  228
  - Error Handling
    228
  - Keyboard Locked Condition
    229
  - Future Expansion
    229
  - Keyboard Division Default Modes
    229
- Default Conditions
  230
  - Audio Volume
    230
  - Default Rates in Autorepeat Buffers
    230
  - VT240-Series Terminal System Block Diagram
    233
  - Monochrome Monitor Exterior View
    235
  - Monochrome Monitor Block Diagram
    236
  - Monochrome Monitor System Communications Diagram
    238
  - J1 Pin-Out
    238
  - Composite Video Signal Representation
    239
  - J3 Pin-Out
    239
  - Composite Video Values
    240
  - Composite Video Sync Timing Diagram
    241
  - Composite Video Sync Component
    242
  - Monitor Module Block Diagram
    244
  - VT240-Series Terminal System Block Diagram
    249
  - Power Supply Block Diagram
    250
  - +5 V Input Circuit
    250
  - AC Input and Fan Components Block Diagram
    251
  - Physical Location of Power Supply Components
    252
  - Power Supply 1 (PS1) Block Diagram
    253
Input Regulation Circuitry

254
- +5.1 V Crowbar Circuit
  255
- DC Output Circuits
  255
- Psl Component Layout
  256
- Power Supply 1 (PSI) Components
  257
- Input Voltage Specifications
  259
- Output Voltage Specifications
  260
- +5 V Input Circuit
  262
- Logic Board DC Power Input Connector
  262
- Input Circuit
  263
- DC Power OK Circuit
  264
- VT240-Series Terminal Block Diagram
  265
- Physical Description
  267
- Audio Coupler
  268
- Modem Control LS I
  268
- Stack Connector
  268
Talk/Data Relay

268
Modem Clock

274
- Carrier Detect (CD)
  275
- Interface Signals
  276
- Signal States
  276
- Interface Signal Levels
  277
- Specifications
  281
Appendix A Specifications

285
- Vt240/Vt102 Differences
  285
Appendix B Vt240/Vt102 Differences

287
- Vt240/Vt125 Differences
  287
Appendix C Vt240/Vt125 Differences

291
Originate Mode

304
Answer Mode

304
- Comm/Modem Control: Modem Control Write Register
  304
(Mcwr

304
- Comm/Modem Control: Modem Control Read Register
  304
(Mcrd

304
- Video Logic Mode Select Register
  305
- Video Logic Unit Register
  306
Appendix D Register Bit Values

307

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Digital Electronics Corporation VT240 Series Manuals

Digital Electronics Corporation VT240 Series Technical Manual (318 pages)

Table of Contents

Appendix E Video Logic Write Mode Programmingoverview

Chapter 2 Controls, Indicators, and Connectors

System Box Controls, Indicators, and Connectors

VR201 Monitor Controls, Indicators, and Connectors

Main Keypad

Editing Keypad

Input Port)

System Interaction in Local (Printer Port Inactive)

System Interaction in On-Line (Printer Port as Inactive or Input Port)

Mode Reg I Ster

Random Access Memory (RAM) Block Diagram

RAM Devices Array

Transacti on

Genera 1

Input Port

Output Port

System Communication Logic Signal Descriptions

System Communication Logic Schematic References

General

8085A-2 Microprocessor Device Internal Block Diagram

PD7220 GDC Commands Summary

PD7220 GDC Timing Diagram: CPU/CP Read Transaction

PD7220 GDC Timing Diagram: Video DMA Write Transaction

Pattern Select

Logic Unit

Genera 1

LK201 Keyboard

Keyboard Matrix

Test Mode

Modes

System Module to Keyboard Protocol

Input Regulation Circuitry

Talk/Data Relay

Modem Clock

Appendix A Specifications

Appendix B Vt240/Vt102 Differences

Appendix C Vt240/Vt125 Differences

Originate Mode

Answer Mode

(Mcwr

(Mcrd

Appendix D Register Bit Values

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