Allwinner Technology A20 ARM Cortex-A7 Manuals

Manuals and User Guides for Allwinner Technology A20 ARM Cortex-A7. We have 1 Allwinner Technology A20 ARM Cortex-A7 manual available for free PDF download: User Manual

Allwinner Technology A20 User Manual (806 pages)

Dual-core ARM Cortex-A7 mobile application solution designed for tablet dual-core ARM Cortex-A7 mobile application solution designed for tablet

Brand: Allwinner Technology | Category: Computer Hardware | Size: 8 MB

Declaration
2
Revision History
3
Table of Contents
4
Chapter 1 System

9
- Overview
  10
  - System Resources
    12
  - Video Output
    13
  - Video Input
    13
  - Analog Audio Output
    13
  - Power Management
    16
- A20 Block Diagram
  17
- Memory Mapping
  18
- CPU Configuration
  22
  - Overview
    22
  - CPU Configuration Register List
    23
  - CPUCFG Register Description
    24
- Ccu
  33
  - Overview
    33
  - Clock Tree Diagram
    34
  - CCU Register List
    34
  - CCU Register Description
    37
- System Boot
  94
  - Overview
    94
  - System Boot Diagram
    95
- System Control
  96
  - Overview
    96
  - System Control Register List
    97
  - System Control Register
    97
- Pwm
  101
  - Overview
    101
  - PWM Register List
    102
  - PWM Register Description
    102
- Timer
  107
  - Overview
    107
  - Timer Register List
    108
  - Timer Register Description
    109
- High Speed Timer
  133
  - Overview
    133
  - High Speed Timer Register List
    134
  - High Speed Timer Controller Register
    135
- Gic
  146
  - Interrupt Source
    146
- Dma
  151
  - Overview
    151
  - DMA Register List
    152
  - DMA Controller Register Description
    153
- Audio Codec
  170
  - Overview
    170
  - Audio Codec Block Diagram
    171
  - Audio Codec Register List
    171
  - Audio Codec Register Description
    172
- Lradc
  189
  - Overview
    189
  - LRADC Block Diagram
    190
  - LRADC Register List
    190
  - LRADC Register Description
    191
  - Overview
    198
  - Typical Application Circuit
    199
  - TP Clock Tree
    199
  - A/D Conversion Time
    199
  - Principle of Operation
    201
  - TP Register List
    206
  - TP Register Description
    207
- Security System
  217
  - Overview
    217
  - Security System Block Diagram
    218
  - Security System Register List
    218
  - Security System Register Description
    219
- Security JTAG
  227
  - Overview
    227
  - Security JTAG Register List
    228
  - Security JTAG Register Description
    228
- Security ID
  230
  - Overview
    230
  - SID Block Diagram
    231
  - Security System Register List
    231
  - Security ID Register Description
    232
- Port Controller
  238
  - Port Description
    238
  - Port Configuration Table
    239
  - Port Register List
    245
  - Port Register Description
    246
Chapter 2 Memory

305
- Dram
  306
  - Overview
    306
- NAND Flash
  307
  - Overview
    307
  - Nand Flash Block Diagram
    308
  - NFC Timing Diagram
    309
  - NFC Operation Guide
    314
Chapter 3 Graphic

317
- Mixer Processor
  318
  - Overview
    318
  - Mixer Processor Block Diagram
    319
  - MP Register List
    319
  - MP Register Description
    321
Chapter 4 Image

361
- Csi0
  362
  - Overview
    362
  - CSI0 Block Diagram
    363
  - CSI0 Description
    363
  - CSI0 Register List
    366
  - CSI0 Register Description
    368
- Csi1
  396
  - Overview
    396
  - CSI1 Block Diagram
    397
  - CSI1 Description
    397
  - CSI1 Timing Diagram
    397
  - CSI1 Register List
    398
  - CSI1 Register Description
    399
- TV Decoder
  411
  - Overview
    411
Chapter 5 Display

412
- Tcon
  414
  - Overview
    414
  - TCON Block Diagram
    415
  - TCON Register List
    416
  - TCON Register Description
    418
- Hdmi
  444
  - Overview
    444
  - HDMI Block Diagram
    445
  - HDMI Control Register Description
    445
  - HDMI Register Description
    447
- Display Engine Frontend
  485
  - Overview
    485
  - DEFE Block Diagram
    486
  - DEFE Register List
    486
  - DEFE Register Description
    490
- Display Engine Backend
  536
  - Overview
    536
  - Display Engine Block Diagram
    537
  - DEBE Register List
    537
  - DEBE Register Description
    540
  - Palette Mode
    577
- TV Encoder
  582
  - Overview
    582
Chapter 6 Interface

583
- Sd3.0
  584
  - Overview
    584
  - SD3.0 Timing Diagram
    584
- Twi
  585
  - Overview
    585
  - TWI Controller Timing Diagram
    586
  - TWI Controller Register List
    586
  - TWI Register Description
    587
  - TWI Controller Special Requirement
    595
- Spi
  597
  - Overview
    597
  - SPI Timing Diagram
    598
  - SPI Register List
    599
  - SPI Register Description
    600
  - SPI Special Requirement
    614
- Uart
  615
  - Overview
    615
  - UART Timing Diagram
    616
  - UART Register List
    616
  - UART Register Description
    617
  - UART Special Requirement
    635
- Ps2
  638
  - Overview
    638
  - PS2 Block Diagram
    639
  - PS2 Timing Diagram
    639
  - PS2 Register List
    641
  - PS2 Register Description
    641
  - PS2 Special Requirements
    649
  - Overview
    650
  - IR Block Diagram
    651
  - IR Register List
    651
  - IR Register Description
    652
- Usb Otg
  665
  - Overview
    665
  - USB OTG Timing Diagram
    665
- USB Host
  666
  - Overview
    666
  - USB Host Block Diagram
    667
  - USB Host Timing Diagram
    667
  - USB Host Register List
    667
  - EHCI Register Description
    668
  - OHCI Register List
    687
  - OHCI Register Description
    688
  - USB Host Special Requirement
    705
- Digital Audio Interface
  706
- AC97 Interface
  729
  - Overview
    729
  - AC97 Block Diagram
    730
  - AC97 Interface Clock Tree
    731
  - AC Link Frame Format
    731
  - AC97 Interface Timing Diagram
    732
  - AC97 Interface Register List
    736
  - AC97 Interface Register Description
    737
  - AC97 Interface Special Requirement
    747
- Emac
  748
  - Overview
    748
  - EMAC Block Diagram
    749
  - EMAC Operation Diagram
    750
- Gmac
  753
  - Overview
    753
  - GMAC Block Diagram
    754
- Transport Stream
  755
  - Overview
    755
  - Transport Stream Block Diagram
    756
  - Transport Stream Controller Register List
    756
  - Transport Stream Register Description
    758
  - Transport Stream Clock Requirement
    777
- Smart Card Reader
  778
  - Overview
    778
  - Smart Card Reader Block Diagram
    779
  - Smart Card Reader Timing Diagram
    779
  - Smart Card Reader Register List
    779
  - Smart Card Reader Register Description
    780
  - SCIO Pad Configuration
    792
- SATA Host
  793
  - Overview
    793
  - SATA_AHCI Timing Diagram
    793
- Can
  794
  - Overview
    794
  - CAN System Block Diagram
    795
  - CAN Bit Time Configuration
    795
- Keypad
  796
  - Overview
    796
  - Keypad Interface Register List
    797
  - Keypad Interface Register Description
    797
  - Keypad Interface Special Requirement
    800
Appendix A

801

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Computer Hardware

More Allwinner Technology Manuals

Allwinner Technology A20 ARM Cortex-A7 Manuals

Allwinner Technology A20 User Manual (806 pages)

Table of Contents

Chapter 1 System

Chapter 2 Memory

Chapter 3 Graphic

Chapter 4 Image

Chapter 5 Display

Chapter 6 Interface

Appendix A

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