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PXIe-9852
ADLINK Technology PXIe-9852 Manuals
Manuals and User Guides for ADLINK Technology PXIe-9852. We have
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ADLINK Technology PXIe-9852 manual available for free PDF download: User Manual
ADLINK Technology PXIe-9852 User Manual (46 pages)
2-CH 14-Bit 200 MS/s Digitizer
Brand:
ADLINK Technology
| Category:
Measuring Instruments
| Size: 1 MB
Table of Contents
Table of Contents
5
List of Figures
7
List of Tables
9
1 Introduction
11
Features
11
Applications
12
Specifications
12
Analog Input
12
Figure 1-1: Analog Input Channel Bandwidth, ±0.2 Vpp
13
Timebase
14
Figure 1-2: Analog Input Channel Bandwidth, ±2 Vpp
14
Table 1-1: Timebase
14
Triggers
15
Table 1-2: Trigger Source & Mode
15
Table 1-3: Digital Trigger Input
15
General Specifications
16
Table 1-4: Digital Trigger Output
16
Software Support
17
Sdk
17
Wd-Dask
17
Device Layout and I/O Array
18
Figure 1-3: Pxie-9852 Schematic
18
Figure 1-4: Pxie-9852 I/O Array
19
Table 1-5: Pxie-9852 I/O Array Legend
20
2 Getting Started
21
Installation Environment
21
Installing the Module
22
3 Operations
25
Functional Block Diagram
25
Analog Input Channel
25
Analog Input Front-End Configuration
25
Figure 3-1: Analog Input Architecture of the Pxie-9852
25
Input Range and Data Format
26
DMA Data Transfer
26
Table 3-1: Input Range and Data Format
26
Table 3-2: Input Range FSR and -FSR Values
26
Table 3-3: Input Range Midscale Values
26
Trigger Source and Trigger Modes
28
Figure 3-2: Linked List of PCI Address DMA Descriptors
28
Figure 3-3: Trigger Architecture of the Pxie-9852
28
External Digital Trigger
29
Figure 3-4: External Digital Trigger
29
PXI STAR Trigger
29
Software Trigger
29
Analog Trigger
30
PXI Trigger Bus
30
Pxie_Dstarb Trigger
30
Trigger Export
31
Trigger Modes
31
Post Trigger Mode
31
Delayed Trigger Mode
31
Figure 3-5: Post-Trigger Acquisition
31
Pre-Trigger Mode
32
Figure 3-6: Delayed Trigger Mode Acquisition
32
Figure 3-7: Pre-Trigger Mode Acquisition
32
Middle Trigger Mode
33
Acquisition with Re-Triggering
33
Figure 3-8: Middle Trigger Mode Acquisition
33
Data Average Mode (Post-Trigger and Delayed-Trigger Only)
34
Figure 3-9: Re-Trigger Mode Acquisition
34
Timebase
35
Internal Reference Clock
35
External Reference Clock
35
External Sampling Clock
35
Figure 3-10: Pxie-9852 Clock Architecture
35
PXI_CLK10 Clock
36
PXI_CLK100 Clock
36
ADC Timing Control
36
Timebase Architecture
36
Basic Acquisition Timing
36
Figure 3-11: Pxie-9852 Timebase Architecture
36
Figure 3-12: Basic Digitizer Acquisition Timing
37
Figure 3-13: Varying Sampling Rates by Adjusting Scan Interval
38
Synchronizing Multiple Modules
39
Table 3-4: Counter Parameters and Description
39
A Appendix: Calibration
41
Calibration Constant
41
Auto-Calibration
41
A.1 Calibration Constant
41
Important Safety Instructions
43
Getting Service
45
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