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Maxim MAX12557 Specifications

Dual, 65msps, 14-bit, if/baseband adc
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19-3544; Rev 0; 2/05
Dual, 65Msps, 14-Bit, IF/Baseband ADC
General Description
The MAX12557 is a dual 3.3V, 14-bit analog-to-digital
converter (ADC) featuring fully differential wideband
track-and-hold (T/H) inputs, driving internal quantizers.
The MAX12557 is optimized for low power, small size,
and high dynamic performance in intermediate frequen-
cy (IF) and baseband sampling applications. This dual
ADC operates from a single 3.3V supply, consuming
only 610mW while delivering a typical 72.5dB signal-to-
noise ratio (SNR) performance at a 175MHz input fre-
quency. The T/H input stages accept single-ended or
differential inputs up to 400MHz. In addition to low oper-
ating power, the MAX12557 features a 166µW power-
down mode to conserve power during idle periods.
A flexible reference structure allows the MAX12557 to
use the internal 2.048V bandgap reference or accept
an externally applied reference and allows the refer-
ence to be shared between the two ADCs. The refer-
ence structure allows the full-scale analog input range
to be adjusted from ±0.35V to ±1.15V. The MAX12557
provides a common-mode reference to simplify design
and reduce external component count in differential
analog input circuits.
The MAX12557 supports either a single-ended or differ-
ential input clock. User-selectable divide-by-two (DIV2)
and divide-by-four (DIV4) modes allow for design flexibil-
ity and help eliminate the negative effects of clock jitter.
Wide variations in the clock duty cycle are compensated
with the ADC's internal duty-cycle equalizer (DCE).
The MAX12557 features two parallel, 14-bit-wide,
CMOS-compatible outputs. The digital output format is
pin-selectable to be either two's complement or Gray
code. A separate power-supply input for the digital out-
puts accepts a 1.7V to 3.6V voltage for flexible interfac-
ing with various logic levels. The MAX12557 is available
in a 10mm x 10mm x 0.8mm, 68-pin thin QFN package
with exposed paddle (EP), and is specified for the
extended (-40°C to +85°C) temperature range.
For a 12-bit, pin-compatible version of this ADC, refer to
the MAX12527 data sheet.
IF and Baseband Communication Receivers
Cellular, LMDS, Point-to-Point Microwave,
MMDS, HFC, WLAN
I/Q Receivers
Ultrasound and Medical Imaging
Portable Instrumentation
Digital Set-Top Boxes
Low-Power Data Acquisition
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Applications
♦ Direct IF Sampling Up to 400MHz
♦ Excellent Dynamic Performance
74.1dB/72.5dB SNR at f
83.4dBc/79.5dBc SFDR at f
♦ 3.3V Low-Power Operation
637mW (Differential Clock Mode)
610mW (Single-Ended Clock Mode)
♦ Fully Differential or Single-Ended Analog Input
♦ Adjustable Differential Analog Input Voltage
♦ 750MHz Input Bandwidth
♦ Adjustable, Internal or External, Shared Reference
♦ Differential or Single-Ended Clock
♦ Accepts 25% to 75% Clock Duty Cycle
♦ User-Selectable DIV2 and DIV4 Clock Modes
♦ Power-Down Mode
♦ CMOS Outputs in Two's Complement or Gray
Code
♦ Out-of-Range and Data-Valid Indicators
♦ Small, 68-Pin Thin QFN Package
♦ 12-Bit Compatible Version Available (MAX12527)
♦ Evaluation Kit Available (Order MAX12557 EV Kit)
Ordering Information
PART
TEMP RANGE
MAX12557ETK
-40°C to +85°C
*EP = Exposed paddle.
SAMPLING RATE
PART
(Msps)
MAX12557
MAX12527
Pin Configuration appears at end of data sheet.
Features
= 70MHz/175MHz
IN
= 70MHz/175MHz
IN
PIN-PACKAGE
68 Thin QFN-EP*
(10mm x 10mm x 0.8mm)
Selector Guide
RESOLUTION
(Bits)
65
14
65
12
1

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  • Page 1 Portable Instrumentation Digital Set-Top Boxes Low-Power Data Acquisition ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. ♦ Direct IF Sampling Up to 400MHz ♦ Excellent Dynamic Performance 74.1dB/72.5dB SNR at f...

  • Page 2: Absolute Maximum Ratings

    Dual, 65Msps, 14-Bit, IF/Baseband ADC ABSOLUTE MAXIMUM RATINGS to GND ...-0.3V to +3.6V to GND...-0.3V to the lower of (V INAP, INAN to GND ...-0.3V to the lower of (V INBP, INBN to GND ...-0.3V to the lower of (V CLKP, CLKN to GND ...-0.3V to the lower of (V REFIN, REFOUT...
  • Page 3 Dual, 65Msps, 14-Bit, IF/Baseband ADC ELECTRICAL CHARACTERISTICS (continued) = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f +85°C, unless otherwise noted.
  • Page 4 Dual, 65Msps, 14-Bit, IF/Baseband ADC ELECTRICAL CHARACTERISTICS (continued) = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f +85°C, unless otherwise noted.
  • Page 5 Dual, 65Msps, 14-Bit, IF/Baseband ADC ELECTRICAL CHARACTERISTICS (continued) = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f +85°C, unless otherwise noted.
  • Page 6 Dual, 65Msps, 14-Bit, IF/Baseband ADC ELECTRICAL CHARACTERISTICS (continued) = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f +85°C, unless otherwise noted.

  • Page 7: Typical Operating Characteristics

    Dual, 65Msps, 14-Bit, IF/Baseband ADC ELECTRICAL CHARACTERISTICS (continued) = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference), C tial), DIFFCLK/SECLK = OV , PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, f +85°C, unless otherwise noted.
  • Page 8 Dual, 65Msps, 14-Bit, IF/Baseband ADC = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), C DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f FFT PLOT (32,768-POINT DATA RECORD) = 65.00352MHz = 174.98857MHz = -0.476dBFS SNR = 72.37dB SINAD = 70.48dB...
  • Page 9 Dual, 65Msps, 14-Bit, IF/Baseband ADC = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), C DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f SNR, SINAD vs. ANALOG INPUT AMPLITUDE = 65.00352MHz, f = 175MHz) SINAD -45 -40 -35...
  • Page 10 Dual, 65Msps, 14-Bit, IF/Baseband ADC = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), C DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f -THD, SFDR vs. ANALOG SUPPLY VOLTAGE = 65.00352MHz, f = 175MHz) SFDR -THD...
  • Page 11 Dual, 65Msps, 14-Bit, IF/Baseband ADC = 3.3V, OV = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), C DIFFCLK/SECLK = OV , PD = GND, G/T = GND, f SNR, SINAD vs. TEMPERATURE = 175MHz, A SINAD TEMPERATURE (°C) GAIN ERROR vs.

  • Page 12: Pin Description

    Dual, 65Msps, 14-Bit, IF/Baseband ADC NAME 1, 4, 5, 9, Converter Ground. Connect all ground pins and the exposed paddle (EP) together. 13, 14, 17 INAP Channel A Positive Analog Input INAN Channel A Negative Analog Input COMA Channel A Common-Mode Voltage I/O. Bypass COMA to GND with a 0.1µF capacitor. Channel A Positive Reference I/O.
  • Page 13 Data-Valid Digital Output. The rising edge of DAV indicates that data is present on the digital outputs. The MAX12557 evaluation kit utilizes DAV to latch data into any external back-end digital logic. Channel A CMOS Digital Output, Bit 0 (LSB)

  • Page 14: Detailed Description

    IN_P IN_N Figure 1. Pipeline Architecture—Stage Blocks Detailed Description The MAX12557 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for high- speed conversion while minimizing power consump- tion. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle.
  • Page 15 DIFFCLK/SECLK CLKP CLKN DIV2 DIV4 Figure 2. Functional Diagram ______________________________________________________________________________________ CLOCK 14-BIT DIGITAL DATA PIPELINE ERROR FORMAT CORRECTION CHANNEL A REFERENCE MAX12557 SYSTEM INTERNAL REFERENCE GENERATOR CHANNEL B REFERENCE SYSTEM 14-BIT DIGITAL DATA PIPELINE ERROR FORMAT CORRECTION CLOCK CLOCK CLOCK...

  • Page 16: Reference Mode

    REFOUT has approxi- (T/H) Amplifier mately 17kΩ to GND when the MAX12557 is powered down. The reference circuit requires 10ms to power up and settle to its final value when power is applied to the MAX12557 or when PD transitions from high to low.
  • Page 17 V REFAN Connect SHREF to GND to disable the shared refer- ence mode of the MAX12557. In this independent refer- ence mode, a better channel-to-channel isolation is achieved. For detailed circuit suggestions and how to drive the ADC in buffered/unbuffered external reference mode, see the Applications Information section.
  • Page 18 AND S ARE OPEN compensated to correct for any input clock duty-cycle variations. The MAX12557 output data changes on the falling edge of DAV, and DAV rises once the output ARE OPEN IN data is valid. The falling edge of DAV is synchronized to have a 5.4ns delay from the falling edge of the input...
  • Page 19 DOR function as is with the output data (Figure 5). DOR_ is high impedance when the MAX12557 is in power-down (PD = high). DOR_ enters a high-impedance state within 10ns after the rising edge of PD and becomes active 10ns after PD’s falling edge.
  • Page 20 Figure 6. Two’s-Complement Transfer Function (G/ The digital outputs D0A/B–D13A/B are high impedance when the MAX12557 is in power-down (PD = 1) mode. D0A/B–D13A/B enter this state 10ns after the rising edge of PD and become active again 10ns after PD transitions low.
  • Page 21 4) THE FINAL GRAY-CODE CONVERSION IS: FIGURE 8 SHOWS THE GRAY-TO-BINARY AND BINARY-TO-GRAY CODE CONVERSION IN OFFSET BINARY FORMAT. THE OUTPUT FORMAT OF THE MAX12557 IS TWO'S-COMPLEMENT BINARY, HENCE EACH MSB OF THE TWO'S-COMPLEMENT OUTPUT CODE MUST BE INSERTED TO REFLECT TRUE OFFSET BINARY FORMAT.

  • Page 22: Applications Information

    An RF transformer (Figure 9) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the MAX12557 for optimum performance. Connecting the center tap of the transformer to COM provides a V shift to the input.
  • Page 23 The MAX4250 buffers the 2.048V reference and pro- Multiple ADCs vides additional 10Hz LP filtering before its output is applied to the REFIN input of the MAX12557. Unbuffered External Reference Drives The unbuffered external reference mode allows for pre- cise control over the MAX12557 reference and allows multiple converters to use a common reference.

  • Page 24: Board Layout

    The MAX12557 requires high-speed board layout design techniques. Refer to the MAX12557 EV kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, prefer- ably on the same side as the ADC, using surface- 0.1µF...

  • Page 25: Parameter Definitions

    90° turns. Ensure that the differential, analog input network layout is symmetric and that all parasitic components are bal- anced equally. Refer to the MAX12557 EV kit data sheet for an example of symmetric input layout. Parameter Definitions...
  • Page 26 . The full-scale limits by ±10%. The MAX12557 requires one clock cycle to recover from the overdrive condition. , 2 x Coupling onto one channel being driven by a Aperture Jitter (-0.5dBFS) signal when the adjacent interfering channel...

  • Page 27: Pin Configuration

    (typically in %FSR) as offset matching. ______________________________________________________________________________________ Gain Matching TOP VIEW Offset Matching INAP INAN COMA REFAP REFAN REFBN REFBP COMB INBN INBP Pin Configuration MAX12557 EXPOSED PADDLE (GND) THIN QFN DORB D13B D12B D11B D10B...

  • Page 28: Package Information

    Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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