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Introduction KMC’s KZM-ARM11-01 is a new evaluation board that has a 532 MHz ARM1136 core (i.MX31 from freescale™ semiconductor) embedded and comes with Linux 2.6. With the supplied Linux 2.6 source/binary codes and ARM11 tool chain this evaluation board can be used immediately after purchase for many purposes ranging from development of ARM11-based Linux applications to debugging of user product boards.
1 Features High-speed RISC i.MX31: incorporates Freescale™ Semiconductor MCIMX31VKN5 (ARM1136JF-S core chip) . ・ The core of i.MX31 is ARM1136JF-S (532 MHz) . Built-in L2 cache in addition to L1 cache. Vector Floating Point Unit (VFP) installed. ・ Built-in large-capacity Mobile-DDR RAM: Equivalent to HYB18M512160×2 (128 Mbytes) Provided with JTAG port for connecting JTAG cable.
5 Memory Map The following tables show memory maps of this board. The addresses shown are physical addresses. For details of the Internal Register Space refer to the CPU Manual. Start Address End Address Size Name 0x0000 0000 0x0000 3FFF Kbytes Secure ROM 0x0000 4000...
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For the memory size of the emulation memory (EMJ) refer to the Emulation Memory (EMJ) Manual. The following memory map assumes that EMJ-64M (64 Mbytes) is connected. For a smaller-capacity memory, additional spaces for aliasing will be secured in CS0. With EMJ being connected Start Address End Address...
6 Various Settings This section describes the jumper plug settings, etc. on this board. If you attempt to modify any of these settings, refer to the Circuit Diagram in the Appendix of this document for an understanding of the jumper plug concerned. External power supply DC-JACK Mode selector rotary switch RSW1...
6.2 Mode Selector:RSW1 This is used to switch over the modules for use depending on the selector position. It enables switching between ATA and CAMERA. Also for UART1, the output destination can be changed. A total of five selection modes are provided and the current switch setting can be seen from the control register.
6.3 SJC_MOD Setting:JP11 This is the setting for enabling the JTAG debugger unit. The factory default is short-circuited, and under regular operations does not need to be changed. The JTAG connector is for connecting with the PARTNER-series JTAG cable. It may be either the ETM type (CN13) or 20-pin type (CN16) shown below.
6.5 BOOT MODE Setting:DSW1,JP11 Used to set the BOOT MODE. As the factory settings, 1,2,4=ON on DSW1 and JP17 are open-circuited. Do not change these switch settings. Fig 9 BOOT MODE SW, JP i.MX31 i.MX31 value SIGNAL DSW 1-1 BT_MD0 0 (default) DSW 1-2 BT_MD1...
6.6 JTAG /SRST and i.MX31 Reset Signal Settings: SW2,3,JP12 Used to define the destination when connecting the JTAG debugger connector, /SRST. The factory default is for connecting to the i.MX31’s POR_B. It is configured as follows: JP12 Fig.10 CN13, 16 JTAG Connector BUFFER FPGA POR_B...
6.10 Interrupt The interrupt function of this product is implemented in such a way that the ARM1136JF-S Vectored Interrupt Controller (AVIC), which is one of the devices of i.MX31, is connected to the interrupt input port. This AVIC can accommodate a maximum of 64 interrupt sources.
6.11.1 NOR FLASH MEMORY The NOR FLASH MEMORY used in this product is linked to the CS0 address space (see the memory map) of the Wireless External Interface Module (WEIM). The setting values related to this WEIM are shown below. With these settings the type of memory, bus size, and control signal timing are defined.
6.11.2 Mobile DDR MEMORY The Mobile DDR MEMORY used for this product is linked to the CSD0 address space of the Enhanced SDRAM Controller (ESDCTL). This product is designed to operate under HCLK of 106 MHz. The DDR memory serves as the SSTL interface whilst the ESDCTL and Mobile DDR MEMORY are 1.8V LVCMOS.
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6-5 DS:1 Half Drive Strength Normal ESDCTL0 address:0xB800_1000,82226080 30–28 SMODE:0 Normal Read/Write ESDMISC address:0xB800_1010,80000004 2MDDREN:1 Enable Mobile DDR SDRAM operation Various Settings ---- 19...
7 Description of Functions 7.1 External Expansion Connector:CN7 (not preinstalled) 1.27mm-pitch Surface Installation Pad Through this connector, signals to/from the local memory bus (WEIM) of i.MX31 are transmitted via a 3V buffer. All these signals are rated to 3V. Fig.14 CN3 External Expansion Connector 7.2 PCMCIA Model No.:IC14A-PL-SF-EJR, manufacturer:HIROSE ・Host adapter interface with full compatibility with PCMCIA standard release 2.1 (PC Card-16).
7.3 UART1 UART1 is connected to D-SUB connector (CN6) via RS-232C driver and JP. Communication between i.MX31 and RS-232C driver is defined as DCE (MODEM). Switchover between straight and cross connections can be achieved through JP setting. This is used for console output of Linux.
7.6 USBOTG Model No.:E43AS-005-8604A, manufacturer: MITSUMI This is a connector for USBOTG. For this type a mini-AB socket has been installed. Either a mini-A plug or mini-B plug can be used. USB2.0 On-The-Go permits automatic switchover between host and slave. Using this connector as mini-A allows any USB client to be connected.
7.9 KEYPAD Model No.: SKRPABE010, manufacturer: Alps Electric Corp. This is connected to the KEYPAD controller, one of the peripheral features of i.MX31. Fig.20 KEYPAD 7.10 AC97 Model No.: HSJ1601-011110, manufacturer: HOSHIDEN Audio signals conform to the Synchronous Serial Interface (SSI) specifications and are connected to AD1981BL, which is a CODEC device.
7.11 ATA Model No.: A3-44DA-2DSA, manufacturer: HIROSE ・Conforms to ATA-6 specifications. ・PIO modes 0, 1, 2, 3, and 4 are supported. ・Multiword DMA modes 0, 1, and 2 are supported. ・Ultra DMA modes 0, 1, 2, 3, and 4 are supported under a bus clock of 50 MHz. ・Ultra DMA mode 5 is supported under a bus clock of 80 MHz.
8 BOARD Controller NAND (IC7), 7-seg LED (LED7), LED (LED 3-6), DIP switch (DSW2) are controlled by EP1C (IC14). 8.1 BOARD CONTROL 8.1.1 Controls control1 Address : 0xB400 1000 Access : 8bit Read/Write Bit No. Description Reserved UART_MBAUD:Controlling the baud rate (MBAUD) of a driver connected to UART1 1:high 0:low UART1_SD:Controlling the shutdown process of a driver connected to UART1...
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RSW1 Address : 0xB400 1002 Access : 8bit Read Bit No. Description Reserved RSW1status Switching of ATA, CAMERA and UART modes. Back Light Address : 0xB400 1004 Access : 8bit Read/Write Bit No. Description Controls the backlight intensity in 255 tones (steps) when BK_LIGHT is set to ON. The initial value is 0x80. 0xFF: Bright :...
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7-seg LED control Address : 0xB400 1010- 0xB400 101F Access : 8bit Read/Write Bit No. Description Reserved LED1dot 1: On 0: Off LED1data display bit3-0 led display bit3-0 led display bit3-0 led display bit3-0 led display Fig.25 7-seg LED BOARD Controller ---- 29...
LED control Address : 0xB400 1020- 0xB400 102F Access : 8bit Read/Write Bit No. Description Reserved LED6 1: On 0: Off LED5 1: On 0: Off LED4 1: On 0: Off LED3 1: On 0: Off DIPSW2 control Address : 0xB400 1003 Access : 8bit Read Bit No.
8.2 NAND FLASH control The NAND FLASH controller provides controls over NAND Flash (IC7) and NAND Flash expansion connector. This NAND FLASH control is not part of the i.MX31 functions, but has been installed as an external FPGA. It is provided with a 2Kbytes MAIN Buffer RAM and 64-bytes SPAR Buffer RAM.
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ECC_STATUS Indicates ECC error conditions. Address : 0xB620 0E0C Access : 16bit Read/Write Bit No. Description 15-4 Reserved ECC Error for Main Area Data 00:No Error 01:1-bit Error 10:Error 11:Reserved ECC Error for Spare Area Data 00:No Error 0:1-bit Error 10:Error 11:Reserved ECC Error Position Main...
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With the setting of ECC_EN=1, bit-by-bit error detection is undertaken per page. Once a program is created, 28 bits of error codes and 10 bits of error codes will be generated for Main Area and Spare Area respectively, and stored in the Spare Area.
8.3 F_UART This is the register of UART in FPGA. F_UART is linked to Touch Panel (at the fixed baud rate of 19200 bps). Word Length is fixed to 8-bits long. The register assignment is 16550-compatible. Interrupt signals are linked to the GPIO1_1 line. Address : 0xB400 1050 Access...
9.10 ATA ATAPWR_SEL Fig.38 CN11 ATA Connector A dedicated buffer, etc., runs between the i.MX31 and this connector as shown in the following table. It is necessary to make pin settings on the i.MX31 side too. For this, refer to Signal Descriptions and Pin Assignments in the i.MX31 Manual and the Linux source file, MX3KZ_GPIO.C.
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ATA 44PIN i.MX31 ATA 44PIN i.MX31 signal signal signal signal /RESET ATA_RESETn /DIOW ATA_DIOW STXD3 /DIOR ATA_DIOR SRXD3 CSPI1_SPI_RDY IORDY PWMO SCK3 CSEL CSPI1_SCLK /DACK ATA_DMACK DD10 SFS3 CSPI1_SS2 INTRQ USBH2_CLK DD11 STXD6 /IOIS16 CSPI1_SS1 USBH2_D0 DD12 SRXD6 /PDIAG CSPI1_SS0 USBH2_NXT DD13 SCK6...
9.11 LCD (optional) Fig .39 CN29, 30 TOUCH PANEL LCD Connectors A dedicated buffer, etc., runs between the i.MX31 and this connector, as shown in the following table. It is necessary to make pin settings on the i.MX31 side too. For this, refer to Signal Descriptions and Pin Assignments in the i.MX31 Manual and the Linux source file, MX3KZ_GPIO.C.
9.13 CAMERA (option) Fig. 41 CN20, 23 CAMERA Connectors i.MX31 i.MX31 SIGNAL SIGNAL CSI_D0 CPU_CSI_D8 CSI_D1 CPU_CSI_D9 CSI_D2 CPU_CSI_D10 CSI_D3 CPU_CSI_D11 CSI_D4 CPU_CSI_D12 CSI_D5 CPU_CSI_D13 CSI_D6 CPU_CSI_D14 CSI_D7 CPU_CSI_D15 CSI_PIXCLK CPU_CSI_PIXCLK Table 22 CN20 CAMERA Connector CAMERA power supply connector: 53261-0471 SIGNAL +12V Table 23 CN20 CAMERA POWER Connector...
10 About the Sample Software The supplied CD-ROM contains the source codes for RedBoot and Linux kernel in addition to the userland resources. For detail of these contents see readme.txt. About the Sample Software ---- 53...