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IC BLOCK DIAGRAM & DESCRIPTION
IC818 LE28DW8163T-70T-MPB(8Mbit Flash)
1
A15
2
A14
3
A13
4
A12
5
A11
6
A10
7
A9
8
A8
9
NC
10
NC
11
WE#
12
RESET#
13
NC
14
WP#
15
RY/BY#
16
A18
17
A17
18
A7
19
A6
20
A5
21
A4
22
A3
23
A2
24
A1
Symbols
A18,A17
Bank Selective Address
A16-A0,A-1
Flush Bank Address
A18-A15
Flush Bank Block Address
A18-A10
Flush Bank Sector Sddress
DQ15-DQ0
Data Input/Output
CE#
Chip Enable
OE#
Output Enable
WE#
Write Enable
BYTE#
Bait Pin
RY/BY#
Ladey/Beje Output
WP#
Write Protect
RESET#
Reset
VDD
Power Supply
VSS
Ground
48
A16
47
BYTE#
CHARGE PUMP
46
VSS
&
45
DQ15/A-1
VOLTAGE
44
DQ7
REFERENCE
43
DQ14
CIRCUIT
42
DQ6
41
DQ13
40
DQ5
ADDRESS BUFFER
39
DQ12
&
38
DQ4
LATCH CIRCUIT
37
VDD
36
DQ11
35
DQ3
34
DQ10
A18-A0,A-1
33
DQ2
CE#
32
DQ9
OE#
31
DQ1
WE#
30
DQ8
WP#
CONTROL LOGIC
29
DQ0
RY/BY#
28
OE#
RESET#
27
VSS
BYTE#
26
CE#
25
AD
Pin Name
Selects bank 1 when "L" and bank 2.
Sapply address for flush bank.
Select flush bank for erease.
Select flush bank sector for erease.
To output data during read cycle and receive input data during write
cycles. Data is internaliy latched during a writecycle. The output are
high inpedance when OE#,CE# is "H".
To activate the flush bank when CE# is "L".
To activate the data output buffer .
To control the write, erease and program.
Bait mode when "L" and word mode when "H".
Output "L" when write and ezcept "H".
To activate hardware write protect when "L".
To activate hardware reset when "L".
2.7V~3.6V supply.
- 30 -
COLUMN DECODER
128Kx16
LOW DECODER
256Kx8
FLUSH
BANK2
DQ15-DQ0
IN/OUTPUT BUFFER
Functions
or
384Kx16
or
788Kx8
FLUSH
BANK1
&
DATA LATCH
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