Summary of Contents for FPGANETWORKING SGA10GD
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Page 1: Ethernet Adapter
SGA10GD Dual 10Gbps PCI Expressx8 Ethernet adapter REFERENCE MANUAL Ver.: 2009.09.29., Ver. 1.1 (C) BUDAPEST UNIVERSITY OF TECHNOLOGY AND ECONOMICS DEPARTMENT OF TELECOMMUNICATIONS AND MEDIA INFORMATICS... -
Page 2: Table Of Contents
Contents Contents......................................2 1. Introduction....................................3 1.1 What is SGA10GD?................................3 1.2 What is on-board?..................................3 1.3 Conformity.....................................4 2. Architecture....................................5 2.1 Power Supply..................................6 2.2 Clock sources..................................7 2.3 Dual XFPs for 10Gbps Ethernet............................8 2.4 PCI Express x8 endpoint..............................10 2.5 DDR2 SODIMM RAM................................12 2.6 Feature Connector................................14 2.7 FPGA Programming................................16... -
Page 3: Introduction
1. Introduction 1.1 What is SGA10GD? SGA10GD is a PCI-Express x8 adapter card, primarily developed for 10Gbits Ethernet network monitoring. It's on-board resources, and reconfigurability of its FPGA extends its functionality beyond the 10G application, 1.2 What is on-board? The figures below show the major on-board components. -
Page 4: Conformity
1.3 Conformity SGA10GD aims the following Standards/Recommendations: 10 Gigabit Small Form Factor Pluggable Module SFF Committee INF-8077i 10 Gigabit Small Form Factor Pluggable Module ...GBE Gigabit Ethernet (Optical/Copper) IEEE Std 802.3 Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications PCIE PCI Express PCI-SIG PCI Express Base Specification Revision 1.0a... -
Page 5: Architecture
2. Architecture The simple and robust architecture of SGA10GD is shown on the block diagram below. The heart of the board is a Xilinx Virtex-5 family FPGA device. The PCB can accomodate two types of devices: XC5VLX110T-2FF1136C (for SGA10GD board) ... -
Page 6: Power Supply
4 Tri-mode (10/100/1000)Ethernet Media Access Controller (MAC) 2 Internal Configuration Acces Ports (ICAP) Core logic can run at 550MHz internal clock speed Two SGA10GD models can be produced depending on the insertion of FPGA type as shown below: Model FPGA SGA10GD XC5VLX110T SGA10GDLXC5VLX50T The following sections detail the rest of the board's architectual elements. -
Page 7: Clock Sources
XPF aux. power VCC1V2 1.222XFP/XAUI XFP/XAUI converter Main supply 2.2 Clock sources There are three clock sources available on SGA10GD for the FPGA cores. The following tables shows their name, nominal frequencies, designated FPGA pins, and their application. Signal f [MHz]FPGA#... -
Page 8: Dual Xfps For 10Gbps Ethernet
Dedicated 156.25 MHz reference clock source is available for FPGA reference, and and other XO reference for XAUI/XFI converter chips. The SGA10GD board provides filtered 1,8V, 3.3V, 5V, power to both XFP modules as per the XFP specification. The table below lists the connectors pins and any associated FPGA connectivity. - Page 9 The table below lists the XAUI/XFI converter vs. FPGA connectivity. Common Signal Function FPGA# PRTAD[0] Port base address 0AJ11 PRTAD[1] Port base address 1AP12 PRTAD[2] Port base address 2AK11 PRTAD[3] Port base address 3AN12 PRTAD[4] Port base address 4AM11 U12 Signals Function FPGA# U14 Signals Function...
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Page 10: Pci Express X8 Endpoint
2.4 PCI Express x8 endpoint The PCI Express endpoint connector (designated as J1 on-board) allows an FPGA design to support x1, x4 and x8 gigabit lanes to communicate with the host, at the speed of 2.5 Gbps of each. Caution! There are jumpers - designated as J2, J9 - on board to select the proper presence detect lane configuration (close J2 for x4, plus close J9 for x8) for the actual design. - Page 11 ** TXPOLARITY attribute for the MGT has to be changed Although the PCI identification codes are FPGA core dependeant, defaults are the following: Vendor ID..15C6 ..Technical University of Budapest Device ID..106D ..SGA10GD dual 10Gbps Ethernet adapter Revision ID..1 ..Rev. 1. (SGA10GD) Base Class..
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Page 12: Ddr2 Sodimm Ram
2.5 DDR2 SODIMM RAM The SGA10GD board contains a 200-pin, small-outline dual in-line memory module (SODIMM) receptacle ( J3 ) that supports installation of DDR2 SDRAM SODIMMs of 128MB, 256MB, or 512 MB. Dual-rank SODIMMs may not be supported. Also, the speed grade of -1 of the default FPGA installation limits the DDR2 memory clock support to a range of 200-233MHz (400-466 million transfers per second - double rate). - Page 13 DQ[25] DQ[29] DM[3] DQS_N[3] NC/RESET_N 069 DQS[3] DQ[26] DQ[30] DQ[27] DQ[31] CKE[0] CKE[1] VCC1V8 VCC1V8 NC/CSN[2] A[15] BA[2] A[14] VCC1V8 VCC1V8 A[12] A[11] A[9] A[7] A[8] A[6] VCC1V8 VCC1V8 A[5] A[4] A[3] A[2] A[1] A[0] AA30 VCC1V8 VCC1V8 A[10] BA[1] BA[0] RAS_N AA31...
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Page 14: Feature Connector
(GND) 2.6 Feature Connector Mainly for historical reason, a 40 pins BERG type Feature Connector ( designated as J5 ) is used for SGA10GD. The table below shows the pinout assignment for FPGA cores implementing IDE/HDD applications. Signal (even)J5#FPGA#.Signal (odd)J5#FPGA#... - Page 15 Note that TTXA and TTXB signals are bound together on the child board to achive the 3 volts peak voltage of the transmitted pulses. (conforming ITU-T Rec. G.703) Crosscurrent glitches are limited by serial resistors on SGA10GD card. The child board has four interfaces with RJ12 connectors, as shown below.
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Page 16: Fpga Programming
2.7 FPGA Programming Three configuration methods are available on SGA10GD to upload (program) the FPGA core. 2.7.1 Programming through JTAG FPGA core can be loaded directly through the JTAG port (designated as J7 on-board) as shown in the figure below 2.7.2 Programming from FLASH... -
Page 17: Partial Reconfiguration
2.7.3 Partial reconfiguration If the Platform FLASH contains the proper core implementing a PCI Express endpoint, and a controller core for ICAP (Internal Configuration Access Port) - this RESIDENT core allows the Partial reconfiguration of the FPGA. TRANSIENT cores can be loaded that way. J6 jumper controls HSWAPEN. -
Page 18: Fpga Test Cores
FPGA to be reloaded from the Platform Flash when the OS restarts, or the reset button is pushed on the PC. Using the Microsoft Windows XP operating system, SGA10GD is found as a new hardware with the following ID's:... -
Page 19: Clock Domains
The test is passed if SGA10GD shows green lit for all LEDs (P2 blinks slowly). 4.4 Clock domains The following table summarizes the proposed clock domains to help devloping new/combined FPGA Cores. It can also be used for estimating the performace of core by using the data bits column for a given clock rate.
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