LG 32LV355T Service Manual page 20

VCC1.5V_U3_DDR
DDR3 1.5V By CAP - Place these Caps near Memory
OPT
Close to DDR Power Pin
VCC1.5V_U3_DDR
VCC1.5V_U3_DDR
C-MVREFDQ
CLose to DDR3 CLose to Saturn7M IC
EAN61828901
IC301
H5TQ1G63DFR-H9C
FRC_DDR_1333_HYNIX
M8 N3
C-MVREFCA
VREFCA A0
P7
A1
P3
A2
H1 N2
C-MVREFDQ VREFDQ A3
P8
A4
P2
R303 A5
L8 R8
ZQ A6
R2
240
A7
1% T8
A8
B2 R3
VDD_1 A9
D9 L7
VDD_2 A10/AP
G7 R7
VDD_3 A11
K2 N7
VDD_4 A12/BC
K8 T3
VDD_5 A13
N1
VDD_6
N9 M7
VDD_7 NC_5
R1
VDD_8
R9 M2
VCC1.5V_U3_DDR
VDD_9 BA0
N8
BA1
M3
BA2
A1
VDDQ_1
A8 J7
VDDQ_2 CK
C1 K7
VDDQ_3 CK
C9 K9
VDDQ_4 CKE
D2
VDDQ_5
E9 L2
VDDQ_6 CS
F1 K1
VDDQ_7 ODT
H2 J3
VDDQ_8 RAS
H9 K3
VDDQ_9 CAS
L3
WE
J1
NC_1
J9 T2
NC_2 RESET
L1
NC_3
L9
NC_4
T7 F3
NC_6 DQSL
G3
DQSL
A9 C7
VSS_1 DQSU
B3 B7
VSS_2 DQSU
E1
VSS_3
G8 E7
VSS_4 DML
J2 D3
VSS_5 DMU
J8
VSS_6
M1 E3
VSS_7 DQL0
M9 F7
VSS_8 DQL1
P1 F2
DQL2
VSS_9
P9 F8
VSS_10 DQL3
T1 H3
VSS_11 DQL4
T9 H8
VSS_12 DQL5
G2
DQL6
H7
DQL7
B1
VSSQ_1
B9 D7
VSSQ_2 DQU0
D1 C3
VSSQ_3 DQU1
D8 C8
VSSQ_4 DQU2
E2 C2
VSSQ_5 DQU3
E8 A7
VSSQ_6 DQU4
F9 A2
VSSQ_7 DQU5
G1 B8
VSSQ_8 DQU6
G9 A3
VSSQ_9 DQU7
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
+1.5V_FRC_DDR
L301
C324
10uF
10V
C-MVREFCA
AR301
C-MA9 C-TMA9
C-MA2 C-TMA2
C-MA0 C-TMA0
C-MBA2 C-TMBA2
22
AR302
C-MA8 C-TMA8
C-MA6 C-TMA6
C-MA4 C-TMA4
C-MBA1 C-TMBA1
22
AR303
C-MA10 C-TMA10
C-MA12 C-TMA12
C-MA1 C-TMA1
C-MA0
C-TMA11
C-MA11
C-MA1
22
C-MA2
AR304
C-MA3
C-MA3 C-TMA3
C-MA4
C-MA5 C-TMA5
C-MA5
C-MA7 C-TMA7
C-MA6
C-MRESETB C-TMRESETB
C-MA7
22
C-MA8
R307
C-MA9
C-MCK C-TMCK
C-MA10 22
R308
C-MA11
C-MCKB C-TMCKB
C-MA12
22
C-TMRASB
R309
C-TMCASB
C-MCKE C-TMCKE
22
R310
C-MRASB C-TMRASB C-TMRESETB
C-MBA0
22
C-MBA1
AR305
C-MBA2
C-MCASB C-TMCASB
C-TMDQSL
C-MCK
C-MODT C-TMODT
C-TMDQSLB
C-MWEB C-TMWEB
C-MCKB C-MBA0 C-TMBA0
C-TMDQSU
22
C-TMDQSUB
C-MCKE
R311
C-TMDQSL
C-MDQSL
C-MODT 22
R312
C-MRASB
C-MDQSLB C-TMDQSLB
C-MCASB
22
VCC1.5V_U3_DDR
C-TMDQL0
C-MWEB R333 R313
10K C-TMDQL1
C-MDQSU C-TMDQSU
22
C-TMDQL2
C-MRESETB R314
C-TMDQL3
C-MDQSUB C-TMDQSUB
22 C-TMDQL4
R315
C-TMDQL5
C-MDQSL
C-MDMU C-TMDMU
C-TMDQL6
C-MDQSLB 22
C-TMDQL7
AR306
C-MDQSU
C-TMDQL7
C-MDQL7
C-TMDQU0
C-MDQSUB
C-MDQL3 C-TMDQL3
C-TMDQU1
C-MDQL1 C-TMDQL1
C-TMDQU2
C-MDML
C-MDML C-TMDML
C-TMDQU3
C-MDMU
22
C-TMDQU4
AR307
C-TMDQU5
C-MDQL0
C-MDQL0 C-TMDQL0
C-TMDQU6
C-MDQL1 C-MDQL2 C-TMDQL2
C-TMDQU7
C-MDQL2
C-MDQL6 C-TMDQL6
C-MDQL3 C-MDQL4 C-TMDQL4
C-MDQL4 22
C-MDQL5 R316
C-MDQL5 C-TMDQL5
C-MDQL6
22
C-MDQL7
AR308
C-MDQU2 C-TMDQU2
C-MDQU0
C-MDQU6 C-TMDQU6
C-MDQU1
V_SYNC
C-MDQU0 C-TMDQU0
C-MDQU2
C-MDQU4 C-TMDQU4
C-MDQU3
22
C-MDQU4
AR309
C-MDQU5
C-MDQU7 C-TMDQU7
C-MDQU6
C-MDQU1 C-TMDQU1
C-MDQU7
C-MDQU5 C-TMDQU5
C-MDQU3 C-TMDQU3
22
VCC1.5V_U3_DDR
C325
0.1uF
16V
S7M-PLUS_DivX_MS10
IC101
LGE107DC-RP [S7M+ DIVX/MS10]
AE1 W26
C-TMA0 FRC_DDR3_A0/DDR2_NC ACKP/RLV3P/RED[3]
AF16 W25
C-TMA1
FRC_DDR3_A1/DDR2_A6 ACKM/RLV3N/RED[2]
AF1 U26
C-TMA2 FRC_DDR3_A2/DDR2_A7 A0P/RLV0P/RED[9]
AE3 U25
C-TMA3 FRC_DDR3_A3/DDR2_A1 A0M/RLV0N/RED[8]
AD14 U24
C-TMA4 FRC_DDR3_A4/DDR2_CASZ A1P/RLV1P/RED[7]
AD3 V26
C-TMA5 FRC_DDR3_A5/DDR2_A10 A1M/RLV1N/RED[6]
AF15 V25
C-TMA6 FRC_DDR3_A6/DDR2_A0 A2P/RLV2P/RED[5]
AF2 V24
C-TMA7 FRC_DDR3_A7/DDR2_A5 A2M/RLV2N/RED[4]
AE15 W24
C-TMA8
FRC_DDR3_A8/DDR2_A2 A3P/RLV4P/RED[1]
AD2 Y26
C-TMA9 FRC_DDR3_A9/DDR2_A9 A3M/RLV4N/RED[0]
AD16 Y25
C-TMA10
FRC_DDR3_A10/DDR2_A11 A4P/RLV5P/GREEN[9]
AD15 Y24
C-TMA11 FRC_DDR3_A11/DDR2_A4 A4M/RLV5N/GREEN[8]
AE16
C-TMA12
FRC_DDR3_A12/DDR2_A8
AC26
BCKP/TCON13/GREEN[1]
AC25
BCKM/TCON12/GREEN[0]
AA26
B0P/RLV6P/GREEN[7]
AF3 AA25
C-TMBA0 FRC_DDR3_BA0/DDR2_BA2 B0M/RLV6N/GREEN[6]
AF14 AA24
C-TMBA1 FRC_DDR3_BA1/DDR2_ODT B1P/RLV7P/GREEN[5]
AD1 AB26
C-TMBA2 FRC_DDR3_BA2/DDR2_A12 B1M/RLV7N/GREEN[4]
AB25
B2P/RLV8P/GREEN[3]
AD13 AB24
C-TMCK
FRC_DDR3_MCLK/DDR2_MCLK B2M/RLV8N/GREEN[2]
AE14 AC24
C-TMCKE FRC_DDR3_CKE/DDR2_RASZ B3P/TCON11/BLUE[9]
AE13 AD26
C-TMCKB
FRC_DDR3_MCLKZ/DDR2_MCLKZ B3M/TCON10/BLUE[8]
AD25
B4P/TCON9/BLUE[7]
AD24
B4M/TCON8/BLUE[6]
AE4
C-TMODT FRC_DDR3_ODT/DDR2_BA1
AD5
FRC_DDR3_RASZ/DDR2_WEZ
AF4 AD23
FRC_DDR3_CASZ/DDR2_CKE CCKP/LLV3P
AD4 AE23
C-TMWEB FRC_DDR3_WEZ/DDR2_BA0
CCKM/LLV3N
AE26
C0P/LLV0P/BLUE[5]
AE2 AE25
FRC_DDR3_RESETB/DDR2_A3 C0M/LLV0N/BLUE[4]
AF26
C1P/LLV1P/BLUE[3]
AF25
C1M/LLV1N/BLUE[2]
AF8 AE24
FRC_DDR3_DQSL/DDR2_DQS0 C2P/LLV2P/BLUE[1]
AD9 AF24
FRC_DDR3_DQSLB/DDR2_DQSB0 C2M/LLV2N/BLUE[0]
AF23
C3P/LLV4P
AE9 AD22
FRC_DDR3_DQSU/DDR2_DQS1 C3M/LLV4N
AF9 AE22
FRC_DDR3_DQSUB/DDR2_DQSB1 C4P/LLV5P
AF22
C4M/LLV5N
AE11
C-TMDML
FRC_DDR3_DML/DDR2_DQ7
AF6
C-TMDMU FRC_DDR3_DMU/DDR2_DQ11
AD19
DCKP/TCON5
AE6 AE19
FRC_DDR3_DQL0/DDR2_DQ6 DCKM/TCON4
AF11 AD21
FRC_DDR3_DQL1/DDR2_DQ0 D0P/LLV6P
AD6 AE21
FRC_DDR3_DQL2/DDR2_DQ1 D0M/LLV6N
AD12 AF21
FRC_DDR3_DQL3/DDR2_DQ2 D1P/LLV7P
AE5 AD20
FRC_DDR3_DQL4/DDR2_DQ4 D1M/LLV7N
AF12 AE20
FRC_DDR3_DQL5/DDR2_NC D2P/LLV8P
AF5 AF20
FRC_DDR3_DQL6/DDR2_DQ3 D2M/LLV8N
AE12 AF19
FRC_DDR3_DQL7/DDR2_DQ5 D3P/TCON3
AD18
D3M/TCON2
AE10 AE18
FRC_DDR3_DQU0/DDR2_DQ8 D4P/TCON1
AF7 AF18
FRC_DDR3_DQU1/DDR2_DQ14 D4M/TCON0
AD11
FRC_DDR3_DQU2/DDR2_DQ13
AD7
FRC_DDR3_DQU3/DDR2_DQ12
AD10 AB22
FRC_DDR3_DQU4/DDR2_DQ15 GPIO0/TCON15/HSYNC/VDD_ODD
AE7 AB23
FRC_DDR3_DQU5/DDR2_DQ9 GPIO1/TCON14/VSYNC/VDD_EVEN
AF10 AC23
FRC_DDR3_DQU6/DDR2_DQ10 GPIO2/TCON7/LDE/GCLK4
AD8 AC22
FRC_DDR3_DQU7/DDR2_DQM1 GPIO3/TCON6/LCK/GCLK2
AB16
FRC_SPI_CZ
AA14
FRC_GPIO1
AC15
FRC_SPI1_CK
Y16
FRC_GPIO8
FRC_L/DIM
AC16
33
R332 FRC_SPI_DO
AE8 AC14
FRC_DDR3_NC/DDR2_DQM0 FRC_SPI1_DI
R317
820
Y11 AA16
FRC_VSYNC_LIKE
FRC_SPI_CK
Y19 AA15
S7M-R
FRC_TESTPIN FRC_SPI_DI
Y10
R317-*1
FRC_I2CS_DA
4.7K
AA11
FRC_I2CS_CK
S7M-PLUS
AB15
FRC_PWM0
AB14
FRC_PWM1
R344
0
3D_SG
EAN61829001
IC301-*2
H5TQ1G63DFR-PBC
FRC_DDR_1600_HYNIX
N3 M8
A0 VREFCA
P7
A1
P3
A2
N2 H1
A3 VREFDQ
P8
A4
P2
A5
R8 L8
A6 ZQ
R2
A7
T8
A8
R3 B2
A9 VDD_1
L7 D9
A10/AP VDD_2
R7 G7
A11 VDD_3
N7 K2
A12/BC VDD_4
T3 K8
A13 VDD_5
N1
VDD_6
M7 N9
A15 VDD_7
R1
VDD_8
M2 R9
BA0 VDD_9
N8
BA1
M3
BA2
A1
VDDQ_1
J7 A8
CK VDDQ_2
K7 C1
CK VDDQ_3
K9 C9
CKE VDDQ_4
D2
VDDQ_5
L2 E9
CS VDDQ_6
K1 F1
ODT VDDQ_7
J3 H2
RAS VDDQ_8
K3
H9
CAS VDDQ_9
L3
WE
J1
NC_1
T2 J9
RESET NC_2
L1
NC_3
L9
NC_4
F3 T7
DQSL NC_6
RXBCK+ G3
DQSL
RXBCK-
RXB0+ C7 A9
DQSU VSS_1
RXB0- B7 B3
DQSU VSS_2
RXB1+ E1
VSS_3
RXB1- E7 G8
DML VSS_4
RXB2+ D3 J2
DMU VSS_5
RXB2- J8
VSS_6
RXB3+ E3 M1
DQL0 VSS_7
RXB3- F7 M9
DQL1 VSS_8
RXB4+ F2 P1
DQL2 VSS_9
RXB4- F8 P9
DQL3 VSS_10
H3 T1
DQL4 VSS_11
H8 T9
DQL5 VSS_12
RXACK+ G2
DQL6
RXACK- H7
DQL7
RXA0+ B1
VSSQ_1
RXA0- D7 B9
DQU0 VSSQ_2
RXA1+ C3 D1
DQU1 VSSQ_3
RXA1- C8 D8
DQU2 VSSQ_4
RXA2+ C2 E2
DQU3 VSSQ_5
RXA2- A7 E8
DQU4 VSSQ_6
RXA3+ A2 F9
DQU5
VSSQ_7
RXA3- B8 G1
DQU6 VSSQ_8
RXA4+ A3 G9
DQU7 VSSQ_9
RXA4-
RXCCK+
RXCCK-
RXC0+
RXC0-
RXC1+
RXC1-
RXC2+
RXC2-
RXC3+
RXC3-
RXC4+
RXC4-
+3.3V_Normal
RXDCK+
RXDCK-
RXD0+
RXD0-
RXD1+
RXD1-
RXD2+
RXD2-
RXD3+
RXD3-
RXD4+
RXD4-
FRC_MODEL_OPT_0
FRC_MODEL_OPT_1
FRC_MODEL_OPT_2
2D/3D_CTL
FRC_/SPI_CS
FRC_CONF0
R300 33
L/DIM_SCLK
FRC_L/DIM
FRC_CONF1
FRC_SPI_SDO
R348 33
L/DIM_MOSI
FRC_L/DIM
FRC_SPI_SCK
FRC_SPI_SDI
R326 22
FRC
I2C_SDA
R331 22
FRC
I2C_SCL
R335
22
FRC_SCL
FRC_PWM0
OPT
FRC_PWM1
FRC_SDA +3.3V_Normal
22
R334
OPT
S7M-PLUS_S_FLASH_2MBIT_WIN
IC302
W25X20BVSNIG
S7M-PLUS
3D_SYNC_RF
R329
10 CS
1
FRC_/SPI_CS $ 0.17
R330
10 DO
FRC_SPI_SDO 2
S7M-PLUS
WP
3
GND
4
EAN61857101
IC301-*3 EAN61857201
K4B1G1646G-BCH9 IC301-*4
NT5CB64M16DP-CF
FRC_DDR_1333_SS_NEW
N3 M8
FRC_DDR_1333_NANYA_NEW
A0 VREFCA
P7 N3 M8
A1 A0 VREFCA
P3 P7
A2 A1
N2 H1 P3
A3 VREFDQ A2
P8 N2 H1
A4 A3 VREFDQ
P2 P8
A5 A4
R8 L8 P2
A6 ZQ A5
R2 R8 L8
A7 A6 ZQ
T8 R2
A8 A7
R3 B2 T8
A9 VDD_1 A8
L7 D9 R3 B2
A10/AP VDD_2 A9 VDD_1
R7 G7 L7 D9
A11 VDD_3 A10/AP VDD_2
N7 K2 R7 G7
A12/BC VDD_4 A11 VDD_3
T3 K8 N7 K2
A13 VDD_5 A12 VDD_4
N1 T3 K8
VDD_6 NC_6 VDD_5
M7 N9 N1
NC_5 VDD_7 VDD_6
R1 M7 N9
VDD_8 NC_5 VDD_7
M2 R9 R1
BA0 VDD_9 VDD_8
N8 M2 R9
BA1 BA0 VDD_9
M3 N8
BA2 BA1
A1 M3
VDDQ_1 BA2
J7 A8 A1
CK VDDQ_2 VDDQ_1
K7 C1 J7 A8
CK VDDQ_3 CK VDDQ_2
K9 C9 K7 C1
CKE VDDQ_4 CK VDDQ_3
D2 K9 C9
VDDQ_5 CKE VDDQ_4
L2 E9 D2
CS VDDQ_6 VDDQ_5
K1 F1 L2 E9
ODT VDDQ_7 CS VDDQ_6
J3 H2 K1 F1
RAS VDDQ_8 ODT VDDQ_7
K3 H9 J3 H2
CAS VDDQ_9 RAS VDDQ_8
L3 K3 H9
WE CAS VDDQ_9
J1 L3
NC_1 WE
T2 J9 J1
RESET NC_2 NC_1
L1 T2 J9
NC_3 RESET NC_2
L9 L1
NC_4 NC_3
F3 T7 L9
DQSL NC_6 NC_4
G3 F3 T7
DQSL DQSL NC_7
G3
DQSL
C7 A9
DQSU VSS_1
B7 B3 C7 A9
DQSU VSS_2 DQSU VSS_1
E1 B7 B3
VSS_3 DQSU VSS_2
E7 G8 E1
DML VSS_4 VSS_3
D3 J2 E7 G8
DMU VSS_5 DML VSS_4
J8 D3 J2
VSS_6 DMU VSS_5
E3 M1 J8
DQL0 VSS_7 VSS_6
F7 M9 E3 M1
DQL1 VSS_8 DQL0 VSS_7
F2 P1 F7 M9
DQL2 VSS_9 DQL1 VSS_8
F8 P9 F2 P1
DQL3 VSS_10 DQL2 VSS_9
H3 T1 F8 P9
DQL4 VSS_11 DQL3 VSS_10
H8 T9 H3 T1
DQL5 VSS_12 DQL4 VSS_11
G2 H8 T9
DQL6 DQL5 VSS_12
H7 G2
DQL7 DQL6
B1 H7
VSSQ_1 DQL7
D7 B9 B1
DQU0 VSSQ_2 VSSQ_1
C3 D1 D7 B9
DQU1 VSSQ_3 DQU0 VSSQ_2
C8 D8 C3 D1
DQU2 VSSQ_4 DQU1 VSSQ_3
C2 E2 C8 D8
DQU3 VSSQ_5 DQU2 VSSQ_4
A7 E8 C2 E2
DQU4 VSSQ_6 DQU3 VSSQ_5
A2 F9 A7 E8
DQU5 VSSQ_7 DQU4 VSSQ_6
B8 G1 A2 F9
DQU6 VSSQ_8 DQU5 VSSQ_7
A3 G9 B8 G1
DQU7 VSSQ_9 DQU6 VSSQ_8
A3 G9
DQU7 VSSQ_9
<U3 CHIP Config>
(FRC_CONF0)
HIGH : I2C ADR = B8
LOW : I2C ADR = B4
(FRC_CONF1,FRC_PWM1, FRC_PWM0)
FRC_MODEL_OPT_0
3'd5 : boot from internal SRAM
3'd6 : boot from EEPROM
FRC_MODEL_OPT_1
3'd7 : boot form SPI flash
FRC_MODEL_OPT_2
2D/3D_CTL
+3.3V_Normal
FRC_CONF0
FRC_CONF1
FRC_PWM1
FRC_PWM0
+3.3V_Normal
VCC
8
HOLD
7
S7M-PLUS
R328
CLK 10
6
FRC_SPI_SCK
R327
DIO
10
5
FRC_SPI_SDI
S7M-PLUS
GP2R 20101023
FRC_DDR 3
LGE Internal Use Only