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Table of Contents
Summary of Contents for Quin Systems CPU360
- Page 1 Quin Systems Limited CPU360 Issue D/E Hardware Manual Issue 4 June 2004 (MAN530)
- Page 2 Quin Systems Limited CPU360 Issue D/E Hardware Manual Issue 4 April 2004 (MAN530)
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Page 3: Copyright Notice
This manual reflects the Issue D/E CPU360 hardware. Important Notice Quin Systems reserves the right to make changes in the products described in this document in order to improve design or performance and for further product development. Examples given are for illustration only, and no responsibility is assumed for their suitability in particular applications. -
Page 4: Table Of Contents
Reset and Watchdog : J6 Processor Configuration : J7 CIO Clock Frequency : J8 Serial Port A Override : J9 3.10 Static Ram Size : J10 3.11 CANbus Interrupts : J11 3.12 Jumper Locations Copyright © 2004 Quin Systems Limited Page 1... - Page 5 Daughter Board Ethernet G64 Bus General Purpose I/O Background Debug Port 4.10 JTAG Port Diagnostics and Tests Switch-on Self-Test Entry to Flashboot Diagnostics Update Commands Exit to PTS code LED functions Index Copyright © 2004 Quin Systems Limited Page 2...
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Page 6: List Of Figures
Ethernet AUI connections Table 16. G64 bus connections : P1 Table 17. General purpose I/O connections : P2 Table 18. Background debug connector : P3 Table 19. JTAG test connector : P4 Copyright © 2004 Quin Systems Limited Page 3... -
Page 7: Introduction
Ethernet port with AUI and twisted pair interfaces, and two CANbus interfaces. It also has provision for an optional 68040 processor if more performance is required. The CPU360 provides four 32-pin JEDEC sockets for eproms or flash roms, allowing ×... -
Page 8: Using The Cpu360
68040 only uses a single DSACK signal, and all transfers are 32 bits wide. Software Control The CPU360 board makes extensive use of the programmable features of the 68360 cpu and its system integration module (SIM). These must be correctly set up by any application or system software when the board starts up. -
Page 9: Figure 1. Address Map
Issue 4 CPU360 Hardware Manual Because the CPU360 module uses the programmable chip select outputs for the rom, ram and i/o areas, the address map is determined by the software at startup. A suggested address map is shown in the following table. -
Page 10: G64 Bus Address Map
G64 bus : VMA Synchronous 1 MHz 0x08200000 0x081FFFFF G64 bus : VPA Synchronous 2 MHz 0x08100000 0x080FFFFF G64 bus : VMA Synchronous 2 MHz 0x08000000 Figure 2. G64 bus address map Copyright © 2004 Quin Systems Limited Page 7... -
Page 11: I/O Address Map
CPU360 Hardware Manual I/O Address Map The address map for the CPU360 I/O devices is shown below. Note that these devices are all 8 bits wide, but are accessed on the 32 bit processor bus to allow for the optional 68040 cpu. -
Page 12: 68360 Internal Registers
(factory fitted only) EEPROM 128k×8, 256k×8, or 512k×8. Note that the larger size dram and sram options must be specified when the CPU360 board is ordered, as they are surface mount packages and are soldered directly to the board. Also note that the use of larger memory devices may require software changes to correctly set up the programmable chip select pins on the 68360 processor. -
Page 13: Communications Ports
CPU360 Hardware Manual Communications Ports The serial communications ports on the CPU360 are very flexible, and use the CPM communications processor module on the 68EN360 cpu. The four ports are allocated as follows to the four serial communications controllers (SCCs) on the 68EN360. -
Page 14: Daughter Board Port
The daughter board uses XS3 and/or XS5 to bring its external signals out to two D type sockets on the CPU360. Copyright © 2004 Quin Systems Limited Page 11... -
Page 15: Serial Ports
J9 pins 1–2 for software control as described above. If this link is removed, then port A is set to RS-485 mode. If the link is fitted to J9 pins 2–3, then RS-232 mode is selected. Copyright © 2004 Quin Systems Limited Page 12... -
Page 16: Serial Eeprom
CPU360. The high speed communications modules use a local processor with a dual port memory interface to the CPU360. These use a local serial port to configure the communications module, which is via XS3 to the second 9 way D socket. -
Page 17: Configuration
The normal configuration is with the G64 bus /FIRQ interrupt connected to level 6, and the G64 bus /IRQ signal connected to irq level 2. The standard firmware supplied with the PTS system uses these interrupt levels. Copyright © 2004 Quin Systems Limited Page 14... -
Page 18: Reset And Watchdog : J6
CONFIG2 : 5 6 : /Reset /DSACK0 : 7 8 : /DSACK1 68040 TDO : 9 10 : 68360 TDO /MDIS : 11 12 : 0V Figure 6. Processor configuration : J7 Copyright © 2004 Quin Systems Limited Page 15... -
Page 19: Cio Clock Frequency : J8
93.75 kHz The clock oscillator enable input (pin S) is also brought to J8. This is to allow the clock to be disabled during board testing, and is not used in normal operation.. Copyright © 2004 Quin Systems Limited Page 16... -
Page 20: Serial Port A Override : J9
(e.g. HM628128), link J10 pins 1 and 2. For use with a 512k×8 device (e.g. HM628512), link pins 2 and 3. Note that the larger static ram is only available if specified when the CPU360 is ordered, as the device is in a surface mount package and is soldered directly to the circuit board. -
Page 21: Jumper Locations
Issue 4 CPU360 Hardware Manual 3.12 Jumper Locations CPU360 module - component side Bottom Figure 11. Jumper locations Copyright © 2004 Quin Systems Limited Page 18... -
Page 22: Connections
P1 pin 30a, P2 pin 30a –12V P1 pin 30b, P2 pin 30c Where the CPU360 is used as a Machine Manager, these supply rails are given by a dedicated backplane, taking +24 volts input. Serial Ports The following table shows the CPU360 serial port connections on the 9 way D sockets in position S4. -
Page 23: Canbus
CPU360 Hardware Manual CANbus The CPU360 has two double 9 way D plugs and sockets for two separate CANbus interfaces. Optional software will allow multiple PTS systems to be linked together via CANbus. This will support motor synchronisation between similar systems (peer to peer operation) and use of the CPU360 to supervise a number of CANbus slave modules. -
Page 24: Daughter Board
CPU360 Hardware Manual Daughter Board Two additional 9 way D sockets are fitted to the CPU360 in position S3. These are provided for use by any optional daughter board. The lower D socket connects to daughter board socket XS5, and the upper D socket connects to daughter board socket XS3. -
Page 25: G64 Bus
Data line /D7 Chain out CHOUT Chain in CHIN +12V supply –12V supply +5V supply VCC +5V supply VC 0V supply GND 0V supply GND Table 5: G64 bus connections : P1 Copyright © 2004 Quin Systems Limited Page 22... -
Page 26: General Purpose I/O
CAN1V+ (7-13V) CAN1 V+ (7-13V) CAN1 0V CAN1 0V +12V supply –12V supply +5V supply VCC +5V supply VCC 0V supply GND 0V supply GND Table 6: General purpose I/O connections : P2 Copyright © 2004 Quin Systems Limited Page 23... -
Page 27: Background Debug Port
Test methods using access through the JTAG port are described in the Controller Repairs Test Specification, document reference TST026. For JTAG testing, remember to link J7 9-10 unless the 68040 is fitted. Copyright © 2004 Quin Systems Limited Page 24... -
Page 28: Diagnostics And Tests
Issue 4 CPU360 Hardware Manual Diagnostics and Tests The flashboot functions of the CPU360 perform a brief self-test before starting the PTS code. Issue E also has features to enable firmware upgrade from the Toolkit 2000. Switch-on Self-Test The processor performs a brief memory self-test following switch-on. The LED numeric displays show testing status: •... -
Page 29: Exit To Pts Code
Green L1:A Ethernet transmit L1:B Ethernet receive L1:C Ethernet twisted pair: off = AUI L1:D Power-up self-test: see above L2:A Ethernet collision L2:B Ethernet jabber L2:C twisted pair polarity error L2:D Power-up self-test Copyright © 2004 Quin Systems Limited Page 26... -
Page 30: Index
LEDs download optional memory size firmware dram burst addressing PEPAR power supply connections eprom/flash pin 1 processor configuration eprom/flash pin 31 processor selection Ethernet connections Copyright © 2004 Quin Systems Ltd Page 27... - Page 31 A override serial port connections serial port signal names SIM module static ram size switch locations tristate control twisted pair watchdog configuration write protect serial eeprom Copyright © 2004 Quin Systems Limited Page 28...