Flash Memory; Serial Eeprom Memory; Audio Interface Audio Sampling Rate And Pll Component Configuration; Front Panel - Sharp DV-SV 80 H Service Manual

8. FLASH MEMORY

The decoder board supports 70ns Flash memories. Currently 4 configurations are supported:
• FLASH_512K_8b
• FLASH_1024K_8b
• FLASH_512Kx2_8b
• FLASH_512Kx2_16b
The MT1379 permits both 8- and 16-bit common memory I/O accesses with a removable storage card via the host interface.

9. SERIAL EEPROM MEMORY

An I2C serial EEPROM is used to store user configuration (i.e. language preferences, speaker setup, etc.) and software
configuration.. Industry standard EEPROM range in size from 1kbit to 256kbit and share the same IC footprint and pinout. The
default device is 2kbit, 256kx 8, SOIC8 SGS Thomson ST24C02M1 or equivalent.

10. AUDIO INTERFACE AUDIO SAMPLING RATE AND PLL COMPONENT CONFIGURATION

The MT1379 audio mode configuration is selectable, allowing it to interface directly with low-cost audio DACs and ADCs. The
audio port provides a standard I S interface input and output and S/PDIF (IEC958) audio output. Stereo mode is in I S format
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while six channels Dolby Digital (5.1 channel) audio output can be channeled through the S/PDIF. The S/PDIF interface consists
of a bi-phase mark encoder, which has low skew. The transmit I S interface supports the 112, 128, 192, 256, 384, and 512
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sampling frequency formats, where sampling frequency Fs is usually 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, or 192 kHz. The audio
samples for the I S transmit interface can be 16, 18, 20, 24, and 32-bit samples.
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For Linear PCM audio stream format, the MT1379 supports 48 kHz and 96 kHz. Dolby Digital audio only supports 48 kHz. The
MT1379 incorporates a built-in programmable analog PLL in the device architecture in order to generate a master audio clock.
The MCLK pin is for the audio DAC clock and can either be an output from or an input to the MT1379. Audio data out (TSD) and
audio frame sync (TWS) are clocked out of the MT1379 based on the audio transmit bit clock (TBCK). Audio receive bit clock
(RBCK) is used to clock in audio data in (RSD) and audio receive frame sync (RWS).

11. FRONT PANEL

11.1. VFD CONTROLLER

The VFD controller is a NEC uPD16311. This controller is not a processor, but does include a simple state machine which
scans the VFD and reads the front panel button matrix. The 16311 also includes RAM so it can store the current state of all
the VFD icons and segments. Therefore, the 16311 need only be accessed when the VFD status changes and when the button
status is read. The MT1379 can control this chip directly using PIO pins or can allow the front panel PIC to control the VFD.
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