Sony BDP-BX1 Service Manual page 70

QQ
3 7 63 1515 0
Pin No. Name
F18 SAVDDTIO
F19 SAVDDDIG
F20 GPIO27
F21 GPIO30
F22 GPIO25
F23 GPIO24
F24 GPIO17
F25 GPIO12
F26 GPIO7
F27 VRVDD
F28 TMODE5
F29 TEST
F30 S2DOUT
F31 AO1LRCK
F32 AO1BCK
F33 VDD3
G1 XO
G2 GND
G3 PCIAD28
G4 PCIAD26
G5 PCIAD31
G6 PCIAD15
G7 PCIAD16
G8 PCIAD10
G9 VDD3
G10 GND
G11 GPIO50
G12 GPIO75
TE
L 13942296513
G13 GPIO61
G14 VDD3
G15 GPIO73
G16 SAVDDDIG
G17 SAVDDANA
G18 SAGNDDIG
G19 SAGNDDIG
G20 GPIO36
G21 VDD10
G22 GND
G23 VDD3
G24 VDD3
G25 GPIO11
G26 VDD10
G27 VRGND
G28 TMODE2
G29 S2CKIN
G30 S0DOUT
G31 S0CKOUT
G32 S2DIN
G33 S0DIN
H1 GND
H2 CLKSEL
H3 PCICLKI
H4 GND
H5 PCIRSTB
www
H6 VDD3
H7 VDD10
H8 VOID
.
H9 VOID
H10 VOID
H11 VOID
H12 VOID
http://www.xiaoyu163.com
I/O
- 1.8V supply (Serial ATA Tx I/O)
- 1.05V supply (Serial ATA digital VDD)
I EJ2DINT (JTAG I/F_1 debug interrupt)
I PCI INT A (PCI Interrupt: USB)
I EJ2TMS (JTAG I/F_1 Mode Set)
O EJ2TDO (JTAG I/F_1 Data Out)
O XAMUTE (Audio Mute: "H": Normal "L": Mute)
O GLB XRST (Not used)
O PCI GNT1 (Not used)
- 1.05V supply for VR5500 PLL
I Test terminal (Not used: Fixed at "L")
I Test terminal (Not used: Fixed at "L")
O IF SDI (IFcon Communication Data Out)
O LR Clock for 2ch output
O Bit Clock for 2ch output
- 3.3V supply (I/O buffers)
O Crystal Output
- Ground for digital and DDR2 SDRAM
I/O PCI Address Data
I/O PCI Address Data
I/O PCI Address Data
I/O PCI Address Data
I/O PCI Address Data
I/O PCI Address Data
- 3.3V supply (I/O buffers)
- Ground for digital and DDR2 SDRAM
I/O VOHSB: Horizontal Sync Signal
I/O AOHBD0: Data output for External HDMI
I/O VODY9: Digital Video Y Data Output
- 3.3V supply (I/O buffers)
I/O AOHLRCK: External HDMI LRCK Clock Output
- 1.05V supply (Serial ATA digital VDD)
- 1.8V supply (Serial ATA analog VDD)
- Digital Ground for Serial ATA
- Digital Ground for Serial ATA
O FORMAT0 (480, 1080="0" 720="1")
- 1.05V supply (core)
- Ground for digital and DDR2 SDRAM
- 3.3V supply (I/O buffers)
- 3.3V supply (I/O buffers)
I EMMA_DIPSW0 (Fixed at "H")
- 1.05V supply (core)
- Ground for VR5500 PLL
I Test terminal (Not used: Fixed at "L")
I IF SCK (IFcon Communication Clock In)
O EMMA CSI0 DO (CSI0 Data Out)
O EMMA CSI0 CKIO (CSI0 Clock Out)
I IF SDO (IFcon Communication Data In)
I CSI0 DI (CSI0 Data In)
- Ground for digital and DDR2 SDRAM
I OSC27/CLK27IN Select Signal
I PCI 33MHz Clock Input
- Ground for digital and DDR2 SDRAM
I PCI Hardware Reset
- 3.3V supply (I/O buffers)
- 1.05V supply (core)
x ao u163
y
- This pin is not ball.
i
- This pin is not ball.
- This pin is not ball.
- This pin is not ball.
- This pin is not ball.
2 9
8
Description
Q Q
3 6 7 1 3 1 5
co
.
-
BDP-BX1/S350
9 4 2 8
0 5 8 2 9 9 4 2 8
m
9 9
9 9