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9!
M
IC BLOCK
DIAGRAM
& DESCRIPTION
—
IC902 LC78622E
(Digital Signal Processor)
No.
Pin Name
Uo
Function
1
DEFI
I
Input terminal for detect signal of defect
2
TAI
I
Input terminal for test.
3
PDO
o
The phase comparison output terminal for
external VCO control.
4
Vvss
-
Ground terminal for built-in VCO
5
lsEr
I
Resistance
connection terminal for
I
I
I
electric
cwrent
adjustment
of
PDO output.
1
~
-
Buiit-in
VCO
ower su
I
terminal.
O
EFM si nal out ut terminal for
slice level control.
I
EFM si nal in ut terminal for slice level control.
11
I
TEST2
I I
TEST pin. Normal time is non connti!on.
12 I
CLV+
I O 10utput terminal for Disc motor control.
13
CLV-
0
Output terminal for Disc motor control.
14
VIP
o
Change of rough servo I phase control
Rough servo: "H", Phase control: "L"
15
HFL
I
Input terminal of track search signal.
16
TES
I
Input terminal of tracking error signal.
17
TOFF
o
Output terminal of tracking off.
18
TGL
o
Output terminal for change of traddng gain.
19
JP+
o
Output terminal for tratilng jump control.
m
JP-
0
Output terminal for tracldng jump control.
21
PCK
o
Clock
monitor
output
terminal
for
EFM data
playback. (4.321 8 MHz)
22
FSEQ
o
Output
terminal
for detect
of
SYNC signal.
23
DVDD
-
+5V
24
CONT1
1/0
25
CONT2
I/o This output can control at serial control from
26
CONT3
I/o micro processor.
27
CONT4
1/0
28
CONT5
1/0
29
EMPH
o
Output terminal of d=emphasis monitor.
"H": de-emphasis
m
C2F
o
Output terminal of C2 flag
31
DOUT
o
Output terminal of digital out
No.
Pin Name
Uo
Function
3?
TEST3
I
Test pin.
33
TEST4
I
Test pin.
34
NC
-
Non connection.
%
MUTEL
o
Mute
output
terminal
for
L-ch
33
LVDD
-
Power supply for L-ch
37
LCHO
o
Output terminal for L-ch
26
LVSS
-
GND for L-ch
39
RVSS
-
GND for R-ch
40]
RCHO
I O 10ufput terminal for R-ch
41 ]
RVDD
I - I Power supply for R-ch
42 I MUTER
I O lMute output terminal for R-ch
431
XVDD
I - I Power supply of crystal oscillation
441
XOUT
] O lConnaction terminal of crystal oscillation (16.9344MHz~
46]
XIN
I lConnaction terminal of crystal oscillation (16.9344MHzj
46
Xvss
-
GND of crystal oscillation
47
SBSY
o
Output terminal for synchronizing signal of
sub-cord block
48
EFLG
o
Output terminal for correction monitor of Cl, C2,
Single and Double
49
Pw
o
Output terminal for sub-cord of P, Q, R, S, T, U and W
w
SFSY
o
Output terminal for synchronizing signal of
sub-cord frame
51
SBCK
I
Input terminal for readout dock of sub-cord
s
FSX
o
Output terminal of Synchronizing signal (7.36kHz)
ml
WRQ
I O IOutput terminal for standby of sub-cord Q output
541
RWC
I I I Input terminal of read /write control
56
SQOUT
o
Output terminal of sub-cord Q
56
COIN
I
Input terminal of command from micro processor
57
CQCK
I
CIOck inPUffor reading sub-cord from SQOUT
59
RES
I
Reset (turn on: L)
F.9
TST11
o
Test pin
63
16M
o
16.9344MHz
61 I
4.2M
I o 14.2336MHz
621
TEST5
I lTest pin
631
Cs
1
I lChip select terminal
641
TEST1
I lTest pin
EFMO
Vvco Vvss
PDO ISET FR
TST11TEST2 TEST4
PCK
TAI
TEST1 TEST3TESTS
Voo Vss
1
1
w
@
Slice Isvel
VCO Cb2k 03cillat0r
'7'
Fm
2K -8bit
RAM Adhss
Control
& Clock Control
RAM
Gsnsratoii
II
I
FSEQ@
Synmws
Detsd
EFM Demodulate
I
I
I
III-+
Cl CZ Error Detsct &
Chsct
Control Flag
SUbc@s Dxrac4
SFSY
CS
+'
I
Digiial Attenuator
wt3a
.%20UT
C-mR
COIN
RWC
WKr2
cnsr4
XV33
XWT
RVS5 MUTER
LVS3
-
C2F
00UT
(NC)
-
-13-
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