LG 37LF65 Service Manual page 55

SIi5100 Decoupling Capacitors
1.2V 1V2
L102 1
C166
HH-1M3216-501 2
10uF
16V
GND
2.5V 2V5
L101 1
C167
HH-1M3216-501 2 10uF
16V
003:J3
003:J3
GND
3V3
3.3V
L100
HH-1M3216-501
1
C168
2 10uF
16V
004:E2 IRQ2
003:F8 IRQ1
GND
3V3
PULL UP/DOWN
3V3
003:J4 R126
FMILBA 47
R128
002:A7 FMIWE 47
002:D8 FMICS3 R129
47
003:E8 R131
FMICS1 47
002:D8;003:J4 FMIOE R133
47
003:K5 R134
FMIBE1 47
For LCD
For PDP
P_3.3V
Voltage_detector
HH-1M3216-501 Voltage_detector
Voltage_detector
L110 R106-*1 R119-*1
TP112 1K
2K FMI_A[1-25] AR105
47
FMI_A[1] E2
FMI_A[2] E1 FMIADDR1
FMIADDR2
FMI_A[3] AR100 F3
FMI_A[4] 47 F2 FMIADDR3
FMIADDR4
Voltage_detector FMI_A[5] F1
IC101 FMI_A[6] G3 FMIADDR5
FMIADDR6
SW100 KIA7029AF FMI_A[7] AR106 G2
FMI_A[8] 47 G1 FMIADDR7
TMUE312GAB R122 FMIADDR8
1 2 I 1 3 O FMI_A[9] H3
TP113 CPU_RST 0 01:F3 FMI_A[10] H2 FMIADDR9
2 47 FMIADDR10
3 4 G FMI_A[11] AR101 H1
CON100 TP114 FMI_A[12] 47 J3 FMIADDR11
GIL-G-02P 5 FMIADDR12
FMI_A[13] J2
J1 FMIADDR13
OPT FMI_A[14] FMIADDR14
FMI_A[15] AR107 K3
1 47 K2 FMIADDR15
GND C202 FMI_A[16] FMIADDR16
100pF FMI_A[17] K1
50V M3 FMIADDR17
2 FMI_A[18] FMIADDR18
FMI_A[19] AR102 M2
47 M1 FMIADDR19
FMI_A[20] FMIADDR20
GND FMI_A[21] N3
Option for remote control N2 FMIADDR21
DTV_RESET FMI_A[22] FMIADDR22
FMI_A[23] N1
12K Must be used in case of P3 FMIADDR23
FMI_A[24] R125 FMIADDR24
using Cortez DTV_RESET FMI_A[25] P2
R106, R119 --> 0 ohm FMI_D[0-15] FMIADDR25
47
L110, L111 --> Delete FMI_D[0] 47 AR103 T3
3V3 R3 FMIDATA0
R121-*1 FMI_D[1] FMIDATA1
FMI_D[2] AR108 P1
13K 47 U3 FMIDATA2
FMI_D[3]
IC102 FMI_D[4] R2 FMIDATA3
INVERTER Voltage_detector R1 FMIDATA4
3V3 FMI_D[5]
74LVC14APW FMI_D[6] AR104 V3 FMIDATA5
47 FMIDATA6
FMI_D[7] T2
001:F3 1A VCC FMI_D[8] 1 8 T1 FMIDATA7
1 14 FMIDATA8
CPU_RST_OUT FMI_D[9] 2 7 W3
FMI_D[10] 3 6 U2 FMIDATA9
1Y 6A FMIDATA10
2 13 FMI_D[11] 4 5 AR109 U1
FMI_D[12] 47 V2 FMIDATA11
FMIDATA12
2A 6Y FMI_D[13] 4 5 V1
3 12 002:K2 FMI_D[14] 3 6 W2 FMIDATA13
FMIDATA14
LDA[0-12] FMI_D[15] 2 7 W1
2Y 4 11 5A 1 8 FMIDATA15
DTV_AUDIO_MUTE
LDA[0] B17
LDA[1] C17 LMIADDR0
3A 5 10 5Y LMIADDR1
LDA[2] A18
LDA[3] B18 LMIADDR2
3Y 4A LMIADDR3
6 9 LDA[4] B3
LDA[5] A3 LMIADDR4
LMIADDR5
GND 4Y R166 LDA[6] C4
7 8 DTV_AUDIO_MUTE_BUF LDA[7] B4 LMIADDR6
47 LMIADDR7
LDA[8] A4
LDA[9] C5 LMIADDR8
LMIADDR9
GND LDA[10] A17
LDA[11] B5 LMIADDR10
LMIADDR11
R102 LDA[12] A5
FE_RESET 003:K1 LMIADDR12
47
B16
002:K4 LDBA0 C16 LMIBA0
002:K4 LDBA1 LMIBA1
R103 B11
SYS_RST 002:K4 LDDQM0 A11 LMIDQM0
47 002:A7 002:K4 LDDQM1 LMIDQM1
C11
002:K4 LDDQS0 B10 LMIDQS0
002:K4 LDDQS1 LMIDQS1
A16
002:K4 LDCS C15 NOT_LMICS
002:K4 LDRAS NOT_LMIRAS
B15
002:K4 LDCAS A15 NOT_LMICAS
[EEPROM] 1V25 002:K4 LDWE LMIRDNOTWR
C6
002:K5 LDCLKE B6 LMICKEN
R124
002:K5 LDCLK A6 LMICLKOUT
120 A10 NOT_LMICLKOUT
LDD[0-15] 002:K5 LDCLKN
3V3 C101 LMIVREF
002:K3 B14
LDD[0] 0.01uF
LDD[1] GND A14 LMIDATA0
LMIDATA1
LDD[2] C13
LDD[3] B13 LMIDATA2
LMIDATA3
LDD[4] A13
LDD[5] C12 LMIDATA4
IC103 LMIDATA5
LDD[6] B12
24LC256-I/SM LDD[7] A12 LMIDATA6
LMIDATA7
LDD[8] A9
R193 A0 VCC LDD[9] B9 LMIDATA8
4.7K 1 8 LMIDATA9
LDD[10] C9
LDD[11] A8 LMIDATA10
R192 4.7K A1 WP LMIDATA11
2 7 LDD[12] B8
R196 LDD[13] C8 LMIDATA12
LMIDATA13
R195 4.7K A2 SCL 100 LDD[14] A7
3 6 I2C_SCL0 001:F9 LDD[15] B7 LMIDATA14
LMIDATA15
VSS SDA
4 5 I2C_SDA0 001:F9
R197
100
C203
0.1uF
16V
R136
005:I5 COMM_UART_TX
47
GND
005:I5 COMM_UART_RX
R137 47
EEPROM I2C ADDRESS : Default 0xAA CI_EN
003:B4;004:F4
005:D8 DTV_AUDIO_MUTE
004:A7
004:A8
I2C_SDA0
I2C_SCL0
I2C_SDA1
I2C_SCL1
FE_TS_DATA[0-7],FE_TS_DATA_CLK,FE_TS_DATA_VAL,FE_TS_DATA_SYN
3V3_CI
001:F8;004:F4
TS_SEL
IC300
74LVC541A(PW)
OE1 VCC
1 20
FE_TS_DATA[7] A0 OE2
2 19
GND
FE_TS_DATA[6] A1 3 18 Y0
TS_DATA[7] 001:K6;003:C8;003:E3
A2 Y1
FE_TS_DATA[5] 4 17
TS_DATA[6] 001:K6;003:C8;003:E3
A3 Y2
FE_TS_DATA[4] 5 16 TS_DATA[5] 001:K6;003:C8;003:E3 5.0V_CI
BUFFER 5.0V
A4 Y3
FE_TS_DATA[3] 6 15 TS_DATA[4] 001:K6;003:C8;003:E3
FE_TS_DATA[2] A5 7 14 Y4
TS_DATA[3] 001:K7;003:C8;003:E3
FE_TS_DATA[1] A6 8 13 Y5
TS_DATA[2] 001:K7;003:C8;003:E3 004:E2 R324
A7 Y6 CI_CD1 100
FE_TS_DATA[0] 9 12
TS_DATA[1] 001:K7;003:C8;003:E3
GND Y7
10 11 TS_DATA[0] 001:K7;003:C8;003:E3 AR303 GND
003:B8 33
CI_TS_DATA[4] 003:B8
4 5
CI_TS_DATA[5] 003:B8 3 6
CI_TS_DATA[6] 003:B8
2 7
CI_TS_DATA[7] 1 8 R306
10K
003:L4;004:E3
IC301 CI_IORD 003:L4
TC74LCX244FT CI_IOWR
AR304
FE_TS_DATA[0] 33
1OE VCC FE_TS_DATA[1] 4 5
1 20 FE_TS_DATA[2] 3 6
FE_TS_DATA[3] 2 7
1A1 2OE 1 8 C306
FE_TS_DATA_SYN 2 19
GND 33 AR305 0.1uF
FE_TS_DATA[4] GND
2Y4 1Y1
TS_DATA_SYN 3 18 TS_DATA_SYN FE_TS_DATA[5] 4 5
FE_TS_DATA[6] 3 6
FE_TS_DATA_VAL 1A2 4 17 2A4 FE_TS_DATA[7] 2 7
CI_TS_DATA_SYN 1 8 R304 10K
2Y3 1Y2 CI_RST 001:H8
TS_DATA_VAL 5 16 004:F3 R301 47
TS_DATA_VAL CI_WAIT
Buffer REG 003:I8 AR306
1A3 2A3 003:C7 33
FE_TS_DATA_CLK 6 15 CI_TS_DATA_VAL CI_TS_DATA_CLK
003:C7 4 5
CI_TS_DATA_VAL 003:C6 3 6
2Y2 1Y3 CI_TS_DATA_SYN
TS_DATA_CLK 7 14 TS_DATA_CLK 2 7
1 8
003:B8 AR307
1A4 8 13 2A2 CI_TS_DATA[0] 003:B8 4 33
CI_TS_DATA_CLK CI_TS_DATA[1] 5
003:B8 3 6
2Y1 1Y4 CI_TS_DATA[2] 003:B8 2
9 12 CI_TS_DATA[3] 7
FE_TS_DATA_CLK_BUF 1 8
GND 2A1
10 11 004:E2 R325 100
CI_CD2
5.0V
FE_TS_DATA_CLK
R305 10K
10K C313
R303
0.1uF
004:F4 TS_SEL_CI
IC302 AR308
74LVC541A(PW) 33 GND
1/16W
FE_TS_DATA_SYN
OE1 VCC FE_TS_DATA_VAL_AND_ERR
1 20
FE_TS_DATA_CLK_BUF
FE_TS_DATA_CLK_BUF
A0 OE2
003:E7 CI_TS_DATA[0] 2 19
GND
A1 3 18 Y0
003:E7 CI_TS_DATA[1] TS_DATA[0] 001:K6;003:C5;003:E3 GND
A2 4 17 Y1
003:E7 CI_TS_DATA[2] TS_DATA[1] 001:K6;003:C5;003:E3
R315
A3 Y2 FMICS1
CI_TS_DATA[3] 5 16 TS_DATA[2] 001:K6;003:C5;003:E3
003:E7
BUFFER
A4 Y3
003:E6 CI_TS_DATA[4] 6 15 TS_DATA[3] 001:K6;003:C5;003:E3 R316 47
IRQ1
A5 Y4
003:E6 CI_TS_DATA[5] 7 14 TS_DATA[4] 001:K7;003:C5;003:E3
A6 8 13 Y5
003:E6 CI_TS_DATA[6] TS_DATA[5] 001:K7;003:C5;003:E3
A7 Y6
9 12 TS_DATA[6] 001:K7;003:C6;003:E3
003:E6 CI_TS_DATA[7]
GND Y7
10 11 TS_DATA[7] 001:K7;003:C6;003:E3
GND
1.2VA
1.2V
R189
0
004:F4
10K
CPU_WAIT R144
47
R154 GND
FMIREQ
FMIGNT
GND
GND
R139
1.2VA
47
R140
47
JTAG
GND
GND
1.2VA
X100
32.768KHz
R155
GND
330K
2V5 1V2
1V2 3V3
W15
VDDRGB W14
VDDYCC
V15
GNDRGB W13
GNDYCC
W16
REXTVDACRGB
V13
REXTVDACYCC
V16
GNDREXTVDACRGB V14
GNDREXTVDACYCC
IC100
Y16
ROUT Y15
GOUT
Y14
BOUT Y12
YOUT
Y13
COUT W12
CVOUT
R17
LRCLK
U18
SCLK P17
PCMCLK N17
PCMDATA V18
SPDIF
Y20
OUTLEFT
STI5100GUC
W20
VBGOUT
Y19
OUTRIGHT
H20
CLK27IN G20
AUXCLKOUT
H19
CLK27OSC
Y1
TS0INDATA[7] Y2
TS0INPACKETCLK
Y4
TS0INBITCLKVALID Y5
TS0INBITCLK
Y3
TS0INERROR
V8
TS1INDATA[0] V7
TS1INDATA[1]
V6
TS1INDATA[2] W8
TS1INDATA[3]
W7
TS1INDATA[4] W6
TS1INDATA[5]
Y7
TS1INDATA[6] Y6
TS1INDATA[7] V9
TS1INPACKETCLK Y8
TS1INBYTECLKVLD Y9
TS1INBYTECLK W9
TS1INERROR
T4
TS2IODATA[0] U4
TS2IODATA[1]
U6
TS2IODATA[2] U7
TS2IODATA[3]
U9
TS2IODATA[4] U5
TS2IODATA[5]
U8
TS2IODATA[6] U10
TS2IODATA[7]
M4
TS2IOPACKETCLK P4
TS2IOBYTECLKVLD
R4
TS2IOBYTECLK N4
TS2IOERROR
R164 12K
GND
GND
R188 47
R185 47
TS_SEL
47
R123 R162
R186 DEBUG_UART_RX 004:F6;005:I5
PIO2B6 47 47
3V3 R163
R187 47 DEBUG_UART_TX 004:F7;005:I5
PIO2B7 47
R157 003:E6
004:C5 R150 47 47 CI_RST
004:C5 R151 47
003:I1 R152 47
003:I1 R153 47
CI OPTIONs(UK)
1OE
1A1
FMIGNT R309 47
2Y4
3V3_CI
R310 47 1A2
FMIREQ
2Y3
IC304
74LVC245A 1A3
R311 47
FMIOE
DIR VCC 2Y2
1 20
FMI_D[0] A0 2 19 OE R327 33 R312 47 1A4
CI_CS FMILBA
001:D3
A1 B0
FMI_D[1] 3 18 2Y1
A2 B1
FMI_D[2] 4 17 GND
FMI_D[3] A3 B2 GND
5 16
Bidirec(High:A->B)
FMI_D[4] A4 6 15 B3
GND
FMI_D[5] A5 7 14 B4
A6 B5
FMI_D[6] 8 13
A7 B6
FMI_D[7] 9 12
GND B7
10 11
3V3_CI
GND
IC305
AR313
1/16W 33 74LCX373MTCX_NL
CI_DATA[7]
CI_DATA[6] OE VCC
1 20
CI_DATA[5]
CI_DATA[4]
T_ADDR[0] O0 O7 GND
2 19 T_ADDR[7]
33
1/16W AR314
CI_DATA[3] FMIBE1 D0 D7
CI_DATA[2] 3 18 FMI_A[7]
CI_DATA[1]
CI_DATA[0] FMI_A[1] D1 D6 FMI_A[6]
4 17
CN300
T_ADDR[1] O1 5 16 O6 T_ADDR[6]
P300
91932-31169LF T_ADDR[2] O2 O5
74031-118CALF 6 15 T_ADDR[5]
36 35 18mm 1 1 FMI_A[2] D2 D5
37 GND3 GND1 2 CI_DATA[3] 7 14 FMI_A[5]
36 CD1 D3 2
38 37 3 3 CI_DATA[4]
D11/MDO3 D4 FMI_A[3] D3 D4
39 38 D12/MDO4 D5 4 4 CI_DATA[5] 8 13 FMI_A[4]
40 39 5 5 CI_DATA[6]
D13/MDO5 D6
41 40 D14/MDO6 D7 6 6 CI_DATA[7] T_ADDR[3] O3 9 12 O4 T_ADDR[4]
42 41 7 7 003:F8;003:I4;003:K3;003:K6;004:G4
D15/MDO7 CE1 CI_ADDR[10] CI_CS
43 42 CE2/EXT_CH A10 8 8
44 43 9 9 003:L3;004:E3 GND 10 11 LE
VS1 OE CI_ADDR[11] CI_OE
45 44 10 10
46 45 IORD/RFU A11 11 11 CI_ADDR[9] 5.0V
IOWR/RFU A9/DRX CI_ADDR[8]
47 46 12 12
48 47 A17/MISTRT A8/CRX 13 13 CI_ADDR[13]
A18/MDI0 A13 R319 10K
49 48 14 14 CI_ADDR[14]
50 49 A19/MDI1 A14 15 15 003:L3
A20/MDI2 WE R326 CI_WE
51 50 16 16 100 CI_IRQ 003:F8 3V3_CI
52 51 A21/MDI3 IREQ/READY 17 17
R308 VCC3.3V2 VCC3.3V1 R318 OPT
OPT 53 52 18 18
54 53 VPP/SW5V2 VPP1/SW5V1 19 19 C308
A22/MDI4 A16/MIVAL 0.1uF GND
55 54 20 20
56 55 A23/MDI5 A15/MCLKI 21 21 CI_ADDR[12]
A24/MDI6 A12 GND IC306
57 56 22 22 CI_ADDR[7]
58 57 A25/MDI7 A7/QTX 23 23 CI_ADDR[6] 74LCX373MTCX_NL
VS2/MCLKO A6/ETX
59 58 24 24 CI_ADDR[5]
60 59 RESET A5/ITX 25 25 CI_ADDR[4]
WAIT A4/CTX OE VCC
61 60 26 26 CI_ADDR[3] 1 20
62 61 INPACK A3 27 27 CI_ADDR[2]
REG A2 GND
63 62 28 28 CI_ADDR[1] O0 O7
64 63 MOVAL/BVD2 A1 29 29 CI_ADDR[0] T_ADDR[8] 2 19 T_ADDR[16]
MOSTRT/BVD1 A0
65 64 30 30 CI_DATA[0]
66 D8/MDO0 D0 31 CI_DATA[1] FMI_A[8] D0 D7 FMI_A[16]
65 D9/MDO1 D1 31 3 18
67 66 32 32 CI_DATA[2]
68 D10/MDO2 D2 33
67 CD2 IOIS16/WP 33 FMI_A[9] D1 4 17 D6 FMI_A[14]
69 68 34 34
GND4 GND2 35 AR309
G2 G1 33 O1 O6
1/16W T_ADDR[9] 5 16 T_ADDR[14]
CI_ADDR[0] T_ADDR[0]
70
CI_ADDR[1] T_ADDR[1] O2 O5
GND CI_ADDR[2] T_ADDR[2] T_ADDR[10] 6 15 T_ADDR[13]
CI_ADDR[3] T_ADDR[3]
GND FMI_A[10] D2 D5 FMI_A[13]
7 14
AR310
GND 1/16W 33 FMI_A[11] D3 8 13 D4 FMI_A[12]
CI_ADDR[4] T_ADDR[4]
CI_ADDR[5] T_ADDR[5] O3 O4
T_ADDR[11] 9 12 T_ADDR[12]
CI_ADDR[6] T_ADDR[6]
CI_ADDR[7] T_ADDR[7]
GND LE
10 11
AR311
33
1/16W
CI_ADDR[8] T_ADDR[8] GND
CI_ADDR[9]
T_ADDR[9]
CI_ADDR[10] T_ADDR[10]
CI_ADDR[11] T_ADDR[11]
FMIBE1,FMI_A[1-16]
AR312
33
1/16W 0 003:E7
47 CI_CS CI_ADDR[12] T_ADDR[12] REG
T_ADDR[16] R314
CI_ADDR[13] T_ADDR[13]
CI_ADDR[14] T_ADDR[14]
CI_IRQ
DDR TERMINATION OPTIONs
DDR Termination Power
1V25 VTT
1.2VA
GND
1.2V
L103 GND
GND V_SENSE
HH-1M3216-501
VREF
GND
3V3
L104
HH-1M3216-501
PDP 12.07 GND
GND
3V3
L105 ADAC_8V
1 HH-1M3216-501
L108
2 HH-1M3216-501
GND
GND
3.3V
L106
HH-1M3216-501
GND
R167
10K
R168
10K
L109
FI-C3216-103KJT
CVBS
005:D7
GND 1 2
GND
R177 LRCLK_DTV
R178 47
47 SCLK_DTV
R179
47 PCMDATA_DTV
R180 SPDIF_STI_OUT
47
C197
OUT_LEFT 005:H8
4.7uF 6.3V
C182
1uF 10V
GND
C198
4.7uF OUT_RIGHT 005:H9
R169 6.3V
0 C195
22pF
R170
0
C196
10pF
GND
001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;003:K5,001:C4;004:J4,001:C4;004:J4,001:C4;004:J4,001:C4;004:G2,001:C4;004:G2,001:C4,001:C4,001:C4,001:C4
TS_DATA[0] 003:C6;003:C8;003:E3
TS_DATA[1] 003:C6;003:C8;003:E3
TS_DATA[2] 003:C5;003:C8;003:E3 FMI_A[1-25]
TS_DATA[3] 003:C5;003:C8;003:E3
TS_DATA[4] 003:C5;003:C8;003:E3
TS_DATA[5] 003:C5;003:C8;003:E3
TS_DATA[6] 003:C5;003:C8;003:E3
TS_DATA[7] 003:C5;003:C8;003:E3
TS_DATA_SYN 003:B6;003:C6;003:E3
003:B6;003:C6;003:E3
TS_DATA_VAL
TS_DATA_CLK 003:B7;003:C7;003:E4
R175 10K
GND
AR110
47 656_D[0] 656_D[0-7]
5 TP125 656_D[1]
4 TP126
3 6 656_D[2]
7 TP127 656_D[3]
2 TP128
1 8
656_D[4]
4 5 TP129
TP130 656_D[5]
3 6 656_D[6]
2 7 TP131
TP132 656_D[7]
1 8 001:D3 FMIWE
47 AR111
001:B6 SYS_RST
R173 YUV_PIXCLK 005:I4
47
3V3_CI
C307 0.1uF
TP380
GND
IC303
CI_CS 003:F8;003:H6;003:I4;003:K6;004:G4
TC74LCX244FT
1 20 VCC
2OE
2 19
1Y1 R313
3 18 47 CI_OE
2A4
4 17
5 16 1Y2 R321 47
CI_WE
Buffer
2A3
6 15
1Y3
7 14 R322 47 CI_IORD
2A2
8 13
1Y4 R323 47
9 12 CI_IOWR
10 11 2A1
[SCART PIN8]
P_12V
2
FMIBE1,FMI_A[1-16] R416 R417
0 0 B
TP445
R414 C 3
001:F8 2
1K B Q401
PIO2B6 2SC3875S
E 1
TP446
R415 C 3
001:F8 2 B Q400
1K
PIO2B7 2SC3875S
E 1
TP447
GND
CI_LATCH
CI_CS
ST UART FOR DEBUG
OPT
C403
0.1uF 16V
ICL3232CBNZ
OPT
C404 C1+
0.1uF
C405 V+
0.1uF
OPT
C1-
C2+
OPT C406 C2-
0.1uF
C407 V-
0.1uF
OPT T2OUT
GND R2IN
VTT
R201
2V5 002:G3;002:J2 LD_D[0]
100
R202
002:G3;002:J2 LD_D[1] 100
R203
002:G3;002:J2 LD_D[2] 100 USE FOR VTT REPPLE USE FOR VTT REPPLE
R204
C208 C209 C212 C213 C216 C217
IC200 002:G3;002:J2 LD_D[3] 100 10uF 10uF 10uF 10uF 10uF 10uF
R205 16V 16V 16V 16V 16V 16V
SC2595STR 002:G3;002:J2 LD_D[4] 100
R206
002:G3;002:J3 LD_D[5] 100
NC 1 8 VTT R207 GND GND GND GND GND GND
002:G3;002:J3 LD_D[6] 100
PVCC R208
2 7
TP203 002:G3;002:J3 LD_D[7] VTT Decoupling Capacitors
R209 100
AVCC
3 6 002:H3;002:J3 LD_D[8]
R210 100
VDDQ 002:H3;002:J3 LD_D[9]
4 5 R211 100
C239 C238 C235 C241 C234 C240 C242 C236 C243 C237
002:H3;002:J3 LD_D[10]
R212 100 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
1
002:H3;002:J3 LD_D[11]
2 R213 100
002:H3;002:J3 LD_D[12]
100
R214
002:H3;002:J3 LD_D[13]
100
R215
002:H3;002:J3 LD_D[14]
100
R216
002:H3;002:J3 LD_D[15]
100
R217
002:G4;002:J1 LD_A[0]
100 002:C1;002:J2
R218
002:G4;002:J1 LD_A[1]
100
R219
002:G4;002:J1 LD_A[2] 002:C1;002:J2
100
R220 002:C1;002:J2
002:G5;002:J1 LD_A[3]
100
R221
002:H5;002:J2 LD_A[4]
100 002:C1;002:J2
R222
002:H4;002:J1 LD_A[5] 002:C1;002:J2
100
R223
002:H4;002:J1 LD_A[6]
100
R224 002:C1;002:J3
002:H4;002:J1 LD_A[7]
100 002:C2;002:J3
R225
002:H4;002:J2 LD_A[8]
100
R226 002:C2;002:J3
002:H4;002:J2 LD_A[9]
100
R227
002:G4;002:J1 LD_A[10]
100
R228
002:H4;002:J2 LD_A[11] 002:C4;002:J4 LD_DQS0
100
R229
002:H4;002:J2 LD_A[12]
100
R230
002:G4;002:J4 LD_BA0
100
R231
002:G4;002:J4 LD_BA1 002:C4;002:J4 LD_DQM0
100
R232
002:G4;002:J4 LD_DQS0 002:C4;002:J4
100
R233 002:C4;002:J4
002:G4;002:J4 LD_DQM0
100 002:C4;002:J4
R234
002:H4;002:J4 LD_DQS1 002:C4;002:J4
100
R235
002:H4;002:J4 LD_DQM1
100
R236 002:C3;002:J4
LD_WE
002:G4;002:J4 100 002:C3;002:J4
R237
002:G4;002:J4 LD_CAS 002:C3;002:J1 LD_A[10]
100
R238
002:G4;002:J4 LD_RAS 002:C2;002:J1
100
R239 002:C2;002:J1
002:G4;002:J4 LD_CS
100 002:C3;002:J1
002:C3;002:J1
R241
002:H4;002:J5 LD_CLKE
100
DDR SDRAM 16MB/32MB/64MB
READY
R240
002:H4;002:J5 LD_CLK
100
002:H4;002:J5 LD_CLKN
3V3
FMI_A[17]
IC201
MX29LV320CTTC-70G 001:C5;003:G4;004:I6,001:C5;003:G4;004:I6,001:C5;003:G4;004:I6,001:C5;003:G4;004:I6,001:C5;003:G4;004:I6,001:C5;003:G4;004:I6,001:C5;003:G4;004:I6,001:C5;003:G4;004:I6,001:C5;004:I6,001:C5;004:I6,001:C5;004:I6,001:C5;004:I6,001:C5;004:I6,001:C5;004:I6,001:C5;004:I6,001:C5;004:I6
FMI_D[0-15]
FMI_A[16] A15 1 48 A16
ST FLASH
FMI_A[15] A14 BYTE#
2 47
3V3 A13 GND_2
FMI_A[14] 3 46
A12 Q15/A-1 FMI_D[15]
FMI_A[13] 4 45
FMI_A[12] A11 5 44 Q7 FMI_D[7]
FMI_A[11] A10 Q14 FMI_D[14]
6 43
A9 Q6 FMI_D[6]
FMI_A[10] 7 42
FMI_A[9] A8 8 41 Q13 FMI_D[13]
FMI_A[20] A19 Q5 FMI_D[5]
9 40
A20 Q12 FMI_D[12]
FMI_A[21] 10 39
WE# Q4 FMI_D[4]
11 38
RESET# 12 37 VCC
FMI_A[22] NC Q11 FMI_D[11]
13 36
WP#/ACC Q3 FMI_D[3]
14 35
RY/BY# Q10 FMI_D[10]
15 34
FMI_A[19] A18 16 33 Q2 FMI_D[2]
FMI_A[18] A17 Q9 FMI_D[9]
17 32
A7 Q1 FMI_D[1]
FMI_A[8] 18 31
A6 Q8 FMI_D[8]
FMI_A[7] 19 30
FMI_A[6] A5 Q0 FMI_D[0]
20 29
A4 OE#
FMI_A[5] 21 28 FMIOE 001:D3;003:J4
A3 GND_1
FMI_A[4] 22 27
FMI_A[3] A2 23 26 CE#
FMICS3 001:D3
A1 A0
FMI_A[2] 24 25
GND
FMI_A[1]
BOOT FLASH 4MB/8MB
CI OPTIONs(UK)
3V3_CI
IC403
C409
74LVC32AD 0.1uF
16V
003:E5 1A 1 14 VCC
CI_CD1 GND
003:E7 1B 2 13 4A
CI_CD2
001:E2 1Y 4B
3 12
IRQ2
R421
47 2A 4Y
4 OR gate 11
2B 3B
5 10
2Y 6 9 3A
GND 3Y
7 8
GND
IC402 3V3_CI
TC74LCX08FT
1A VCC
003:H6;003:L3 1 14
CI_OE C410
16V
1B 4B
003:E6;003:L4 CI_IORD 2 13 0.1uF
1Y 4A GND
003:G3 D_T/R 3 12
2A 4 11 4Y
003:H6;003:L3 FE_TS_DATA_VAL AND GATE
2B 3B
TUNER_ERROR 5 10
47 2Y 3A
003:G3 6 9
R412
FE_TS_DATA_VAL_AND_ERR GND 3Y
7 8
GND
IC404
74LVC14APW 3V3_CI
1A VCC
003:E6 CI_WAIT 1 14
R413 C411
001:F2 47 1Y 2 13 6A 0.1uF
CPU_WAIT 16V
2A 6Y GND
3 12
INVERTER
2Y 5A
4 11
3
C 3A 5Y
Q402 5 10
2SC3875S
3Y 4A
E 1 013:C8 6 9 CI_CS 003:F8;003:H6;003:I4;003:K3;003:K6
REC_8 001:F8;003:B4 TS_SEL
GND 7 8 4Y
4.89V / 9.09V_120ohm(LOAD) CI_LATCH 003:K6
003:B7 TS_SEL_CI
5.19V / 10.91V_1Kohm(LOAD) GND
3.3V 3V3_CI
L400
HH-1M3216-501
C4121 C413 1 C415
C414
10uF 16V 10uF 0.1uF
2 0.1uF 2 16V 16V
16V
GND GND
OPTION
SPDIF OPTIC JACK
3V3_CI
CON400 OPTION
35337-0320
IC401 C408
0.1uF
OPT
OPT
1 J400
VCC
1 16 SPDIF
OPT GND 2
GND SPDIF_OUT GND GND
2 15 2 1
3
R456 OPT R437
3 14 T1OUT 22 INPUT GND
4 3
R1IN R455 OPT
4 13 GND Option for remote control 5V 6 5 GND
5.0V
R1OUT R419 OPT
5 12
DEBUG_UART_RX
PI4[1]
T1IN R420 OPT STi5100
6 11 DEBUG_UART_TX PI4[0]
T2IN
7 10 IF YOU WANT TO USE CN401, R449,R450 -> 0 Ohm ADD
R543,R544 -> DELETE
8 9 R2OUT
TP442
GND
R242
LDA[10]
002:C3;002:G4 LD_A[10]
22
AR200
22
1/16W
002:C3;002:G5 LD_A[3] LDA[3]
LDA[2]
002:C3;002:G4 LD_A[2]
002:C2;002:G4 LD_A[1] LDA[1]
LDA[0]
002:C2;002:G4 LD_A[0]
AR201
2V5 1/16W 22
002:C3;002:H4 LD_A[7] LDA[7]
LDA[6]
002:C3;002:H4 LD_A[6]
002:C3;002:H4 LD_A[5] LDA[5]
LDA[4]
002:C3;002:H5 LD_A[4]
AR202
22
1/16W
LDA[12]
002:C3;002:H4 LD_A[12] LDA[11]
002:C3;002:H4 LD_A[11]
GND LDA[9]
002:C3;002:H4 LD_A[9] LDA[8]
002:C3;002:H4 LD_A[8]
001:C6
LDA[0-12]
AR203
22
1/16W
002:C1;002:G3 LD_D[0] LDD[0]
LDD[1]
002:C1;002:G3 LD_D[1]
002:C1;002:G3 LD_D[2] LDD[2]
LDD[3]
002:C1;002:G3 LD_D[3]
AR204
22
IC202 1/16W
2V5 2V5 LDD[7]
002:C2;002:G3 LD_D[7] LDD[6]
HYB25D256160CE-5 002:C2;002:G3 LD_D[6]
LDD[5]
002:C1;002:G3 LD_D[5] LDD[4]
002:C1;002:G3 LD_D[4]
VDD_1 VSS_3
1 66 AR205
DQ0 DQ15
LD_D[0] 2 65 LD_D[15] 002:C2;002:J3 22
VDDQ_1 VSSQ_5 1/16W
3 64 LDD[11]
002:C2;002:H3 LD_D[11] LDD[10]
DQ1 4 63 DQ14 002:C2;002:H3 LD_D[10]
LD_D[1] LD_D[14] 002:C2;002:J3 LDD[9]
DQ2 DQ13 002:C2;002:H3 LD_D[9] LDD[8]
LD_D[2] 5 62 LD_D[13] 002:C2;002:J3 002:C2;002:H3 LD_D[8]
VSSQ_1 VDDQ_5
6 61
DQ3 DQ12 AR206
7 60
LD_D[3] LD_D[12] 002:C2;002:J3 22
DQ4 8 59 DQ11 1/16W
LD_D[4] LD_D[11] 002:C2;002:J3 LDD[12]
VDDQ_2 VSSQ_4 002:C2;002:H3 LD_D[12] LDD[13]
9 58 002:C2;002:H3 LD_D[13]
DQ5 DQ10 LDD[14]
LD_D[5] 10 57 LD_D[10] 002:C2;002:J3 002:C2;002:H3 LD_D[14] LDD[15]
002:C2;002:H3 LD_D[15]
DQ6 11 56 DQ9
LD_D[6] LD_D[9] 002:C2;002:J3
VSSQ_2 VDDQ_4
12 55
DQ7 DQ8
LD_D[7] 13 54 LD_D[8] 002:C2;002:J3
NC_1 NC_8
14 53
VDDQ_3 15 52 VSSQ_3
1V25 R243
LDQS UDQS 002:C3;002:G4 LD_BA0
16 51 LD_DQS1 002:C4;002:J4
NC_2/A13 NC_7 22
17 50 R244
VDD_2 VREF
18 49 002:C3;002:G4 LD_BA1
22
NC_3 19 48 VSS_2
R245
LDM UDM 002:C4;002:G4 LD_DQS0
20 47 LD_DQM1 002:C4;002:J4 22
WE CK R246
LD_WE 21 46 LD_CLKN 002:D5;002:J5 002:C4;002:G4 LD_DQM0
GND 22
CAS 22 45 CK R247
LD_CAS LD_CLK 002:C4;002:J5 002:C4;002:H4 LD_DQM1
RAS CKE 22
LD_RAS 23 44 LD_CLKE 002:D5;002:J5 R248
CS0 NC_6
LD_CS 24 43 002:C4;002:H4 LD_DQS1 22
NC_4 NC_5/A12
25 42 002:C3;002:J2
LD_A[12] R260 22
BA0 26 41 A11 002:C4;002:G4 LD_CS
LD_BA0 LD_A[11] 002:C3;002:J2
BA1 A9 R257 22
LD_BA1 27 40 LD_A[9] 002:C3;002:J2 002:C4;002:G4 LD_RAS
A10/AP A8
28 39 LD_A[8] 002:C3;002:J2 R259 22
A0 A7 002:C4;002:G4 LD_CAS
29 38 002:C3;002:J1
LD_A[0] LD_A[7] R258 22
A1 30 37 A6 002:C4;002:G4 LD_WE
LD_A[1] LD_A[6] 002:C3;002:J1
A2 A5
LD_A[2] 31 36 LD_A[5] 002:C3;002:J1
A3 A4 R249
LD_A[3] 32 35 LD_A[4] 002:C3;002:J2 002:C4;002:H4 LD_CLK
VDD_3 VSS_1
33 34 22
R250
002:D5;002:H4 LD_CLKN
22
GND
R251
002:D5;002:H4 LD_CLKE
22
R256
10K
GND
DDR Series Resistors
FAN OPTION
FAN
IC406
KIA78R09F
6
C424
1 2 3 4 5 FAN_VCC
0.1uF
C425 100 FAN_1EA
FAN_VCC 47uF R431
FAN 16V
C417 1 C419 FAN
47uF FAN_ALARM FAN_1EA
0.1uF 16V FAN_1EA
2
FAN FAN
FAN
R423
100
9V_ON
R427
4.7K
FAN
IC405
KIA78R09F
FAN
6 C422 D401 EU1ZV(1)
0.1uF R429 10
1 2 3 4 5 FAN_FULL HD
FAN C423
47uF
16V
FAN_PDP
FAN
R429-*1
18
C416 C418
0.1uF 47uF
16V
FAN FAN
FAN L402
R424 HH-1M3216-501
100
FAN_VCC
8V_ON FAN_FULL_HD
L412
HH-1M3216-501
5.0V
FAN_FULL_HD
L401 FAN_FULL_HD
HH-1M3216-501
C439
FAN_FULL_HD
FAN_ALARM
R400 100
FAN P_3.3V C436
IC407 FAN_FULL_HD READY
LM75
LM75CIMX-3
FAN
R425
100
SDA 1 SDA +VS 8
FAN
R426
SCL 100 2 SCL A0 7 0.1uF
C427
FOR ONLY USE 60"PDP(PY3 Tool)
FAN 3 FAN
C420 OS A1 6
C421
READY READY R430
4 5
GND A2 10K
TP437
I2S SWITCHING (DTV&HDMI)
P_3.3V
IC410
TC74LCX157FT
3_STATE_BUFFER
R438 0 SEL VCC
1 16
SPDIF_STI_OUT
1A LOW ST
2 15
SPDIF_MSP_OUT
1B 3 HIGH 14 4A PCMDATA_DTV
R441 100 4B TO MSP
1Y 4 13 HDMI_LRCH
SPDIF_OUT
C435
READY 2A 4Y R446 100
LRCLK_DTV 5 12 PCMDATA_MUX
C434
READY
2B 3A
HDMI_LRCK 6 11 SCLK_DTV
R439 100
LRCLK_MUX 2Y 7 10 3B HDMI_SCK
C432 R448 100
GND 8 9 3Y SCLK_MUX
READY
C433
READY
001:D7
LDD[0-15]
LDBA0001:D6
LDBA1001:D6
LDDQS0 001:D6
LDDQM0001:D6
LDDQM1001:D6
LDDQS1 001:D6
LDCS 001:D6
LDRAS001:D6
LDCAS001:D7
LDWE 001:D7
LDCLK001:D7
LDCLKN 001:D7
LDCLKE 001:D7
FAN_1EA
P400
GIL-G-03-S3T2
L406
1
R432
12K L407
2
R433 JP402
10K 3
C438
READY JP411
L411
P402
SMW200-08
JP408
FAN_FULL_HD
1
2
JP410
3
4
5
JP406 6
L403
7
FAN_FULL_HD JP404
8
JP409
FAN_FULL_HD
L405