Sanyo DVD-SL25 Service Manual page 30

IC BLOCK DIAGRAM & DESCRIPTION
IC822 K4S161622D-TC80(512K x 16bit x 2 Bank Synchronous DRAM)
Bank Select
CLK
35
20~24,
ADD
27~32
LCKE
LRAS
35 34
CLK CKE
Pin
CLK System Clock
CS Chip Select
CKE Clock Enable
Address
A - A AP
0 10/
Bank Select Address
BA
Row Address Strobe
RAS
Column Address Strobe
CAS
Write Enable
WE
Data Input/Output Mask
L(U)DQM
DQ - Data Input/Output
0 15
V /V Power Supply/Ground
DD SS
V /V Dsta Output Power/Ground
DDQ SSQ
No Connection/
N.C/RFU
Reserved for Furure Use
LCBR LWE
LCAS
Timing Register
18 17 16
CS RAS CAS
NAME
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK,CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latchea column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Mskes data output Hi-Z, I
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
Data Input Register
512K x 16
512K x 16
Column Decoder
Latency & Borst Length
Programming Register
LWCBR
15 36
WE L(U)DQM
Input Function
- RA , Column address : CA
0 10 0
sfter the clock and masks the output.
SHZ
- 29 -
LWE
14 LDQM
2,3,5,6,7,8,9,11,
12,39,40,42,43,
45,46,48,49
LDQM
- CA
7
DQ1