NAD T 741 Service Manual page 32

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AC3 BOARD
U104, U109, U116, U134: NJM5532
U131: NJM4558D
AMPLIFIER 1
OUTPUT
1
INVERTING
2
INPUT
– +
NON-INVERTING
3
INPUT
4
V –
AC3 BOARD
U105: CS4926
CMPDAT,
27
SDATAN2
Compressed
CMPCLK,
Data Input
28
SCLKN2
Interface
CMPREQ,
29
LRCLKN2
SCLKN1,
25
STCCLK2
LRCLKN1
26
22
SDATAN1
30
CLK1N
CLKSEL
31
32
FILT2
AC3 BOARD
U106, U107: 74HC574
D0
CP
OE
AMPLIFIER 2
8
V +
7
OUTPUT
+ –
INVERTING
6
INPUT
NON-INVERTING
5
INPUT
DATA7-0,
EMAD7-0,
RESET
CS
GPIO7-0
36
8-11,14-17
18
Framer
Shifter
Input
Buffer
Controller
Digital
Audio
Input
RAM Input
Interface
Buffer
PLL
Clock Manager
33
34
35
FILT1
VA
AGND
D1
D
Q
D
Q
CP
CP
FF1
FF2
Q0
AC3 BOARD
U108: AT27C020-70
V
(32)
CC
GND(16)
VPP(1)
OE(24)
CE(22)
PGM(31)
A0-A17
ADDRESS
INPUTS
(2-12, 25-30)
RD,
WR,
SCDIO,
R/W,
DS,
SCDOUT,
A0,
EMOE,
EMWR,
PSEL,
SCCLK
GPIO11
GPIO10
GPIO9
5
4
19
Parallel or Serial Host Interface
24-Bit
DSP Processing
RAM
RAM
Program
Program
Memory
Memory
RAM
RAM
Program
Program
Memory
Memory
STC
2 13 24
1 12 23
DGND[1-3] VD[1-3]
D2 to D5
D6
D
CP
Q1
44
OE, CE AND
PROGRAM LOGIC
Y DECODER
X DECODER
A1,
ABOOT,
EXTMEM,
SCDIN
INTREQ
GPIO8
7
6
20
21
Output
RAM
Formatter
Output
Buffer
D7
Q
D
Q
CP
FF7
FF8
Q6
Q7
DATA OUTPUTS
O0-O7
(13-15, 17-21)
OUTPUT
BUFFERS
Y-GATING
CELL MATRIX
IDENTIFICATION
37
DD
38
DC
44
MCLK
43
SCLK
42
LRCLK
41
AUDATA0
40
AUDATA1
39
AUDATA2
3
XMT958

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