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Artesyn PmPPC440 User Manual

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PmPPC440
PowerPC-Based Processor PMC Module
User's Manual
April 2005

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  • Page 1 PmPPC440 PowerPC-Based Processor PMC Module User’s Manual April 2005...
  • Page 2 Artesyn Communication Products 8310 Excelsior Dr. Madison, WI 53717 Web Site: www.artesyncp.com Sales: (800) 356-9602 Technical Support: (800) 327-1251 PmPPC440 User’s Manual—Artesyn Part Number: 10003794-05...
  • Page 3 PmPPC440 PowerPC-Based Processor PMC Module User’s Manual April 2005...
  • Page 4 PRODUCTS DOES NOT ASSUME ANY LIABILITY ARISING OUT OF USE OR OTHER APPLICATION OF ANY PRODUCT, CIRCUIT, OR PROGRAM DESCRIBED HEREIN. This document does not convey any license under Artesyn Communica- tion Products patents or the rights of others. Artesyn and the Artesyn logo are registered trademarks of Artesyn Technologies and are used by Artesyn Communication Products under licence from Artesyn Technologies.
  • Page 5 Regulatory Agency Warnings & Notices The Artesyn PmPPC440 meets the requirements set forth by the Federal Communications Commission (FCC) in Title 47 of the Code of Federal Regulations. The following informa- tion is provided as required by this agency. This device complies with part 15 of the FCC Rules. Operation is subject to the following...
  • Page 6 Artesyn Technologies Communication Products Division Manufacturer’s Address: 8310 Excelsior Drive Madison, Wisconsin 53717 Manufacturer’s Artesyn CP Scandinavia AB Authorized Representative Isafjordsgatan 22,b 5tr within the EU/EEA: SE-164 40 Kista, Sweden (Hans Öhman) Declares that the following product, in accordance with the requirements...

  • Page 7: Table Of Contents

    2.2 PmPPC440 Circuit Board ........
  • Page 8 8.1.4 Auto-booting ............8-2 PmPPC440: Contents...
  • Page 9 8.1.5 Flash Programming ..........8-2 8.2 Basic Operation .
  • Page 10 8.15.2 Motorola S-Record ..........8-25 PmPPC440: Contents...
  • Page 11 DMC Location on PmPPC440 ........
  • Page 12 DMC Jumper ..........7-10 PmPPC440: Contents...
  • Page 13 Tables Table 1-1. Regulatory Agency Compliance..........1-4 Table 1-2.
  • Page 14 PmPPC440: Contents...

  • Page 15: Overview

    Overview The Artesyn PmPPC440 module is a Processor PCI Mezzanine Card (PPMC) based ® on the IBM PowerPC 440GP Embedded Processor. It functions as a complete, low-power, processor subsystem that can operate in both PPMC Monarch and non-Monarch modes. The PmPPC440 supports various memory configurations, user flash memory, up to two serial ports, two 10/100BaseTX Ethernet ports, and an optional Development Mezzanine Card (DMC).
  • Page 16 The PmPPC440 supports a Peripheral Component Interconnect (PCI) / PCI-X bus that can operate at 33/66/133 MHz with a 32- or 64-bit data path. The PmPPC440 can function as a local PCI host (Monarch) or as a peripheral (non-Monarch). The Development Mezzanine Card (DMC) is a custom, optional, plug-on card that mounts on the back of the PmPPC440.

  • Page 17: Functional Overview

    Functional Overview 1.2 Functional Overview The following block diagram provides a functional overview for the PmPPC440: Serial Port Ethernet Ethernet LEDs Reset Switch Development Mezzanine Card (DMC) Programming LEDs Header Socket Jumpers Header 3.3V Power 2.5V Monitor 1.8V CPLD RS-232...

  • Page 18: Additional Information

    PmPPC440 hardware’s ability to comply with any of the stated specifications. The UL web site at http://www.ul.com has a list of Artesyn’s UL certifications. To find the list, search in the online certifications directory using Artesyn’s UL file number, E190079.

  • Page 19: Terminology And Notation

    Additional Information well as a list for products shipped to Canada. To find the PmPPC440, search in the list for 10003548-xx, where xx changes with each revision of the printed cir- cuit board. 1.3.2 Terminology and Notation Active low signals An active low signal is indicated with an asterisk * after the signal name.
  • Page 20 1. Frequently, the most current information regarding addenda/errata for specific documents may be found on the corresponding web site. If you have questions, please call an Artesyn Product Support Services representa- tive at 1-800-327-1251, visit the web site at http://www.artesyncp.com, or send e-mail to support@artesyncp.com.

  • Page 21: Setup

    2.1 Electrostatic Discharge Before you begin the setup process, please remember that electrostatic discharge (ESD) can easily damage the components on the PmPPC440 hardware. Electronic devices, especially those with programmable parts, are susceptible to ESD, which can result in operational failure. Unless you ground yourself properly, static charges can accumulate in your body and cause ESD damage when you touch the board.

  • Page 22: Pmppc440 Circuit Board

    PmPPC440: Setup 2.2 PmPPC440 Circuit Board The PmPPC440 circuit board is a PCI Mezzanine Card (PMC) assembly. It uses a 12-layer printed circuit board with the following dimensions: Table 2-1. Circuit Board Dimensions Width Length Height 2.9 in. 5.9 in.

  • Page 23: Figure 2-2. Component Map, Top (Rev. 02)

    PmPPC440 Circuit Board EIA-232 Mini-USB Ethernet Ethernet RJ45 RJ45 Strata- Strata- Strata- Strata- Flash Flash Flash Flash SO-DIMM PPC440GP Processor P11 – PMC Connector P13 – PMC Connector P12 – PMC Connector P14 – PMC Connector Figure 2-2. Component Map, Top (Rev. 02)

  • Page 24: Figure 2-3. Component Map, Bottom (Rev. 02)

    PmPPC440: Setup P1 – DMC Connector MSC PLD Figure 2-3. Component Map, Bottom (Rev. 02) April 2005...

  • Page 25: Identification Numbers

    PmPPC440 Circuit Board 2.2.1 Identification Numbers Before you install the PmPPC440 circuit board in a system, you should record the following information: ❑ The board serial number:_____________________________________ . The board serial number appears on a bar code sticker located on the back of the board.

  • Page 26: Pmppc440 Setup

    PmPPC440: Setup 2.3 PmPPC440 Setup You need the following items to set up and check the operation of the Artesyn PmPPC440. ❑ Artesyn PmPPC440 board ❑ Compatible baseboard host ❑ Card cage and power supply ❑ Serial interface cable (EIA-232) ❑...

  • Page 27: Installing The Module

    PmPPC440 Setup 2.3.3 Installing the Module PMC-compatible baseboards have one or two sets of four connectors (J11–J14 and J21–J24), as defined by the PMC specification. Fig. 2-4 shows the location of these connectors on a typical cPCI baseboard. cPCI Baseboard PMC Module Figure 2-4.

  • Page 28: Figure 2-6. Installing The Module

    PmPPC440: Setup The following procedure describes how to attach the PmPPC440 module to an Artesyn VME baseboard (see Fig. 2-6). For installation on a cPCI baseboard, the procedure would be similar. 1. Remove the screws from the standoffs on the PMC module.

  • Page 29: Resets

    Resets 2.4 Resets The PmPPC440 has several sources for resets. The power-on sequence, the front panel reset switch, and a PCI reset all perform a hard reset to the entire board. Also, a software-controlled Reset Command register at C100,0008 allows for...

  • Page 30: Led Control

    Register Map 2-4. LED 2.6 Monarch Functionality The PmPPC440 can function as either a Monarch or a non-Monarch module, as described in the VITA 32 PPMC draft specification. A Monarch is the main PPMC device on the local PCI bus. It performs enumeration on that bus after power-up and is often the interrupt handler.

  • Page 31: Board Configuration

    Please see the draft PPMC standard (reference in Table 1-2) for carrier board pull-up requirements. 2.7 Board Configuration The PmPPC440 has a register that provides configuration information about the board. The read-only Board Configuration register at C100,0020 identifies whether or not the board is a Monarch and whether or not it boots from the...

  • Page 32: Troubleshooting

    2.8 Troubleshooting In case of difficulty, use this checklist: ❑ Be sure the PmPPC440 circuit board is seated firmly in the card cage. ❑ Be sure the system is not overheating. ❑ Check the cables and connectors to be certain they are secure.

  • Page 33: Service Information

    Troubleshooting 2-13 2.8.2 Service Information If you plan to return the board to Artesyn Communication Products for service, call 1-800-327-1251 and ask for our Test Services Department (or send e-mail to serviceinfo@artesyncp.com) to obtain a Return Merchandise Authorization (RMA) number. We will ask you to list which items you are returning and the board serial number, plus your purchase order number and billing information if your PmPPC440 hardware is out of warranty.
  • Page 34 2-14 PmPPC440: Setup April 2005...

  • Page 35: Ppc440Gp Processor

    PPC440GP Processor The PmPPC440 uses an IBM PPC440GP central processing unit (CPU), which has a 32-bit reduced instruction set computer (RISC) embedded processor. The pro- cessor runs at 400MHz and features debug facilities, timer facilities, and 32-kilo- byte instruction and data caches. The PPC440GP has a 128-bit processor local bus (PLB), a 32-bit on-chip peripheral bus (OPB), a 32-bit device control register (DCR) bus.

  • Page 36: Physical Memory Map

    The following block diagram provides an overview of the PPC440GP architecture: PPC440 Processor Core Figure 3-1. PPC440GP Block Diagram 3.2 Physical Memory Map The PmPPC440 monitor (see Chapter 8) configures the memory map for the PPC440GP processor. The following figure shows the PmPPC440 physical mem- ory map: April 2005...

  • Page 37: Figure 3-2. Ppc440Gp Memory Map

    Physical Memory Map 32-Bit Hex Address: FFFF,FFFF Boot Area (256MB) F000,0000 Reserved E900,0000 DMC ROM Socket (1MB) E800,0000 Reserved E000,0000 FLASH (up to 256MB) D000,0000 Reserved C200,2000 Internal SRAM (8KB) C200,0000 Reserved C000,0A00 C110,0001 EMAC1 C000,0900 CPLD Registers EMAC0 C000,0800 C100,0000 ZMII Reserved...

  • Page 38: On-Card Memory

    SO-DIMM SDRAM (up to 1GB) 3.3.2 3.3 On-Card Memory The PmPPC440 has various types of on-card memory to support the PPC440GP. It has user Flash, SDRAM for data storage, and two serial EEPROMs for non-volatile memory storage. The following subsections describe these memory devices.

  • Page 39: Sdram

    On-Card Memory 3.3.2 SDRAM The PmPPC440 supports 16, 128, 256, and 512 megabytes of 72-bit wide synchro- nous dynamic random access memory (SDRAM). The PmPPC440 also will sup- port one gigabyte of SDRAM (when the 1-gigabyte devices become available). The SDRAM interface implements eight additional bits to allow for error correcting code (ECC).

  • Page 40: Serial I/O

    3.5 Ethernet The PPC440GP provides two reduced media independent interface (RMII) con- nections to support two optional 10/100BaseTX Ethernet ports on the PmPPC440 front panel (see Table 6-2 for pin assignments). The optional Ethernet signals also route to the P14 PMC connector (see Table 5-2 for pin assignments). Please refer to Chapter 6 for additional information about the Ethernet interface.

  • Page 41: Miscellaneous Status Register

    Miscellaneous Status Register 3.7 Miscellaneous Status Register The PmPPC440 has a read-only Miscellaneous Status register at C100,002C that allows software to monitor the status of the wait signal from the flash and the system error signal from the PPC440GP. Bit one monitors the GP440_SYSERR sig- nal, and bit zero monitors the FLASH_WAIT signal.
  • Page 42 PmPPC440: PPC440GP Processor April 2005...

  • Page 43: Real-Time Clock

    Real-Time Clock The standard real-time clock (RTC) for the PmPPC440 is provided by an M41T00 device from STMicroelectronics. This device has an integrated year-2000-compat- ible RTC, power sense circuitry, and uses eight bytes of non-volatile RAM for the clock/calendar function. The M41T00 is powered from the +3.3 V rail during nor- mal operation.

  • Page 44: Operation

    PmPPC440: Real-Time Clock 4.2 Operation The M41T00 clock operates as a slave device on the serial bus. To obtain access, the RTC implements a start condition followed by the correct slave address ). Access the eight bytes in the following order: 1.

  • Page 45: Table 4-1. Rtc Register Map

    Clock Operation Table 4-1. RTC Register Map Address Data Function/Range BCD Format 10 Seconds Seconds Seconds 00–59 10 Minutes Minutes Minutes 00–59 10 Hours Hours Century/Hours 0-1/00-23 01–07 10 Date Date Date 01–31 10 M Month Month 01–12 10 Years Years Years 00–99...
  • Page 46 PmPPC440: Real-Time Clock Calibration Calibration bits. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage. The number of times pulses are blanked (subtracted, negative calibration) or split (added, posi- tive calibration) depends on this five-bit byte. Adding counts accelerates the clock, and subtracting counts slows the clock down.

  • Page 47: Pci/Pci-X Interface

    PCI enumeration status and con- trol. If the PmPPC440 is a Monarch, the register is read only (1 = ready for enu- meration, 0 = not ready for enumeration). If it is not a Monarch, the register is writable (0 = PMC not ready for enumeration [default], 1 = PMC is ready for enu- meration).

  • Page 48: Pci Bus Control Signals

    ACK64*, REQ64* These output signals are used to tell a 64-bit PCI device whether to use the 64-bit or the 32-bit data width. Since the PmPPC440 is a 64-bit board, these signals are tied off to indicate the 64-bit data width.
  • Page 49 ENABLE 66MHZ. When grounded, this signal prevents 66MHz operation of the PCI bus. MONARCH* MONARCH. When this signal is grounded, it indicates that the PmPPC440 is a Monarch and must provide PCI bus enumeration and interrupt handling. LOCK* LOCK. This sustained three-state signal indicates that an automatic oper- ation may require multiple transactions to complete.

  • Page 50: Additional Pmc Signals

    PmPPC440: PCI/PCI-X Interface REQ* REQUEST. This output pin indicates to the arbiter that a particular mas- ter wants to use the bus. RST* RESET. The assertion of this input line brings PCI registers, sequencers, and signals to a consistent state.

  • Page 51: Pmc Connector Pin Assignments

    PMC Connector Pin Assignments 5.5 PMC Connector Pin Assignments The PmPPC440 has four 64-pin PMC connectors. Table 5-1 shows the pin assign- ments for P11, P12, and P13. Table 5-1. PMC Connector Pin Assignments, P11–P13 ISP_TCK no connection no connection...

  • Page 52: Table 5-2. Pmc Connector Pin Assignments, P14

    PmPPC440: PCI/PCI-X Interface Table 5-2 shows the pin assignments for P14. Table 5-2. PMC Connector Pin Assignments, P14 440GP I C SDA no connection 440GP I C SCL no connection Serial1 TxData no connection Serial1 RxData no connection Serial2 TxData...

  • Page 53: Ethernet Interface

    Ethernet Interface The PPC440GP processor provides an Ethernet interface that supports two 10/ 100BaseTX Ethernet ports for the PmPPC440. The interface uses two Broadcom BCM5221 PHY transceivers to provide two isolated Ethernet ports to the front panel or two non-isolated ports to the P14 PMC connector.

  • Page 54: Ethernet Addresses

    00 80 F9 69 0X XX or 00 80 F9 69 8X XX 00 80 F9 is Artesyn’s identifier. 69 is the identifier for the PmPPC440 product group. The last two pairs of hex numbers correspond to the following formula: n –...

  • Page 55: Front Panel Ethernet Connectors

    Front Panel Ethernet Connectors 6.3 Front Panel Ethernet Connectors The PmPPC440 has two, optional, RJ45, Ethernet connectors located on the front panel. The pinouts for these connectors are as follows: Table 6-2. Ethernet Pin Assignments, P3 & P4 Signal Signal RX–...
  • Page 56 PmPPC440: Ethernet Interface April 2005...

  • Page 57: Development Mezzanine Card

    Development Mezzanine Card The development mezzanine card (DMC) is an optional plug-on card mounted on the front of the PmPPC440 board to expedite product development. This chapter describes the physical layout of the DMC, the setup process, and how to check for proper operation once the board has been installed.

  • Page 58: Serial Numbers

    PmPPC440: Development Mezzanine Card Mini-USB RJ45 RJ45 CPLD JTAG 10002939-00 COPYRIGHT 2002 TECHNOLOGIES 10002939-00 Figure 7-1. DMC Component Maps, Top and Bottom (Rev. 01) 7.1.1 Serial Numbers Before you install the DMC in a system, you should record the following infor- mation: ❑...

  • Page 59: Connectors

    7.2.1 DMC Connector Pin Assignments Connector P1 is an 80-pin connector that routes memory, CPLD, CPU, and Ether- net signals from the PmPPC440 to the DMC. Table 7-2 shows the pin assign- ments. Table 7-2. DMC Connector Pin Assignments, P1...

  • Page 60: Table 7-2. Dmc Connector Pin Assignments, P1

    PmPPC440: Development Mezzanine Card Table 7-2. DMC Connector Pin Assignments, P1 — Continued Signal Signal LA16 no connection LA15 LA14 BOOT_SRC LA13 LA12 LA11 LED1* LA10 LED2* LED3* LED4* CPU_TDO CPU_TDI CPU_TRST* CPU_TMS no connection no connection BADDR2 no connection...
  • Page 61 CPU Test Clock is an output from DMC and part of CPU JTAG interface. BOOT_SRC Boot source is an output from DMC and indicates to the PmPPC440 whether to boot from the DMC socketed Flash or the PmPPC440 sol- dered Flash.

  • Page 62: Eia-232 Interface (Unused)

    PmPPC440: Development Mezzanine Card CPLD_TMS PLD Test Mode Select is an output from DMC and part of PLD JTAG interface. CPLD_TDO PLD Test Data Out is an input to DMC and part of PLD JTAG interface. DMC_DETECT DMC Presence Detect is an output from DMC and indicates to the PMC that the DMC is installed.

  • Page 63: Jtag/Cop Interface

    Connectors 7.2.3 JTAG/COP Interface The JTAG/COP interface provides for boundary-scan testing of the CPU and the PmPPC440. This interface is compliant with the IEEE 1149.1 standard. Table 7-4. DMC JTAG/COP Connector Pin Assignments, P3 Signal Signal no connection no connection...

  • Page 64: Jtag Chain Header

    PmPPC440: Development Mezzanine Card 7.2.4 JTAG Chain Header This header allows access to the CPLD programming interface. Table 7-5. DMC JTAG Chain Header Pin Assignments, P4 Signal Signal no connection no connection no connection Fused 3.3 V Test Clock Input. This is the clock input to the boundary scan test (BST) circuitry.

  • Page 65: Ethernet Ports (Unused)

    Connectors 7.2.5 Ethernet Ports (Unused) P5 and P6 are RJ45 connectors that allow for 10/100BASE-T Fast Ethernet access. Table 7-6. DMC Ethernet Port Pin Assignments, P5–P6 Signal Signal TD_P no connection TD_N no connection RD_P no connection no connection no connection no connection RD_N TD_P...

  • Page 66: Dmc Jumpers

    JP2 (pins 3 and 4) selects the 8-bit ROM socket as the boot device. In order for the socket to provide boot code, the DMC must be seated on the PmPPC440 and the boot jumper must be in place. This is a user-defined jumper.

  • Page 67: Debug/Status Leds

    Fig. 7-1 for LED locations. These LEDs are controlled by the PPC440GP through its general-purpose input/output bits, GPIO[31:28]. 7.5 DMC Setup You need the following items to set up and check the operation of the Artesyn DMC. ❑ A compatible PPMC board, such as the Artesyn PmPPC440 ❑...

  • Page 68: Installing The Dmc Card

    7-12 PmPPC440: Development Mezzanine Card 7.5.1 Installing the DMC Card Use the following procedure to attach the DMC to the PmPPC440 (see Fig. 7-8 for DMC location): 1. Remove the protective vinyl caps from the screws. 2. Line up the screws with the threaded holes on the bezel from the bottom side of the PmPPC440.

  • Page 69: Troubleshooting

    7.6 Troubleshooting In case of difficulty, use this checklist: ❑ Be sure the PmPPC440 module is seated firmly on the PMC and that the PMC host is seated firmly in the card cage. ❑ Verify the boot jumper and Ethernet (ENET) settings (see Fig. 7-7).
  • Page 70 7-14 PmPPC440: Development Mezzanine Card Artesyn Communication Products Test Services Department 8310 Excelsior Drive Madison, WI 53717 RMA #____________ Please put the RMA number on the outside of the package so we can handle your problem efficiently. Our service department cannot accept material received without an RMA number.

  • Page 71: Monitor

    Monitor The PmPPC440 monitor is based on the Embedded PowerPC Linux Boot Project (PPCBoot) boot program, available under the GNU General Public License (GPL). For instructions on how to obtain the source code for this GPL program, please visit http://www.artesyncp.com, send an e-mail to support@artesyncp.com, or call Artesyn at 1-800-327-1251.

  • Page 72: Auto-Repeat

    After a command has been entered, it can be re-executed simply by pressing the ENTER or RETURN key. 8.1.3 TFTP booting Application images can be loaded via Ethernet into the PmPPC440’s memory using the TFTP protocol. 8.1.4 Auto-booting Specific boot commands can be stored in the environment and executed auto- matically after reset.

  • Page 73: Basic Operation

    Basic Operation 8.2 Basic Operation The PmPPC440 monitor performs various configuration tasks upon power-up or reset. This section describes the monitor operation during initialization of the PmPPC440 board. 8.2.1 Power-up/Reset Sequence At power-up or board reset, the PmPPC440 performs the following: 1.
  • Page 74 PmPPC440: Monitor 5. Clear the C BSS section. 6. The monitor initializes on-board devices as follows: (These are board_init_f() function operations while PPCBoot is in RAM.) • Load all PPCBoot commands into RAM. • Copy exception vector table into low RAM.

  • Page 75: Monitor Sdram Usage

    Basic Operation 8.2.2 Monitor SDRAM Usage PPCBoot locates its stack, uninitialized data, and code at the very end of SDRAM. The exact address varies with the amount of installed memory. CAUTION. Any writes to this area can cause unpredictable operation of the monitor.

  • Page 76: Monitor Recovery

    This procedure describes how to recover from corrupted monitor code in the sol- dered flash memory. 1. First, attach a DMC module to the PmPPC440 PMC module. Make sure that a monitor ROM device is installed in the PLCC socket on DMC module and set the boot jumper on the DMC module to boot the PmPPC440 from the socket ROM device (see section 7.3).

  • Page 77: Corrupted Bootstrap I C Parameters

    C nonvolatile memory device. By default, this device is write-pro- tected. (However, it can be unprotected by writing to a PLD register.) If the boot- strap parameters are not properly initialized or are corrupted, the PmPPC440 board may become unstable. The following procedure describes how to recover from this situation: 1.

  • Page 78: Monitor Command Reference

    PmPPC440: Monitor 8.4 Monitor Command Reference This section describes the syntax and typographic conventions for the PmPPC440 monitor commands. Subsequent sections in this chapter describe individual com- mands, which fall into the following categories: boot, memory, Flash, environ- ment variables, test, and other commands.

  • Page 79: Typographic Conventions

    Boot Commands 8.4.2 Typographic Conventions In the following command descriptions, Courier New font is used to show the command format. Square brackets [] enclose optional arguments, and Italic type indicates that you must substitute your own selection for the italicized text. 8.5 Boot Commands The boot commands provide facilities for booting application programs and operating systems from various devices.

  • Page 80: Rarpboot (Boot Rarp/Tftp)

    8-10 PmPPC440: Monitor 8.5.4 rarpboot (boot RARP/TFTP) The rarpboot command boots an image via a network connection using the RARP/TFTP protocol. If loadaddress or bootfilename is not specified, the environ- ment variables loadaddr and bootfile are used as the default.

  • Page 81: File Load Commands

    File Load Commands 8-11 8.6 File Load Commands 8.6.1 loads (load S-record) The loads command loads an S-Record file over the serial port. The command takes two optional parameters: offset The address offset parameter allows the file to be stored in a location dif- ferent than what is indicated within the S-Record file by adding the value [off] to the file’s absolute address.

  • Page 82: Memory Commands

    8-12 PmPPC440: Monitor 8.7 Memory Commands The memory commands provide facilities for manipulating specific regions of memory. For some memory commands, the data size is determined by the follow- ing flags: This is for data in 8-bit bytes. This is for data in 16-bit words.

  • Page 83: Mm (Memory Modify - Incrementing Address)

    Memory Commands 8-13 EXAMPLE In this example, the mw command is used to write the value 0xabba three times starting at the physical address 0x80000. => mw.w 80000 abba 3 => md 80000 00080000: abbaabba abbaffff ffffffff ffffffff ....00080010: ffffffff ffffffff ffffffff ffffffff ....

  • Page 84: Cp (Copy Memory)

    8-14 PmPPC440: Monitor same address. Pressing ENTER without entering a new value leaves the original value unchanged. To exit the nm command, enter a non-valid hexadecimal value (such as x) followed by ENTER. DEFINITION nm [.b, .w, .l] address 8.7.5 cp (copy memory) The cp command copies count objects located at the source address to the target address.

  • Page 85: C Device Commands

    C Device Commands 8-15 8.8 I C Device Commands 8.8.1 imd (I C memory display) The command imd displays the contents of memory for an I C device starting at address. The number of objects displayed can be defined by an optional third argument, # of objects.

  • Page 86: Icrc32

    8-16 PmPPC440: Monitor DEFINITION imw chip address [.0, .1, .2] value [count] 8.8.5 icrc32 The icrc32 command computes a CRC32 checksum for an I C device on count bytes starting at address. DEFINITION icrc32 chip address count 8.8.6 iprobe The iprobe command discovers valid I C devices.

  • Page 87: Iloop

    C Device Commands 8-17 8.8.7 iloop The iloop command executes an infinite loop on an address range. DEFINITION iloop chip address [.b, .w, .l] number_of_objects 8.8.8 isdram The isdram command prints the SDRAM configuration for an SPD device. DEFINITION isdram chip EXAMPLE =>...

  • Page 88: Flash Commands

    8.9 Flash Commands The Flash commands affect the StrataFlash devices on the PmPPC440 circuit board. There is a maximum of two Flash banks on the PmPPC440 board. The fol- lowing Flash commands access the individual Flash banks as Flash bank 1 or Flash bank 2.

  • Page 89: Protect (Flash Sector Protect)

    Flash Commands 8-19 Erase all of the sectors in Flash bank # N. erase bank N Erase all of the sectors in all of the Flash banks. erase all 8.9.3 protect (Flash sector protect) The protect command enables or disables the Flash sector protection for the specified Flash sector.

  • Page 90: Environment Parameter Commands

    8-20 PmPPC440: Monitor 8.10 Environment Parameter Commands The monitor uses on-board, non-volatile memory for the storage of environment parameters. Environment parameters are stored as ASCII strings with the follow- ing format. <Parameter Name>=<Parameter Value> Some environment variables are used for board configuration and identification by the monitor.

  • Page 91: Initenv (Initialize Environment)

    Test Commands 8-21 8.10.4 initenv (initialize environment) The initenv command initializes all PmPPC440-specific environment variables to their factory defaults. This command over-writes any existing configurations. The four-digit serial number must be entered with this command. DEFINITION initenv serial number 8.11 Test Commands 8.11.1 um (destructive memory test)

  • Page 92: Run

    8-22 PmPPC440: Monitor 8.12.2 run The run command runs the commands in an environment variable var. DEFINITION run var […] 8.12.3 crc32 The crc32 command computes a CRC32 checksum on count bytes starting at address. DEFINITION crc32 address count 8.12.4 base The base command prints or sets the address offset for memory commands.

  • Page 93: Coninfo

    Other Commands 8-23 8.12.7 coninfo The coninfo command displays the information for all available console devices. DEFINITION coninfo 8.12.8 loop The loop command executes an infinite loop on address range. DEFINITION loop [.b, .w, .l] address number_of_objects 8.12.9 reset The reset command performs a hard reset of the CPU by writing to the reset reg- ister on the board.

  • Page 94: Help

    8-24 PmPPC440: Monitor 8.12.13 help The help (or ?) command displays the online help. Without arguments, all com- mands are displayed with a short usage message for each. To obtain more detailed information for a specific command, enter the desired command as an argument.

  • Page 95: Troubleshooting

    Troubleshooting 8-25 Table 8-2. Optional Environment Variable Variable Default Value Description Enable/disable ECC protection (on = enable, off = disable) This is not initialized by initenv. (Note: This variable is currently not implemented.) 8.14 Troubleshooting To bypass the full board initialization sequence, attach a terminal to the console located on the front of the module.
  • Page 96 8-26 PmPPC440: Monitor April 2005...
  • Page 97 JP2 7-10 file load commands, monitor 8-11 caution statements Flash commands, monitor 8-18 writes to monitor area 8-5 component map DMC 7-2 PmPPC440, bottom 2-4 grounding 2-1 PmPPC440, top 2-3 connectors overview, DMC 7-3 overview, module 2-5 PMC 5-5...
  • Page 98 I2C crc32 8-16 returning boards 2-13, 7-13 I2C DRAM config. 8-17 RMA number 2-13, 7-14 I2C loop 8-17 I2C probe 8-16 imd (I2C memory display) 8-15 iminfo 8-22 serial I/O 3-6 (I2C memory modify-incrementing serial number address) 8-15 Index-2 PmPPC440: Index...
  • Page 99 DMC 7-2 PMC interrupt, PCI 5-3 location 2-5 power management, PCI 5-3 user ROM 2-5, 7-3 present, PCI 5-3 service information 2-13, 7-13 ready, PCI 5-2 setup REQ64*, PCI 5-2 DMC requirements 7-11 REQ64, PCI 5-3 module requirements 2-6 request, PCI 5-4 signal descriptions reset output, PCI 5-3 DMC 7-5...

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