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5
1U_0603_10V4Z
2
C319
1
0.01U_0402_16V7K
D
+3VS
R236
R252 6.34K_0402_1%
CPS
1
2
1
2
4.7K_0402_5%
PHY_TEST
XTPBIAS0
1
R250
2
4.7K_0402_5%
XTPA0+
XTPA0-
R213
XTPB0+
MC_PWRON#
XTPB0-
1
2
7611@
10K_0402_5%
XTPBIAS1
R251
CNA
1
2
10K_0402_5%
XTPB1+
XTPB1-
PHY_TEST
CPS
CNA
X_OUT
X_IN
C
<25>
MC_PWRON#
<25>
SD_CD#
<25>
MS_CD#
BOM change
<25>
SM_CD#
R224
7611@
0_0402_5%
1
2
<25>
MSCLK_SDCLK_SMELWP#
R536
7611@
0_0402_5%
1
2
<25>
CB_MSBS_SDCMD_SMWE#
R537
1
2
7611@
0_0402_5%
<25>
MSD3_SDD3_SMD3
R538
7611@
0_0402_5%
1
2
<25>
MSD2_SDD2_SMD2
R539
7611@
0_0402_5%
1
2
<25>
MSD1_SDD1_SMD1
R540
7611@
0_0402_5%
1
2
<25>
MSD0_SDD0_SMD0
CB_SDCLK_SMRE#
R209
7611@
0_0402_5%
1
2
<25>
SDCMD_SMALE
<25>
SDD0_SMD4
<25>
SDD1_SMD5
<25>
SDD2_SMD6
<25>
SDD3_SMD7
<25>
CB_SDWP#_SMCE#
<25>
SMCLE
CB_SM_RB#
TI requires to pull high this pin
B
1
2
+5VS
R208
7611@
10K_0402_5%
<26>
VCCD1#
R240
220_0402_5%
1
2
4510@
R247
220_0402_5%
1
2
+VDDPLL
1
2
C332
4510@
0.1U_0402_16V4Z
CLK_48M_CB
1
2
<15>
CLK_48M_CB
R532
7611@
0_0402_5%
R533
0_0402_5%
4510@
CLK_48M_CB
C343
R93
@
10_0402_5%
@
1M_0402_5%
A
1
C112
@
10P_0402_25V8K
2
C342 10P_0402_50V8J
5
4
0.01U_0402_16V7K
+3VS
+3VS_PLL
10U_0805_10V4Z
C326
1
1
C317
C303
+3VS
1
1
2
2
2
2
U23B
AD31
AD30
U18
R0
AD29
U19
R1
AD28
AD27
U15
TPBIAS0
AD26
V15
TPA0+
AD25
W15
TPA0-
AD24
V14
TPB0+
AD23
W14
TPB0-
AD22
AD21
U17
TPBIAS1
AD20
V18
TPA1+
AD19
W18
TPA1-
AD18
V16
TPB1+
AD17
W16
TPB1-
AD16
AD15
R17
PHY_TEST_MA
AD14
M11
CPS
AD13
P15
CNA
AD12
AD11
R19
XO
AD10
AD9
R18
XI
AD8
AD7
R12
PC0(TEST1)
AD6
U13
PC1(TEST2)
AD5
V13
PC2(TEST3)
AD4
AD3
AD2
F1
MC_PWR_CTRL_0
AD1
F2
MC_PWR_CTRL_1
AD0
E3
SD_CD#
F5
MS_CD#
C/BE3#
F6
SM_CD#
C/BE2#
C/BE1#
G5
MS_CLK/SD_CLK/SM_EL_WP#
C/BE0#
F3
MS_BS/SD_CMD/SM_WE#
H5
MS_DATA3/SD_DAT3/SM_D3
PAR
G3
MS_DATA2/SD_DAT2/SM_D2
FRAME#
G2
MS_DATA1/SD_DAT1/SM_D1
TRDY#
G1
MS_SDIO(DATA0)/SD_DAT0/SM_D0
IRDY#
STOP#
J5
SD_CLK/SM_RE#/SC_GPIO1
DEVSEL#
J3
SD_CMD/SM_ALE/SC_GPIO2
IDSEL
H3
SD_DAT0/SM_D4/SC_GPIO6
PERR#
J6
SD_DAT1/SM_D5/SC_GPIO5
SERR#
J1
SD_DAT2/SM_D6/SC_GPIO4
REQ#
J2
SD_DAT3/SM_D7/SC_GPIO3
GNT#
H7
SD_WP/SM_CE#
PCICLK
J7
SM_CLE/SC_GPIO0
PCIRST#
K1
SM_R#/SC_RFU
GRST#
K2
SM_PHYS_WP#/SC_FCB
RI_OUT#/PME#
L2
SC_CD#
SUSPEND#
K5
SC_CLK
K3
SC_RST
SPKROUT
K7
SC_VCC_5V
L1
SC_DATA
MFUNC0
L3
SC_OC#
MFUNC1
L5
SC_PWR_CTRL
MFUNC2
MFUNC3
P12
TEST0
MFUNC4
W17
NC
MFUNC5
T19
RSVD
MFUNC6
SCL
M1
CLK_48
SDA
VR_EN#
SNC1R21GHK_PBGA288
C331
+VDDPLL
1
2
7611@
0.1U_0402_16V4Z
put C331 as close to
controller as possible
10P_0402_50V8J
X_IN
R253
X2
X_OUT
24.576MHZ_16P_XSL024576FG1H
4
3
+3VS_PLL
+3VS
R254
0_0603_5%
2
1
1
C334
C330
<25>
MSBS_SDCMD_SMWE#
10U_0805_10V4Z
1
2
2
1U_0603_10V4Z
<25>
PCI_AD31
U2
PCI_AD30
V1
PCI_AD29
V2
PCI_AD28
U3
PCI_AD27
W2
PCI_AD26
V3
PCI_AD25
U4
PCI_CBE#[0..3] <18,27,29>
PCI_AD24
V4
PCI_AD23
V5
PCI_AD22
U5
PCI_AD[0..31] <18,22,27,29>
PCI_AD21
R6
PCI_AD20
P6
PCI_AD19
W6
PCI_AD18
V6
PCI_AD17
U6
PCI_AD16
R7
PCI_AD15
V9
PCI_AD14
U9
PCI_AD13
R9
PCI_AD12
N9
PCI_AD11
V10
+3VS
PCI_AD10
U10
PCI_AD9
R10
PCI_AD8
N10
PCI_AD7
V11
PCI_AD6
U11
PCI_AD5
R225
R11
PCI_AD4
10K_0402_5%
W12
PCI_AD3
V12
PCI_AD2
U12
PCI_AD1
CB_PME#
N11
3
1
PCI_PME# <19,29>
PCI_AD0
W13
Q18
PCI_CBE#3
2N7002_SOT23
W4
PCI_CBE#2
W7
PCI_CBE#1
W9
PCI_CBE#0
W11
P9
PCI_PAR <18,27,29>
V7
PCI_FRAME# <18,27,29>
R8
PCI_TRDY# <18,27,29>
U7
PCI_IRDY# <18,27,29>
W8
PCI_STOP# <18,27,29>
CLK_PCI_PCM
N8
PCI_DEVSEL# <18,27,29>
R235
PCI_AD20
W5
1
2
100_0402_5%
V8
PCI_PERR# <18,27,29>
U8
PCI_SERR# <18,27,29,38>
U1
PCI_REQ#2 <18>
T2
PCI_GNT#2 <18>
P5
CLK_PCI_PCM <18>
R3
PCI_RST# <18,26,27,29,32>
T1
CB_PME#
T3
R2
R226
1
2
+3VS
4.7K_0402_5%
PCM_SPK#
L7
PCM_SPK# <30>
N3
PCI_PIRQE# <18>
M5
PCI_PIRQF# <18>
P1
P2
SIRQ
<18,37,38>
R228
P3
1
2
+3VS
CARD_LED
4.7K_0402_5%
N5
R1
PM_CLKRUN# <18,27,29,37,38>
R215
220_0402_5%
M3
1
2
R229
M2
1
2
220_0402_5%
If EEPROM is unused, SCL/SDA must be
VR_EN#
H2
pulled down to GND with 220ohm resistor.
R231
10K_0402_5%
when VR_EN# is low, internal
regulator is actived
D17
7611@
12-21SYGC/S530-E1/TR8_GRN
Layout change
R556
@
10K_0402_5%
R495
1
2
2
<25>
CARD_LED
7611@
1K_0402_5%
Compal Secret Data
Security Classification
2005/03/01
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
U41
MC_PWRON#
1
14
1OE#
VCC
CB_MSBS_SDCMD_SMWE#
2
13
1A
4OE#
MSBS_SDCMD_SMWE#
3
12
1B
4A
4
11
2OE#
4B
CB_SDCLK_SMRE#
5
10
2A
3OE#
SDCLK_SMRE#
6
9
SDCLK_SMRE#
2B
3A
7
8
GND
3B
7611@
SN74CBTLV3125PWR_TSSOP14
Layout change
PCM_SPK#
R531
@
33K_0402_5%
R245
56.2_0603_1%
R227
XTPBIAS0
XTPA0+
@
10_0402_5%
XTPA0-
XTPB0+
XTPB0-
1
C291
@
10P_0402_25V8K
CLOSE TO CHIP
2
R241
56.2_0603_1%
1
C314
220P_0603_50V8J
2
CLOSE TO CHIP
+3VS
CARDREADER LED
XTPBIAS1
GREEN
2
XTPB1+
C324
XTPB1-
1U_0603_10V4Z
1
R496
7611@
R243
R246
220_0402_5%
1K_0402_5%
1K_0402_5%
Q45
7611@
MMBT3904_SOT23
2006/03/11
Title
Deciphered Date
Size
Document Number
Custom
Date:
Friday, April 15, 2005
2
1
+3VS
MC_PWRON#
CB_SM_RB#
SM_RB#
SM_RB#
<25>
CB_SDWP#_SMCE#
SDWP#_SMCE#
D
SDWP#_SMCE# <25>
C
2
R244
C325
56.2_0603_1%
1U_0603_10V4Z
1
4
4
3
3
2
2
1
1
JP10
R242
SUYIN_020204FR004S506ZL
56.2_0603_1%
B
R239
5.1K_0603_1%
A
CardBus Controller TI7611
R e v
0.4
LA-2541
Sheet
23
o f
58
1
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