Sony STR-DB840 Service Manual page 54

Pin No. Pin Name
CLKI
99
CLKO
100
VSS1
101
VDD0
102
AVSS
103
104 AVDD
PLLCK
105
XPLLEN
106
TST
107
LRCT
108
109 LROUT
BKOUT
110
VSS2
111
VDD1
112
113 BCK0
BCK1
114
LRCK0
115
LRCK1
116
117 to
SIA to SID
120
54
I/O
I
Master clock signal input terminal (10MHz)
O
Master clock signal output terminal (10MHz)
—
Ground terminal
—
Power supply terminal (+3.3V)
—
Ground terminal (for PLL cell)
— Power supply terminal (+3.3V) (for PLL cell)
I/O
PLL output/test clock signal input terminal (for check)
PLL cell oscillation enable signal input terminal
I
(fixed at "L" in this set)
I
Test data input terminal (Normally: fixed at "L")
I
Frequency counter input terminal (fixed at "L" in this set)
O Clock driver signal output terminal (for check)
O
Clock driver signal output terminal (for check)
—
Ground terminal
—
Power supply terminal (+3.3V)
I Clock 0 signal input from the digital audio interface receiver (IC1101)
I
Clock 1 signal input from the digital audio interface receiver (IC1101)
I
Clock 0 signal input from the digital audio interface receiver (IC1101)
I
Clock 1 signal input from the digital audio interface receiver (IC1101)
—
Serial data input from the dolby digital audio decoder (IC1301)
Description
"L": oscillation enable