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WinSystems - "The Embedded Systems Authority" RE VI SION HIS TORY P/N 403- 0230- 000 ECO Num ber Date Code Rev Level Origi nated 960206 97- 31 970513...
TA BLE OF CON TENTS Sec tion Para graph Page Num ber Ti tle Num ber Gen eral In for ma tion Fea tures Gen eral De scrip tion Speci fi ca tions PCM-A/D Tech ni cal Ref er ence In tro duc tion I/O Ad dress Se lec tion In ter rupt Rout ing...
Op tional DC/DC con verter for +5V only op era tion General Description The PCM-A/D-16 and PCM-A/D-12 are low cost, gen eral pur pose, suc ces sive ap proxi - ma tion analog- to- digital con vert ers. The PCM-A/D-16 uses the Burr- Brown ADS7807 16- bit con verter while the PCM-A/D-12 uses the Burr- Brown ADS7806 12- bit con verter.
WinSystems - "The Embedded Systems Authority" Specifications Electrical 1.3.1 Bus In ter face : PCM-A/D- XX-8 PC/104 8- Bit stack through PCM-A/D- XX- 16 PC/104 16- Bit stack through Power re quire ments : +5V +/- 5% at 200mA typ. with DC- DC con verter in stalled 15mA typ.
This sec tion of the man ual is in tended to pro vide suf fi cient in for ma tion re gard ing con - figu ra tion and us age of the PCM-A/D-16 and PCM-A/D-12 mod ules. Win Sys tems main - tains a Tech ni cal Sup port Group to help an swer ques tions re gard ing con figu ra tion and pro gram ming of the board.
WinSystems - "The Embedded Systems Authority" The PCM-A/D uses four con secu tive I/O ad dresses with the base ad dress de ter mined by the set ting of the jump ers on J8. Each po si tion on the J8 jumper cor re sponds to an ad dress bit.
WinSystems - "The Embedded Systems Authority" DC-DC Converter Selection To al low for slightly bet ter line ar ity across the full +/-10V in put range sup ported, an op tional DC- DC con verter is popu lated at VR1. When in stalled, it pro vides +15V and -15V to the ana log cir cuitry.
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WinSystems - "The Embedded Systems Authority" Mode 1 - 0-5V Single-Ended Unipolar 2.5.1 This in put mode pro vides for 16 chan nels of 0-5 volt in put range. In no case should the in put be driven nega tive in this mode. The cor rect jump er ing for this mode is shown be low : Each chan nel's in put is de liv ered at J3.
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WinSystems - "The Embedded Systems Authority" Mode 2 - +/-10V Single-Ended Bipolar 2.5.2 This in put mode pro vides for 16 chan nels of +-10V in put range. The cor rect jump er ing for this mode is shown be low :...
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WinSystems - "The Embedded Systems Authority" Mode 3 - 0-5V Differential 2.5.3 This in put mode pro vides for 8 chan nels of 0- 5volt dif fer en tial in put. The cor rect jump - er ing for this mode is shown be low :...
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WinSystems - "The Embedded Systems Authority" Mode 4 - +/-10 Volt differential/Bipolar 2.5.4 This mode pro vides 8 chan nels of dif fer en tial in put with 2 im por tant limi ta tions. 1. The maxi mum dif fer en tial volt age be tween the two legs is 10V.
WinSystems - "The Embedded Systems Authority" Input Connector Pin definitions In put to the PCM-A/D board is made via J3. When used in the single- ended mode, 16- channels are avail able and when used in a dif fer en tial mode, 8 chan nels are avail able. The il lus tra tion be low shows the pin defi ni tions for each case.
WinSystems - "The Embedded Systems Authority" Connector/Jumper Summary Con nec tor/ De scrip tion Page Jumper Ref er ence Mode Se lect, dif fer en tial or single- ended DC- DC Con verter En able Ana log in put con nec tor In put range se lect jumper Mode se lect, dif fer en tial vs.
PCM-A/D Programming Reference I/O Register Definitions The PCM-A/D uses 4 con secu tive I/O ad dresses be gin ning with a base ad dress se lected via jumper block J8. See Sec tion 2.1 for I/O ad dress se lec tion de tails. The four al lo cated I/O ad dresses are used as shown here : AD DRESS Write Reg is ter...
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WinSystems - "The Embedded Systems Authority" Read Reg is ter - Con ver sion Status D7 - N/A D6 - N/A D5 - N/A D4 - N/A D3 - N/A D2 - N/A D1 - Busy 0 = Con verter busy, 1 = Con ver sion com plete D0 - In ter rupt 0 = Con ver sion in prog ress, 1 = Con ver sion com plete This status reg is ter in di cates when a con ver sion is com plete.
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WinSystems - "The Embedded Systems Authority" Note that the data is only valid if both the BUSY and IN TER RUPT bits are both set to 1 in the status reg is ter. Base + 2 Address 3.1.3 Write Reg is ter - Start Con ver sion...
WinSystems - "The Embedded Systems Authority" Conversion Techniques The PCM-A/D can be pro grammed in any lan guage sup port ing port I/O in struc tions. The code snip pet be low is in the 'C' lan guage and dem on strates a sim ple func tion that takes as an ar gu ment the chan nel number and re turns a 16- bit un signed value cor re spond ing to the cur rent con ver sion value.
WinSystems - "The Embedded Systems Authority" PCM-A/D Demonstration Program In cluded on a 3 1/2" disk ette with the PCM-A/D board is a sam ple pro gram in both 'C' source code and in MS- DOS ex ecu ta ble for mat. The PCMAD12.EXE file was cre ated us ing Bor land C/C++ Ver sion 3.1.
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WinSystems - "The Embedded Systems Authority" There are 5 key strokes rec og nized by PCMAD12.EXE. They are as fol lows : 'T' - Tog gles the in put mode through the 4 sup ported modes : +0 to +5 Volts - Sin gle Ended...
WinSystems - "The Embedded Systems Authority" Calibration Procedures 1. Jumper the board for 0-5 Volt Single- Ended Mode. Base Ad dress 110H and IRQ5. 2. Run the PCMAD12.EXE pro gram. 3. Ap ply a pre ci sion (+/-1.5mV) in put source to chan nel 0. Set the source to 0.00V 4.
APPENDIX C BURR- BROWN ADS7806/ADS7807 Da tasheet Re print...
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® ADS7806 Low-Power 12-Bit Sampling CMOS ANALOG-to-DIGITAL CONVERTER FEATURES DESCRIPTION 35mW max POWER DISSIPATION The ADS7806 is a low-power 12-bit sampling analog- µ to-digital using state-of-the-art CMOS structures. It W POWER DOWN MODE contains a complete 12-bit, capacitor-based, SAR A/D µ...
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SPECIFICATIONS ELECTRICAL At T = –40°C to +85°C, f = 40kHz, V = +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified. ADS7806P, U ADS7806PB, UB PARAMETER CONDITIONS UNITS RESOLUTION Bits ANALOG INPUT ±10, 0 to +5, 0 to +4 Voltage Ranges Impedance (See Table II)
SPECIFICATIONS (CONT) ELECTRICAL At T = –40°C to +85°C, f = 40kHz, V = +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified. ADS7806P, U ADS7806PB, UB PARAMETER CONDITIONS UNITS DIGITAL TIMING Bus Access Time = 3.3kΩ, C = 50pF Bus Relinquish Time...
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DIGITAL PIN # NAME DESCRIPTION Analog Input. See Figure 7. AGND1 Analog Sense Ground. Analog Input. See Figure 7. Reference Buffer Output. 2.2µF tantalum capacitor to ground. Reference Input/Output. 2.2µF tantalum capacitor to ground. AGND2 Analog Ground. SB/BTC Selects Straight Binary or Binary Two’s Complement for Output Data Format. EXT/INT External/Internal data clock select.
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TYPICAL PERFORMANCE CURVES = +25°C, f = 40kHz, V = +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified. FREQUENCY SPECTRUM FREQUENCY SPECTRUM (8192 Point FFT; f = 1kHz, 0dB) (8192 Point FFT; f = 15kHz, 0dB) –20 –20 –40...
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TYPICAL PERFORMANCE CURVES (CONT) = +25°C, f = 40kHz, V = +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified. POWER SUPPLY RIPPLE SENSITIVITY INL/DNL DEGRADATION PER LSB OF P-P RIPPLE 0.10 –1 All Codes INL –2 –0.10 2560...
BASIC OPERATION output valid data from the previous conversion on SDATA (pin 19) synchronized to 12 clock pulses output on PARALLEL OUTPUT DATACLK (pin 18). BUSY (pin 24) will go LOW and stay LOW until the conversion is completed and the serial data Figure 1a) shows a basic circuit to operate the ADS7806 with a ±10V input range and parallel output.
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The ADS7806 will begin tracking the input signal at the end CS and R/C are internally OR’d and level triggered. There of the conversion. Allowing 25µs between convert com- is not a requirement which input goes LOW first when mands assures accurate acquisition of a new signal. Refer to initiating a conversion.
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PARALLEL OUTPUT (After a Conversion) port will shift the internal output registers one bit per data clock pulse. As a result, data can be read on the parallel port After conversion ‘n’ is completed and the output registers prior to reading the same data on the serial port, but data have been updated, BUSY (pin 24) will go HIGH.
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SERIAL OUTPUT INTERNAL DATA CLOCK (During A Conversion) Data can be clocked out with the internal data clock or an To use the internal data clock, tie EXT/INT (pin 8) LOW. external data clock. When using serial output, be careful The combination of R/C (pin 22) and CS (pin 23) LOW will with the parallel outputs, D7-D0 (pins 9-13 and 15-17), as initiate conversion ‘n’...
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FIGURE 5. Conversion and Read Timing with External Clock (EXT/INT Tied HIGH) Read after Conversion. ® ADS7806...
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EXTERNAL DATACLK BUSY Bit 11 (MSB) Bit 0 (LSB) Tag 0 Tag 1 DATA Tag 0 Tag 1 Tag 12 Tag 13 Tag 14 FIGURE 6. Conversion and Read Timing with External Clock (EXT/INT tied HIGH) Read During a Conversion. EXTERNAL DATA CLOCK TAG FEATURE (After a Conversion)
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used for each input range (see Figure 8). The input resistor OFFSET ADJUST GAIN ADJUST divider network provides inherent overvoltage protection INPUT RANGE RANGE (mV) RANGE (mV) guaranteed to at least ±25V. ±10V ±15 ±60 Analog inputs above or below the expected range will yield ±4 ±30 0 to 5V...
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ered when choosing the accuracy and drift specifications of To further analyze the effects of removing any combination the external resistors. In most applications, 1% metal-film of the external resistors, consider Figure 9. The combination resistors will be sufficient. of the external and the internal resistors form a voltage divider which reduces the input signal to a 0.3125V to The external resistors shown in Figure 7b may not be 2.8125V input range at the CDAC.
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output of the buffer. Using a capacitor any smaller than 1µF loading effects on the external reference. See Figure 10 for can cause the output buffer to oscillate and may not have the characteristic impedance of the reference buffer’s input sufficient charge for the CDAC.
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The resistive front end of the ADS7806 also provides a bus. This interface and the following discussion assume a guaranteed ±25V overvoltage protection. In most cases, this master clock for the QSPI interface of 16.78MHz. Notice eliminates the need for external over voltage protection that the serial data input of the microcontroller is tied to the circuitry.
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SPI INTERFACE the pulse width is (0.7)RC. Choosing a pulse width as close to the minimum value specified in this data sheet will offer The SPI interface is generally only capable of 8-bit data the best performance. See the Starting A Conversion sec- transfers.
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® ADS7807 Low-Power 16-Bit Sampling CMOS ANALOG-to-DIGITAL CONVERTER DESCRIPTION FEATURES 35mW max POWER DISSIPATION The ADS7807 is a low-power, 16-bit, sampling A/D µ using state-of-the-art CMOS structures. It contains a W POWER DOWN MODE complete 16-bit, capacitor-based, SAR A/D with S/H, µ...
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SPECIFICATIONS ELECTRICAL At T = –40°C to +85°C, f = 40kHz, V = +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified. ADS7807P, U ADS7807PB, UB PARAMETER CONDITIONS UNITS RESOLUTION Bits ANALOG INPUT ±10, 0 to +5, 0 to +4 Voltage Ranges Impedance (See Table II)
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SPECIFICATIONS (CONT) ELECTRICAL At T = –40°C to +85°C, f = 40kHz, V = +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified. ADS7807P, U ADS7807PB, UB PARAMETER CONDITIONS UNITS DIGITAL TIMING Bus Access Time = 3.3kΩ, C = 50pF Bus Relinquish Time...
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DIGITAL PIN # NAME DESCRIPTION Analog Input. See Figure 7. AGND1 Analog Sense Ground. Analog Input. See Figure 7. Reference Buffer Output. 2.2µF tantalum capacitor to ground. Reference Input/Output. 2.2µF tantalum capacitor to ground. AGND2 Analog Ground. SB/BTC Selects Straight Binary or Binary Two’s Complement for Output Data Format. EXT/INT External/Internal data clock select.
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TYPICAL PERFORMANCE CURVES At T = +25°C, f = 40kHz, V = +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified. FREQUENCY SPECTRUM FREQUENCY SPECTRUM (8192 Point FFT; f = 15kHz, 0dB) (8192 Point FFT; f = 1kHz, 0dB) –10 –10...
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TYPICAL PERFORMANCE CURVES (CONT) At T = +25°C, f = 40kHz, V = +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified. POWER SUPPLY RIPPLE SENSITIVITY INL/DNL DEGRADATION PER LSB OF P-P RIPPLE All Codes INL –1 –1 –2...
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BASIC OPERATION output valid data from the previous conversion on SDATA (pin 19) synchronized to 16 clock pulses output on PARALLEL OUTPUT DATACLK (pin 18). BUSY (pin 24) will go LOW and stay LOW until the conversion is completed and the serial data Figure 1a) shows a basic circuit to operate the ADS7807 with a ±10V input range and parallel output.
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The ADS7807 will begin tracking the input signal at the end CS and R/C are internally OR’d and level triggered. There of the conversion. Allowing 25µs between convert com- is not a requirement which input goes LOW first when mands assures accurate acquisition of a new signal. Refer to initiating a conversion.
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port will shift the internal output registers one bit per data PARALLEL OUTPUT (After a Conversion) clock pulse. As a result, data can be read on the parallel port After conversion ‘n’ is completed and the output registers prior to reading the same data on the serial port, but data have been updated, BUSY (pin 24) will go HIGH.
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SERIAL OUTPUT INTERNAL DATA CLOCK (During a Conversion) Data can be clocked out with the internal data clock or an To use the internal data clock, tie EXT/INT (pin 8) LOW. external data clock. When using serial output, be careful The combination of R/C (pin 22) and CS (pin 23) LOW will initiate conversion ‘n’...
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FIGURE 5. Conversion and Read Timing with External Clock (EXT/INT Tied HIGH) Read after Conversion. ® ADS7807...
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EXTERNAL DATACLK BUSY Bit 15 (MSB) Bit 0 (LSB) Tag 1 DATA Tag 0 Tag 0 Tag 1 Tag 16 Tag 17 Tag 18 FIGURE 6. Conversion and Read Timing with External Clock (EXT/INT tied HIGH) Read During a Conversion. EXTERNAL DATA CLOCK TAG FEATURE (After a Conversion)
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used for each input range (see Figure 8). The input resistor OFFSET ADJUST GAIN ADJUST divider network provides inherent overvoltage protection INPUT RANGE RANGE (mV) RANGE (mV) guaranteed to at least ±25V. ±10V ±15 ±60 Analog inputs above or below the expected range will yield ±4 ±30 0 to 5V...
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The external resistors shown in Figure 7b may not be divider which reduces the input signal to a 0.3125V to necessary in some applications. These resistors provide 2.8125V input range at the CDAC. The internal resistors are compensation for an internal adjustment of the offset and laser trimmed to high relative accuracy to meet full scale gain which allows calibration with a single supply.
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200Ω 39.8kΩ CDAC (0.3125V to 2.8125V) 20kΩ 40kΩ 66.5kΩ 9.9kΩ 100Ω +2.5V +2.5V 200Ω 39.8kΩ CDAC (0.3125V to 2.8125V) 33.2kΩ 100Ω 9.9kΩ 20kΩ 40kΩ +2.5V +2.5V 200Ω 39.8kΩ CDAC (0.3125V to 2.8125V) 33.2kΩ 40kΩ 100Ω 9.9kΩ 20kΩ +2.5V +2.5V FIGURE 9. Circuit Diagrams Showing External and Internal Resistors. the overall power consumption of the ADS7807 by approxi- mately 5mW.
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cycle. This capacitor also provides compensation for the loading effects on the external reference. See Figure 10 for output of the buffer. Using a capacitor any smaller than 1µF the characteristic impedance of the reference buffer’s input can cause the output buffer to oscillate and may not have for both REFD HIGH and LOW.
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The resistive front end of the ADS7807 also provides a guaranteed ±25V overvoltage protection. In most cases, this eliminates the need for external over voltage protection circuitry. INTERMEDIATE LATCHES The ADS7807 does have tri-state outputs for the parallel port, but intermediate latches should be used if the bus will be active during conversions.
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Figure 15 shows another interface between the ADS7807 QSPI ADS7807 and a QSPI equipped microcontroller which allows the microcontroller to give the convert pulses while also allow- PCS0 EXT/INT ing multiple peripherals to be connected to the serial bus. This interface and the following discussion assume a master PCS1 clock for the QSPI interface of 16.78MHz.
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The monostable multi-vibrator in this circuit will provide width as close to the minimum value specified in this data varying pulse widths for the convert pulse. The pulse sheet will offer the best performance. See the Starting A width will be determined by the external R and C values Conversion section of this data sheet for details on the used with the multi-vibrator.
APPENDIX D PCM-A/D Demo Soft ware Source List ing...
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****************************************************************************** /* Permission is hereby granted to users of the Winsystems PCM-A/D-12 and PCM-A/D-16 boards to freely use this source code as-is or in any user modified form for personal or commercial use. WinSystems provides this sample source code on an as-is basis and makes no warranty as to fitness of purpose.
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/* These four arrays, store the low, high, and current values for each of the 16 channels. There are more elegant ways to code this but this is the ultimate in simplicity. unsigned current_val[16]; unsigned high_val[16]; unsigned low_val[16]; char flag[16]; /* Various global variables used to keep track of the current channel and the floating point values used in calculating voltages.
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\n"); /* Display all of the channel numbers and clear the flags */ for(channel = 0; channel < max_channel; channel++) flag[channel] = 0; gotoxy(1,channel + 4); printf(" %02d",channel); /* Display the screen footer */ gotoxy(1,21); printf ("----------------------------------------------------------------------------- \n"); printf("'T' Toggle Scale, 'B' Converter toggle 'M' Interrupt toggle, 'R' Reset values\n");...
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if(!interrupt_mode) outportb(0x21,inportb(0x21) | IRQ_MASK); else outportb(0x21,inportb(0x21) & ~IRQ_MASK); outportb(AD_BASE+1,channel_number); /* Jump start the background task /* This loop runs until we exit or until we change modes */ while(1) if(kbhit()) /* If a kestroke detected, see what is is and handle it accordingly.
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max_channel = 8; offset_val = 10.0; full_scale = 20.0; goto restart; else if(c == 'm') interrupt_mode++; interrupt_mode = interrupt_mode & 1; goto restart; else if(c == 'b') full_count = full_count ^ 0x000f; goto restart; else break; /* Go through channel by channel displaying the current value */ for(channel = 0;...
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clrscr(); /* This function polls the AD chip awaiting the completion of the conversion in progress. void wait_complete() int stat; while(1) stat = inportb(AD_BASE); /* Read status */ if((stat & 0x03) == 3) break; if(kbhit()) /* We allow a keystroke to also get us out */ break;...
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if((current ^ 0x8000) > (high_val[temp] ^ 0x8000)) high_val[temp] = current; else if(current < low_val[temp]) low_val[temp] = current; if(current > high_val[temp]) high_val[temp] = current; /* Send the EOI to the interrupt controller to re-arm for next interrupt */ outportb(0x20,0x20);...
. . E-mail: info@winsystems.com WARRANTY WinSystems warrants that for a period of two (2) years from the date of shipment any Products and Software purchased or licensed hereunder which have been developed or manufactured by WinSystems shall be free of any material defects and shall perform substantially in accordance with WinSystems' specifications therefore.
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