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Terasic ALTERA VEEK-MT User Manual

Video and embedded evaluation kit- muli-touch
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Summary of Contents for Terasic ALTERA VEEK-MT

  • Page 2: Table Of Contents

    CONTENTS   INTRODUCTION OF THE VEEK-MT ................CHAPTER 1 1.1 About the Kit ..............................5 1.2 Setup License for Terasic Multi-touch IP....................6 1.3 Getting Help ...............................7 ARCHITECTURE ......................CHAPTER 2 2.1 Layout and Components..........................8 2.2 Block Diagram of the VEEK-MT-MT......................9 USING VEEK-MT CHAPTER 3 ......................10...
  • Page 3 5.3 Application Selector Details ........................40 5.4 Restoring the Factory Image ........................42 APPENDIX CHAPTER 6 ........................45 6.1 Revision History............................45 6.2 Copyright Statement ..........................45...

  • Page 4: Chapter 1 Introduction Of The Veek-Mt

      Chapter 1 Introduction The Video and Embedded Evaluation Kit - Multi-touch (VEEK-MT) is a comprehensive design environment with everything embedded developers need to create processing-based systems. VEEK-MT delivers an integrated platform that includes hardware, design tools, intellectual property (IP) and reference designs for developing embedded software and hardware platform in a wide range of applications.
  • Page 5 Figure 1-1 Video and Embedded Development Kit – Multi-touch The key features of the board are listed below: DE2-115 Development Board • Cyclone IV EP4CE115 FPGA o 114,480 LEs o 432 M9K memory blocks o 3,888 Kb embedded memory o 4 PLLs •...
  • Page 6 • Character Display o 16x2 LCD module • On-board Clocking Circuitry o Three 50MHz oscillator clock inputs o SMA connectors (external clock input/output) • SD Card Socket o Provides SPI and 4-bit SD mode for SD Card access • Two Gigabit Ethernet Ports o Integrated 10/100/1000 Ethernet •...
  • Page 7 Table 1-1 General Physical Specifications of the LCD Item Specification Unit LCD size 7-inch (Diagonal) Resolution 800 x3(RGB) x 480 Dot pitch 0.1926(H) x0.1790 (V) Active area 154.08 (H) x 85.92 (V) Module size 164.9(H) x 100.0(V) x 5.7(D) Surface treatment Glare Color arrangement RGB-stripe...

  • Page 8: About The Kit

    Pixel dynamic range 70.1dB SNRMAX 38.1dB Power 3.3V Supply Voltage 1.7V～3.1V Digital Accelerometer Digital Accelerometer • Up to 13-bit resolution at +/- 16g • SPI (3- and 4-wire) digital interface • Flexible interrupts modes Ambient Light Sensor Ambient Light Sensor •...

  • Page 9: Setup License For Terasic Multi-Touch Ip

    Setup License for Terasic Multi-Touch IP To utilize the multi-touch panel in a Quartus II project, the Terasic Multi-Touch IP is required for operation. Error messages will be displayed if the license file for the Multi-Touch IP is not added before compiling projects.

  • Page 10: Getting Help

    . Save the Quartus II license file. Getting Help Getting Help Here is information of how to get help if you encounter any problem: • Terasic Technologies • Tel: +886-3-550-8800 • Email: support@terasic.com...

  • Page 11: Chapter 2 Architecture

    Chapter 2 Architecture This chapter describes the architecture of the Video and Embedded Evaluation Kit – Multi-touch (VEEK-MT) including block diagram and components. Layout and Components Layout and Components The picture of the VEEK-MT is shown in Figure 2-1 Figure 2-2.

  • Page 12: Block Diagram Of The Veek-Mt-Mt

    Figure 2-2 VEEK-MT PCB and Component Diagram (Bottom) Block Diagram of the VEEK-MT Block Diagram of the VEEK-MT Figure 2-3 gives the block diagram of the VEEK-MT board. To provide maximum flexibility for the user, all connections are made through the Cyclone IV E FPGA device. Thus, the user can configure the FPGA to implement any system design.

  • Page 13: Using Veek-Mt

    Chapter 3 Using VEEK-MT This section describes the detailed information of the components, connectors, and pin assignments of the VEEK-MT. Configuring the Cyclone IV E FPGA Configuring the Cyclone IV E FPGA The Video and Embedded Evaluation Kit (VEEK-MT) contains a serial configuration device that stores configuration data for the Cyclone IV E FPGA.
  • Page 14 Figure 3-1 JTAG Chain Figure 3-2 JTAG Chain Configuration Header Configuring the FPGA in JTAG Mode Figure 3-3 illustrates the JTAG configuration setup. To download a configuration bit stream into the Cyclone IV E FPGA, perform the following steps: • Ensure that power is applied to the VEEK-MT •...
  • Page 15 Figure 3-3 JTAG Chain Configuration Scheme Figure 3-4 The RUN/PROG Switch (SW19) Set to JTAG Mode Configuring the EPCS64 in AS Mode Figure 3-5 illustrates the AS configuration set up. To download a configuration bit stream into the EPCS64 serial configuration device, perform the following steps: •...

  • Page 16: Bus Controller

    Figure 3-5 The AS Configuration Scheme Bus Controller Bus Controller The VEEK-MT comes with a bus controller using the Max II EPM240 that allows user to access the touch screen module through the HSMC connector. This section describes its structure in block diagram-form and its capabilities.

  • Page 17: Using The 7" Lcd Capacitive Touch Screen

    Using the 7” LCD Capacitive Touch Screen Using the 7” LCD Capacitive Touch Screen The VEEK-MT features a 7-inch capacitive amorphous TFT-LCD panel. The LCD touch screen offers resolution of (800x480) to provide users the best display quality for developing applications. The LCD panel supports 24-bit parallel RGB data interface.
  • Page 18 Vertical Valid Setup time Tdsu DATA Hold time Tdsu Table 3-2 Pin assignment of the LCD touch panel FPGA Pin Signal Name Description I/O Standard LCD_B0 LCD blue data bus bit 0 2.5V LCD_B1 LCD blue data bus bit 1 2.5V LCD_B2 LCD blue data bus bit 2...

  • Page 19: Using 5-Megapixel Digital Image Sensor

    LCD_UPDN Up / Down Display Control 2.5V LCD_VSD Vertical sync input. 2.5V TOUCH _I2C_SCL touch I2C clock 2.5V TOUCH _I2C_SDA touch I2C data 2.5V TOUCH _INT_n touch interrupt 2.5V Using 5 Megapixel Digital Image Sensor Using 5 Megapixel Digital Image Sensor The VEEK-MT is equipped with a 5 megapixel digital image sensor that provides an active imaging array of 2,592H x 1,944V.

  • Page 20: Using The Digital Accelerometer

    Using the Digital Accelerometer Using the Digital Accelerometer The VEEK-MT is equipped with a digital accelerometer sensor module. The ADXL345 is a small, thin, ultralow power assumption 3-axis accelerometer with high resolution measurement. Digitalized output is formatted as 16-bit twos complement and can be accessed either using SPI interface or I2C interface.

  • Page 21: Using Terasic Multi-Touch Ip

    Using Terasic Multi-Touch IP Using Terasic Multi-Touch IP Terasic Multi-Touch IP is provided for developers to retrieve user inputs, including multi-touch gestures and single-touch. The file name of this IP is i2c_touch_config and it is encrypted. To compile projects with the IP, users need to install the IP license first. For license installation, please refer to section 1.2 Setup License for Terasic Multi-Touch IP...
  • Page 22 0x3A West 0x3C North-West 0x3E Click 0x40 Zoom In 0x48 Zoom Out 0x49 Note: The Terasic Multi-Touch IP can also be found under the \IP folder in the system CD as well as the \IP folder in the reference designs.

  • Page 23: Veek-Mt Demonstrations

    Chapter 4 VEEK-MT Demonstrations This chapter gives detailed description of the provided bundles of exclusive demonstrations implemented on VEEK-MT. These demonstrations are particularly designed (or ported) for VEEK-MT, with the goal of showing the potential capabilities of the kit and showcase the unique benefits of FPGA-based SOPC systems such as reducing BOM costs by integrating powerful graphics and video processing circuits within the FPGA.

  • Page 24: Painter Demonstration

    VIP Video Out is used to display the display content. The display content is filled by NIOS II processor according to users’ input. For multi-touch processing, a Terasic Memory-Mapped IP is used to retrieve the user input, including multi-touch gesture and single-touch coordinates. Note, the IP is encrypted, so the license should be installed before compiling the Quartus II project.
  • Page 25 Figure 4-2 Block Diagram of the Painter Demonstration Demonstration Source Code • Project directory: Painter • Bit stream used: Painter.sof • Nios II Workspace: Painter \Software Demonstration Batch File Demo Batch File Folder: Painter \demo_batch The demo batch file includes the following files: •...
  • Page 26 • Figure 4-4 shows the photo when users paint in the canvas area. Figure 4-5 shows the phone when counter-clockwise rotation gesture is detected. Figure 4-6 shows the photo when zoom-in gesture is detected Figure 4-3 GUI of Painter Demo Figure 4-4 Single Touch Painting...
  • Page 27 Figure 4-5 Counter-clockwise Rotation Gesture Figure 4-6 Zoom-in Gesture Note: execute the test.bat under Picture_Viewer\demo_batch will automatically download the .sof and .elf file.

  • Page 28: Picture Viewer

    Picture Viewer Picture Viewer This demonstration shows a simple picture viewer implementation using Nios II-based SOPC system. It reads JPEG images stored on the SD card and displays them on the LCD. The Nios II CPU decodes the images and fills the raw result data into frame buffers in SDRAM. The VEEK-MT will show the image the buffer being displayed points to.
  • Page 29 Demonstration Setup Format your SD card into FAT16 format Place the jpg image files to the \jpg subdirectory of the SD card. For best display result, the image should have a resolution of 800x480 or the multiple of that Insert the SD card to the SD card slot on the VEEK-MT Load the bit stream into the FPGA on the VEEK-MT Run the Nios II Software under the workspace Picture_Viewer\Software (Note*) After loading the application you will see a slide show of pictures on the SD card.

  • Page 30: Video And Image Processing

    Video and Image Processing Video and Image Processing The Video and Image Processing (VIP) Example Design demonstrates dynamic scaling and clipping of a standard definition video stream in either National Television System Committee (NTSC) or Phase Alternation Line (PAL) format and picture-in-picture mixing with a background layer. The video stream is output in high resolution (800×480) LCD touch panel.
  • Page 31 A video source is input through an analog composite port on VEEK-MT which generates a digital output in ITU BT656 format. A number of common video functions are performed on this input stream in the FPGA. These functions include clipping, chroma resampling, motion adaptive deinterlacing, color space conversion, picture-in-picture mixing, and polyphase scaling.
  • Page 32 Demonstration Source Code • Project directory: VIP • Bit stream used: VIP.sof • Nios II Workspace: VIP\Software Demonstration Batch File Demo Batch File Folder: VIP\demo_batch The demo batch file includes the following files: • Batch File: VIP.bat, VIP_bashrc • FPGA Configuration File: VIP.sof •...

  • Page 33: Camera Application

    Figure 4-10 VIP Demonstration Figure 4-11 Setup for the VIP Demonstration Camera Application Camera Application This demonstration shows a digital camera reference design using the 5 megapixel CMOS sensor and 7-inch LCD modules on the VEEK-MT. The CMOS sensor module sends the raw image data to FPGA on the DE2-115 board, the FPGA on the board handles image processing part and converts the data to RGB format to display on the LCD module.
  • Page 34 As soon as the configuration code is downloaded into the FPGA, the I2C Sensor Configuration block will initial the CMOS sensor via I2C interface. The CMOS sensor is configured as follow: • Row and Column Size: 800 * 480 • Exposure time: Adjustable •...
  • Page 35 Demonstration Source Code • Project directory: Camera • Bit stream used: Camera.sof Demonstration Batch File Demo Batch File Folder: Camera\demo_batch The demo batch file includes the following files: • Batch File: test.bat • FPGA Configuration File: Camera.sof Demonstration Setup • Load the bit stream into FPGA by executing the batch file ‘test.bat’...

  • Page 36: Video And Image Processing For Camera

    On: Shorten the exposure time Mirror mode SW[17] HEX[7:0] Frame counter (Display ONLY) Figure 4-13 Screen Shot of the Camera Demonstration Video and Image Processing for Camera Video and Image Processing for Camera The Video and Image Processing (VIP) for Camera Example Design demonstrates dynamic scaling and clipping of a standard definition video stream in RGB format and picture-in-picture mixing with a background layer.
  • Page 37 running on a Nios® II processor. Nios II software demonstrates how to control the clocked video input, clocked video output, and mixer functions at run-time is also provided. The video system is implemented using the SOPC Builder system level design tool. This abstracted design tool provides an easy path to system integration of the video processing data path with a NTSC or PAL video input, VGA output, Nios II processor for configuration and control.
  • Page 38 Demonstration Source Code • Project directory: VIP_Camera • Bit stream used: VIP_Camera.sof • Nios II Workspace: VIP_Camera \Software Demonstration Batch File Demo Batch File Folder: VIP_Camera\demo_batch The demo batch file includes the following files: • Batch File: VIP_Camera.bat, VIP_Camera _bashrc •...

  • Page 39: Digital Accelerometer Demonstration

    Figure 4-15 Setup for the VIP_Camera demonstration Digital Accelerometer Demonstration Digital Accelerometer Demonstration This demonstration shows a bubble level implementation based on a digital accelerometer. We use C protocol to control the ADXL345 digital accelerometer, and the APDS-9300 Miniature Ambient Light Photo Sensor.
  • Page 40 Figure 4-16 Block Diagram of the Digital Accelerometer Demonstration Demonstration Source Code • Project directory: G_sensor • Bit stream used: G_sensor.sof • Nios II Workspace: G_sensor\Software Demonstration Batch File Demo Batch File Folder: G_sensor\demo_batch The demo batch file includes the following files: •...
  • Page 41 Figure 4-17 Digital Accelerometer Demonstration Note: Execute G_sensor \demo_batch\test.bat to download .sof and .elf files.

  • Page 42: Chapter 5 Application Selector

    Chapter 5 Application Selector The application selector utility is the default code that powers on the FPGA and offers a graphical interface on the LCD, allowing users to select and run different demonstrations that reside on an SD card. Ready to Run SD Card Demos Ready to Run SD Card Demos You can find several ready-to-run SD card demos in your SD card root directory as well as in the System CD under Factory_Recovery\Application_Selector folder.

  • Page 43: Running The Application Selector

    Running the Application Selector Running the Application Selector • Connect power to the VEEK-MT • Insert the SD card with applications into the SD card socket of VEEK-MT • Switch on the power (SW18) (1*) • Scroll to select the demonstration to load using the side-bar •...
  • Page 44 CFI Flash CFI flash is used to store the software binary files of applications. All software binary files used by the application selector contain a boot copier which is pre-ended by the Nios2-elf-objcopy utility during file conversion process described in the “Creating Your Own Loadable Applications” section. The boot copier copies the software code to program memory before running it.

  • Page 45: Restoring The Factory Image

    • nios2-elf-objcopy –O binary “your example.elf” “your example_SW.bin ”(4,5*) • Create a new subdirectory and name it what you would like the title of your application to be shown as in the application selector • Using an SD card reader, copy the directory onto an SD card into a directory named “Application_Selector”.
  • Page 46 • Convert Selector.sof file into Selector_HW.flash file • sof2flash --epcs –input= Selector.sof --output= Selector_HW.flash • Convert .flash file into .bin file • nios2-elf-objcopy –I srec –O binary Selector_HW.flash Selector_HW.bin • From the command shell navigate to where your ELF file is located and create your software bin image using the following command commands listed below •...
  • Page 47 Figure 5-2 Programming Flash settings...

  • Page 48: Chapter 6 Appendix

    Chapter 6 Appendix Revision History Revision History Version Change Log V1.0 Initial Version (Preliminary) Copyright Statement Copyright Statement Copyright © 2011 Terasic Technologies. All rights reserved.

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