Theory Of Operation - Vector Matrix printer User Manual

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Vector Graphic MP Ibt Matrix Printer
III.
THEORY OF OPERATION
3.1 Print wire firing
The firing of the 7 print wires are controlled by the 8 bit output of port
B.
The signal from output bits 1-7 (the character column bits) are each
presented to an input on a 7426 NAND gate (U3 and U8) and held there for a
predetermined time by the software.
Simultaneously, the 8th (most
significant) bit of Port B provides the strobe pulse needed to activate the
pulse width timer.
The pulse width timer (Vl) is used to regulate the timing of the print
wire solenoid actuation.
This is particularly impJrtant since print quality
is dependent upon a precise amount of energ}' being applied to the solenoids.
The strobe pulse from the 8th bit triggers the 555 timer to begin timing,
holding the output high.
Capacitor Cl begins charging.
If the voltage
present is slightly higher than normal, it will charge quickly and then turn
off the timer.
Conversely, if the voltage is lower than normal, Cl will
take longer to charge and the output of the timer will be held up longer.
Thus this timer is able to compensate for differences in supply voltage,
ensuring that the energy supplied to the print wire solenoids remains
constant no matter what the variation.
Transistor Ql is used to convert the
signal output of analog IC Vl to digital IC voltage levels while inverting
it at the same time.
This signal is again inverted through inverter on U5
and is presented to one of the inputs of the AND gate U2.
Due to mechanical considerations, two conditions have to be met before the
print wires can fire.
The print head has to be off the home position and
dot (column) timing has to be received.
This is taken care of by IC U4.
A signal indicating that the print head
is off the home position is received from the printer mechanism via J2-13.
This clears the 7474 flip-flop.
The dot timing from b'1e printer mechanism
clocks the Q output of the flip flop.
The Q signal is Jl.NCed at U2 with the
pulse from the pulse width timing circuit discussed above.
This resultant
signal is logically
~~Ced
wiG'1 the character column bits.
If both inputs
are high, the NAND gate pulls the print wire solenoid transistor base
10d,
permitting current to flow through the solenoid thereby firing print wire.
Diode, resistor and capacitor wired in series/parallel to the solenoid are
for arc suppression and current limitation.
3-1
Rev. 1-B
6/7/80

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