Sanyo VPC-HD1A Service Manual page 4

3. IC932 (V Driver)
A V driver (IC932) is necessary in order to generate the clocks
(vertical transfer clock and electronic shutter clock) which
driver the CCD.
In addition the XV1-XV8 signals which are output from IC102
are vertical transfer clocks, and the XSG signal is superim-
posed onto XV1, XV3, XV5 and XV7 at IC932 in order to gen-
erate a ternary pulse. In addition, the XSUB signal which is
output from IC102 is used as the sweep pulse for the elec-
tronic shutter.
VMSUB
13
3-level
OSUB 14
VL 8
41
VL
2-level
OV5R 26
2-level
OV7R 25
2-level
OV4 31
2-level
OV6 30
2-level
OV8 29
VM 12
VM 37
RESET 43
Level
SUBCNT 4
conversion
Level
SUB 5
conversion
VDC
6
Level
V8 50
conversion
Level
V6 46
conversion
Level
V4 45
conversion
Level
44
V2
conversion
Level
V7R 55
conversion
Level
V5R
54
conversion
Fig. 1-3. IC932 Block Diagram
4. IC931 (H Driver, CDS, AGC and A/D converter)
IC931 contains the functions of H driver, CDS, AGC and A/D
converter. As horizontal clock driver for CCD image sensor,
HØ1, HØ2, HØL and RG are generated inside, and output to
CCD.
The video signal which is output from the CCD is input to pin
(1) and pin (74) of IC931. There are sampling hold blocks
generated from the SHP and SHD pulses, and it is here that
CDS (correlated double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier (VGA: Variable Gain Amplifier). It
is A/D converted internally into a 14-bit signal, and is then
input to MOVIC (IC102). The gain of the VGA amplifier is con-
11
trolled by pins (4), (5), (6), (69), (70) and (71) serial signal
VHH
3-level
which is output from ASIC (IC101).
27 OV1B
3-level
28 OV1A
3-level
22 OV3B
3-level
23
OV3A
3-level
20 OV5B
3-level
21 OV5A
3-level
CCDIN_A
15
OV7B
3-level
19
OV7A
10 VH
CCDIN_B
38 VH
7 GND
H1A TO H4A
Level
62 CH8
conversion
H1B TO H4B
Level
63 CH4
conversion
Level
3 V7
conversion
Level
59 CH7
conversion
Level
60
CH3
conversion
Level
61 V5
conversion
Level
56 CH6
conversion
Level
57 CH2
conversion
Level
58 V3
conversion
Level
52 CH1
conversion
Level
53 V1
conversion
– 4 –
REFT_A REFB_A REFT_B
VREF_A VREF_B
VGA
CDS
0~18 dB
0~18 dB
CDS VGA
INTERNAL CLOCKS
RG_A
RG_B
PRECISION
4
HORIZONTAL
TIMING
DRIVERS
CORE
4
SYNC
GENERATOR
HD_A VD_A HD_B
Fig. 1-4. IC931 Block Diagram
REFB_B
AD9942
14
DOUT_A
ADC
CLAMP
CLAMP
14
DOUT_B
ADC
CLI_A
CLI_B
SCK_A
INTERNAL
REGISTERS
SCK_B
VD_B SL_A
SL_B
SDATA_A SDATA_B