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5. New adoption technology
[System control micom I001(M3062)]
Pin function table
No.
PIN MANE
VREF (+5.0V)
1
+5.0V
2
NC
3
OSD_DATA
4
OSD_CLK
5
6
HP_VOL
FE.AGC_O(M)
7
8
DATA_OUT(FC)
9
DATA_IN(FC)
10
CLK(FC)
EDID_PROTECT
11
TRAP_MAIN
12
GND
13
CNVSS(FLASH)
14
DSUB COMP
15
RGBSW
16
RESET
17
16MHz oscillation
18
GND
19
16MHz oscillation
20
+5.0V
21
NMI(+5.0V)
22
RMCON(AVC)
23
V.FREQ_2(VIDEO)
24
V.FREQ_1/3
25
SCV.SYNC
26
IRQ�PM-IRQ)
27
MCV.SYNC
28
POWER_LED
29
H.FREQ_2(VIDEO)
30
PDP_WVGA_LCD_SW_2
31
H.FREQ_1/_3
32
33
PDWN
RXD2
34
TXD2
35
TXD1(RS232C/FLASH)
36
37
RXD1(RS232C/FLASH)
38
39
SCLK(FLASH)
40
BUSY(FLASH)
41
TXD0(PDP)
42
RXD0(PDP)
43
SDA4(panel)
44
SCL4(panel)
45
M_ENABLE
46
M_SCLK
47
M_SDA
48
M_WAKEUP
49
PDPGO(PM_ON)
50
32PD7800/42PD7800 (PW2)
I/O
I
5V
I
5V
I/O
NC
I/O
OSD DATA
I/O
OSD CLK
I/O
Head Phone Volume
I/O
AGC Voltage(F/E)
I/O
FC DATA
I/O
FC DATA
I/O
FC CLOCK
I/O
Memory Protect
I/O
TRAP-MAIN
I
GND
I
CNVSS(FLASH)
I/O
SYNC-SW
I/O
SYNC-SW
I
RESET
O
OSC-OUT
I
GND
I
OSC-IN
I
5V
I
5V PULL UP
I/O
IR Signal
I/O
TA1370(LA7213), COMPONENT2
I/O
TA1370(LA7213), COMPONENT(Main)/ DSUB COMPONENT
I/O
CVBS for SYNC Detection(Sub Picture)
I/O
PANEL MODULE Condition(L:Normal,H:Erroe)
I/O
CVBS for SYNC Detection(Main Picture)
I/O
L�LED ON(Power Save)
I/O
TA1370(LA7213), COMPONENT2
I/O
PDP/42WVGA/LCD detection
I/O
TA1370(LA7213), COMPONENT1(Main), D-SUB
I/O
RESERVE(LVDS Power Down mode(PANEL))
I/O
DTT
I/O
DTT
I/O
DATA(RS-232C)
I
5V
I/O
DATA(RS-232C)
I
GND
I/O
CLOCK(FRASH MEMORY Writing)
I/O
BUSY(FRASH MEMORY Writing)
I/O
Ether Net
I/O
Ether Net
I/O
2
I
C-BUS Contorol DATA
I/O
2
I
C-BUS Contorol CLOCK
I/O
Media Enable
I/O
Media Clock
I/O
Media Data
I/O
Media Wakeup
I/O
PDP PALEL Contorol
FUNCTION
7
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