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Clock Generator Circuit
The clock generator circuit generates a l6-MHz clock and is used as the fundamental element for the system clock in the
CPU, the timing clock for the FDD to read/write data and the timing clock for the CRT.
The l6-MHz clock, generated by M37 (NAND gate) and the l6-MHz crystal oscillator, is transferred to the FOD interface
circuit and also transferred to M27 (SED9421C). This l6-MHz clock is divided by four by M27 and, passing through M14,
it
is transferred to the CPU as a 4-MHz clock. The CPU uses this clock as the system clock.
Also in M27, the l6-MHz clock is used as the timing clock to read/write data between the FDD. This l6-MHz clock is divided
by two by M47 and the divided 8-MHz clock is supplied to the pre-compensation circuit in the FDD interface. The timing
clock of the CRT isalso generated by this circuit.
The fundamental factor of character display is DCLK. DCLK is a timing signal which shows 1 dot on the CRT. Every eight
DCLK outputs one lOAD signal. lOAD is a timing signal which displays one character on the CRT.
There are two modes of character display; one is 40 characters per one line and the other is 80 characters per one line.
For the 80 characters mode, 1Q in M16 is set by the CPU and BOC becomes "l". Then Mll becomes preset so that the
16-MHz ciock passes through M34and M37, and is input into the elK terminal of M33 dIrectly.
For the 40 characters mode, at the gate of M34, BOC becomes "H" so that the 16-MHz clock is inhibited and divided by two
in Ml1, and input into the ClK terminal of M33.
Because of this logic, display time of one character in 80 characters mode becomes half of that in 40 characters mode.
DClK
2
M32
ClI<
•
G
5
14
0A
13
08
M33
2
12
0C
to CRCT ClK
NC
11
00
M37
n
Vee
,
"
"
5
a
ClR
D 2
C83
Jr
56P
Mn
6 b
PR
,
3
C:l<>----''---+_
M34
2
R24
1K
C44
25P
I
f-'~
r-+
046
33'
e51
r+r
220P
8M
>OM
5 Q
6
Q
D'
3
elK
M7
15
10
1D 14
DD
8
'DC
M>O
f6
CCK
STSWR
9
•
Figure 4-5. Clock Generator Circuit
4-5
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