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Aeroflex GR-UT699 User Manual

Aeroflex GR-UT699 User Manual

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GR-UT699
Development Board
User Manual
AEROFLEX GAISLER AB
Rev. 0.6, 2013-03-28

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Summary of Contents for Aeroflex GR-UT699

  • Page 1 GR-UT699 Development Board User Manual AEROFLEX GAISLER AB Rev. 0.6, 2013-03-28...
  • Page 2 Information furnished by Aeroflex Gaisler AB is believed to be accurate and reliable. However, no responsibility is assumed by Aeroflex Gaisler AB for its use, nor for any infringements of patents or other rights of third parties which may result from its use.

  • Page 3: Table Of Contents

    GR-UT699 Development Board User Manual TABLE OF CONTENTS INTRODUCTION......................7 Overview........................7 References........................9 Handling........................9 Abbreviations......................10 ELECTRICAL DESIGN....................11 Block Diagram......................11 UT699 ASIC....................... 11 Memory........................12 2.3.1 SRAM......................... 13 2.3.2 FLASH........................13 2.3.3 EEPROM........................13 2.3.4 MEMORY EXPANSION CONNECTOR..............13 CAN Interface......................14 2.4.1 Configuration of Bus Termination................14...

  • Page 4: List Of Tables

    GR-UT699 Development Board User Manual LIST OF TABLES Table 3-1: Default Status of Jumpers/Switches................27 Table 4-1: List of Connectors......................32 Table 4-2: J1 UART-1 - Serial Interface (RS232) connections .............34 Table 4-3: J2 RJ45-ETHERNET Connector...................34 Table 4-4: J3 ASIC– JTAG Connector ..................34 Table 4-5: J4A (upper connector) CANBUS-1 interface connections..........35...

  • Page 5: List Of Figures

    GR-UT699 Development Board User Manual LIST OF FIGURES Figure 1-1: GR-UT699 Development Board..................8 Figure 2-1: Block Diagram of GR-UT699 board................11 Figure 2-2: UT699 ASIC......................... 12 Figure 2-3: On-Board Memory Configuration.................13 Figure 2-4: Block Diagram of the CAN interface................14 Figure 2-5: Transceiver and Termination Configuration (one of 2 interfaces shown).....15 Figure 2-6: Transceiver and Termination of the SPW interfaces (2 of 4 interfaces shown)....16...
  • Page 6 GR-UT699 Development Board User Manual Intentionally Blank © Aeroflex Gaisler AB March 2013, Rev. 0.6...

  • Page 7: Introduction

    V8 Processor ASIC device. The UT699 is a Leon3FT based custom ASIC for Aerospace applications. The GR-UT699 Unit comprises a custom designed PCB with a 6U Compact PCI front panel, making the board suitable either for stand-alone bench top development, or for installation in a 6U High Compact PCI rack.

  • Page 8: References

    GR-UT699 Development Board User Manual One Serial UART interface (RS232) • Ethernet • JTAG - DSU • Two CAN bus interfaces • Four Spacewire interfaces • Serial DSU UART (Mini-AB USB connector) • 16 pins General Purpose I/O Port •...

  • Page 9: Handling

    GR-UT699 Development Board User Manual 1.3 Handling ATTENTION : OBSERVE PRECAUTIONS FOR HANDLING ELECTROSTATIC SENSITIVE DEVICES This unit contains sensitive electronic components which can be damaged by Electrostatic Discharges (ESD). When handling or installing the unit observe appropriate precautions and ESD safe practices.

  • Page 10: Electrical Design

    GR-UT699 Development Board User Manual ELECTRICAL DESIGN 2.1 Block Diagram The GR-UT699 board provides the electrical functions and interfaces as represented in the block diagram, Figure 2-1. POWER COMPACT PCI INTERFACE POWER & FLASH UT699RH EEPROM ASIC SDRAM SRAM SWITCHES...

  • Page 11: Memory

    GR-UT699 Development Board User Manual Figure 2-2: UT699 ASIC 2.3 Memory The memory configuration installed on the board is shown in the figure below comprising of: 80Mbit of SRAM memory, organised as 1 banks x 2Mword x 40 bits wide •...

  • Page 12: Sram

    User Manual 2.3.1 SRAM The GR-UT699 board is laid out with two SRAM memory banks but only has one bank mounted as standard. Each bank is made up of five CY7C1069AV33. These devices are 16Mbit (2Mbyte x 8 bit devices with 10 or 12 ns access times.

  • Page 13: Configuration Of Bus Termination

    GR-UT699 Development Board User Manual CAN_H CAN_L TRANSCEIVER TRANSCEIVER CAN_H CAN_L TRANSCEIVER TRANSCEIVER Figure 2-4: Block Diagram of the CAN interface 2.4.1 Configuration of Bus Termination The CAN interfaces on the board can be configured for either end node or stub-node operation by means of the jumpers JP3 and JP4 for interface 1 and 2 respectively, as shown in Figure 2-5.

  • Page 14: Configuration Of Slew Rate

    LVTTL (3.3V logic), LVDS driver and receiver circuits are required on the PCB to interface between the ASIC and the external interface. The PCB traces for the LVDS signals on the GR-UT699 board are laid out with 100-Ohm differential impedance design rules and matched trace lengths.

  • Page 15: Spwclk

    GR-UT699 Development Board User Manual The pin out and connector types for these Spacewire interfaces conform to the Spacewire standard, as shown in Figure 2-6. The inner shield pin (pin3 of the connector) is connected to DGND via a Zero-ohm resistor.

  • Page 16: Serial Interface

    2.7 Debug Support Unit (DSU) Serial Interface The GR-UT699 unit provides a interface for Debug and control of the processor by means of a host terminal via the DSU serial link to the UT699 ASIC, as represented in Figure 2-8.
  • Page 17 GR-UT699 Development Board User Manual normal use the DSU feature will always be enabled to allow processor control and program debugging via the DSU link. An LED is provided on the PCB to indicate the conditions of the DSUACT signal from the UT699 processor.

  • Page 18: Oscillators And Clock Inputs

    GR-UT699 Development Board User Manual 2.8 Oscillators and Clock Inputs The oscillator and clock scheme for the UT699 ASIC is shown in Figure 2-9. MEMORY EXPANSION MEMORY EXPANSION CONNECTOR CONNECTOR COAX CONNECTOR ZERO SYS CLK ZERO DELAY TBD MHz DELAY...

  • Page 19: Power Supply And Voltage Regulation

    2.10 Ethernet Interface The UT699RH ASIC device incorporates a Ethernet controller with support for MII interface, and the GR-UT699 Development Board has an Intel LXT971 10/100Mbit/s Ethernet PHY transceiver and RJ45 connector are on board. For more information on the registers and functionality of the Ethernet MAC+PHY device please refer to the data sheet for the WJLXT971A device.

  • Page 20: Pci Interface

    SYSTEM slot (HOST) or in PERIPHERAL slots (GUEST). The GR-UT699 board can be configured to operate either as a peripheral slot card or system slot card as described in the following sections.

  • Page 21: Host/System Slot Configuration

    GR-UT699 Development Board User Manual 2.11.1 Host/System Slot Configuration When installed in the System slot, the board provides the PCI arbitration and distributes the required PCI clocks to the backplane, and to the PCI interface in the FPGA. ASIC SYSEN...

  • Page 22: Peripheral Slot Configuration

    GR-UT699 Development Board User Manual necessary to ensure that this pin is driven by the host slot. This can be achieved by installing jumper JP18 on the board, so that the board system reset signal RESETN provides the drive for the PCIRSTN signal. If the jumper is not installed, a weak (22k) pull up will pull the PCIRSTN signal high.

  • Page 23: Other Interfaces And Circuits

    GR-UT699 Development Board User Manual 2.12 Other Interfaces and Circuits 2.12.1 GPIO The 16 general Purpose Input Output signals of the ASIC (3.3V LVTTL voltage levels) are connected to a set of 0.1” pitch pin header connector on the front panel thus allowing easy access to these signals.

  • Page 24: Jtag Interface

    I/O space of the UT699 processor. Figure 2-16, shows the pin numbering scheme as implemented on the GR-UT699 Board. © Aeroflex Gaisler AB...

  • Page 25: Figure 2-16: Mezzanine Connector Pin Number Ordering

    GR-UT699 Development Board User Manual Figure 2-16: Mezzanine Connector Pin Number Ordering Please note that this pin ordering does not match exactly the pin ordering which you will find on the Tyco part datasheets for the Mezzanine board mating connectors. The reason for this is explained in more detail in the Technical Note, RD-4.

  • Page 26: Setting Up And Using The Board

    GR-UT699 Development Board User Manual SETTING UP AND USING THE BOARD The default status of the Jumpers on the boards is as shown in table Figure 3-1. In this configuration the board is set up as a PCI Host. For the meaning of the various jumpers, refer to Table 4-23 and RD 1.
  • Page 27 GR-UT699 Development Board User Manual To perform software download and debugging on the processor, a link from the Host computer to the DSU interface of the board is necessary. A connection to the DSU of the board can be made using a USB cable (Type-A to Mini-AB connectors) from the Host PC to the USB-DSU connector on the front panel.

  • Page 28: Figure 3-1: Grmon Output Screenshot #1

    GR-UT699 Development Board User Manual Figure 3-1: GRMON Output Screenshot #1 © Aeroflex Gaisler AB March 2013, Rev. 0.6...

  • Page 29: Figure 3-2: Grmon Output Screenshot #2

    GR-UT699 Development Board User Manual Figure 3-2: GRMON Output Screenshot #2 © Aeroflex Gaisler AB March 2013, Rev. 0.6...

  • Page 30: Interfaces And Configuration

    GR-UT699 Development Board User Manual INTERFACES AND CONFIGURATION 4.1 List of Front/Back Panel Connectors Name Function Type Description UART-1 D9-S (Female) Connections for Serial UART-1 (RS232) ETHERNET RJ45 10/100Mbit/s Ethernet Connector JTAG 2x7pin 2mm header JTAG signal interface CANBUS-1 Dual D9-P (male)

  • Page 31: Figure 4-1: Front Panel View (Pin 1 Of Connectors Marked)

    GR-UT699 Development Board User Manual Figure 4-1: Front Panel View (pin 1 of connectors marked) © Aeroflex Gaisler AB March 2013, Rev. 0.6...

  • Page 32: Table 4-2: J1 Uart-1 - Serial Interface (Rs232) Connections

    GR-UT699 Development Board User Manual Name Comment No connect No connect TXD-1 Transmit pin No connect RXD-1 Receive pin No connect No connect No connect Ground Table 4-2: J1 UART-1 - Serial Interface (RS232) connections Name Comment TPFOP Output +ve...

  • Page 33: Table 4-5: J4A (Upper Connector) Canbus-1 Interface Connections

    GR-UT699 Development Board User Manual Name Comment No connect Ground CAN1_L CAN Dominant Low CAN1_H CAN Dominant High Ground No connect No connect No connect CANSHD1 Shield Table 4-5: J4A (upper connector) CANBUS-1 interface connections Name Comment No connect DGND...

  • Page 34: Table 4-8: J6 Spw-1 Interface Connections

    GR-UT699 Development Board User Manual Name Comment DIN1+ Data In +ve DIN1- Data In -ve SIN1+ Strobe In +ve SIN1- Strobe In -ve SHIELD Inner Shield SOUT1+ Strobe Out +ve SOUT1- Strobe Out -ve DOUT1+ Data Out +ve DOUT1- Data Out -ve...

  • Page 35: Table 4-11: Expansion Connector J9 Pin-Out (See Section 2.12.5 For Pin Order)

    GR-UT699 Development Board User Manual FUNCTION ASIC pin CONNECTOR PIN ASIC pin FUNCTION DGND DGND DGND DGND -12V -12V DGND DGND +12V +12V DGND DGND +3.3V +3.3V DGND DGND +3.3V +3.3V DGND DGND +3.3V +3.3V DGND DGND +3.3V +3.3V DGND...

  • Page 36: Table 4-12: J10 Pio Header Pin Out

    GR-UT699 Development Board User Manual FUNCTION ASIC pin CONNECTOR PIN FUNCTION ■ □ GPIO0 DGND □ □ GPIO1 DGND □ □ GPIO2 DGND □ □ GPIO3 DGND □ □ GPIO4 DGND □ □ GPIO5 DGND □ □ GPIO6 DGND □ □...

  • Page 37: Table 4-14: J12 Dsu-Serial Over Usb Miniab

    GR-UT699 Development Board User Manual Name Comment +5V Power Data Negative Data Positive Identifier Ground Table 4-14: J12 DSU-Serial over USB MiniAB Name Comment Inner Pin, 5V, typically TBD A Outer Pin Return Table 4-15: J13 POWER – External Power Connector...

  • Page 38: Table 4-17: Sodimm Socket J15 Pin-Out

    GR-UT699 Development Board User Manual FUNCTION ASIC PIN CONNECTOR PIN ASIC PIN FUNCTION DGND DGND +3.3V +3.3V DGND DGND SDDQM3 SDDQM0 SDDQM2 SDDQM5 / pulled high +3.3V +3.3V DGND DGND +3.3V +3.3V DGND DGND SDCLK0 SDCKE0/ pulled high +3.3V +3.3V...

  • Page 39: List Of Oscillators, Switches And Led's

    GR-UT699 Development Board User Manual 4.2 List of Oscillators, Switches and LED's Name Function Description OSC_MAIN Main oscillator for ASIC DIL8 socket, 3.3V (75MHz as standard) OSC_ETH Oscillator for Ethernet PHY transceiver, SMD type, 3.3V, 25.000MHz OSC_SPW DIL8 socket for user installed SPW Clock Oscillator, 3.3V...

  • Page 40: List Of Jumpers

    GR-UT699 Development Board User Manual FUNCTION ASIC pin OPEN SWITCH CLOSED PIO8 PIO9 PIO10 PIO11 PIO12 PIO13 PIO14 PIO15 Table 4-22: DIP Switch S4 'PIO[15..8]' definition 4.3 List of Jumpers Name Function Type Description CONFIG 4x2 pin 0.1” Header Header for DSU, PROM and WDOG enable ETH_INTR 2 pin 0.1”...

  • Page 41: Figure 4-2: Pcb Top View

    GR-UT699 Development Board User Manual Figure 4-2: PCB Top View © Aeroflex Gaisler AB March 2013, Rev. 0.6...

  • Page 42: Figure 4-3: Gr-Ut699 Assembly Photo

    GR-UT699 Development Board User Manual Figure 4-3: GR-UT699 Assembly Photo © Aeroflex Gaisler AB March 2013, Rev. 0.6...

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