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Concurrent Technologies VP 110/01x VME Pentium III-M Single Technical Reference Manual

Vp 110/01x vme pentium iii-m single
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Concurrent Technologies Inc
3840 Packard Road
Suite 130
Ann Arbor, MI 48108
USA
Tel: (734) 971 6309
Fax: (734) 971 6350
E-mail: info@gocct.com
Technical Reference Manual
for VP 110/01x
VME Pentium
Board Computer
Manual Order Code 550 0014 Rev 02
Concurrent Technologies Plc
4 Gilberd Court
Newcomen Way
Colchester, Essex CO4 9WN
United Kingdom
Tel: (+44) 1206 752626
Fax: (+44) 1206 751116
http://www.gocct.com
®
III-M Single
August 2002

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Summary of Contents for Concurrent Technologies VP 110/01x VME Pentium III-M Single

  • Page 1 VP 110/01x ® VME Pentium III-M Single Board Computer Manual Order Code 550 0014 Rev 02 August 2002 Concurrent Technologies Inc Concurrent Technologies Plc 3840 Packard Road 4 Gilberd Court Suite 130 Newcomen Way Ann Arbor, MI 48108 Colchester, Essex CO4 9WN...
  • Page 2 Concurrent Technologies reserves the right to change specifications at any time without notice. Concurrent Technologies assumes no responsibility either for the use of this document or for any infringements of the patent or other rights of third parties which may result from its use. In particular, no license is either granted or implied under any patent or patent rights belonging to Concurrent Technologies.
  • Page 3 BIST · · · · · Built In Self Test BSB· · · · · · Back Side Bus CCT· · · · · · Concurrent Technologies CPU · · · · · Central Processing Unit CRT· · · · · · Cathode Ray Tube DDC ·...

  • Page 4: Notational Conventions

    NOTATIONAL CONVENTIONS NOTE Notes provide general additional information. WARNING Warnings provide indication of board malfunction if they are not observed. CAUTION Cautions provide indications of board or system damage if they are not observed. VP 110/01x...
  • Page 5 Revision Revision History Date Initial Release July 2002 Added clarifications to several sections August 2002 VP 110/01x...

  • Page 6: Table Of Contents

    Table of Contents Introduction and Overview · · · · · · · · · · · · · · · · · General · · · · · · · · · · · · · · · · ·...
  • Page 7 ROM Disk · · · · · · · · · · · · · · · · · · · · · · · · · RAM Disk · · · · · · · · · · · ·...
  • Page 8 10.2.1 Slot Numbering · · · · · · · · · · · · · · · · · · · · · · · 10-1 10.2.2 VSA Console Devices· · · · · · · · · · ·...
  • Page 9 11.2.33 Test 64: PC Keyboard Test· · · · · · · · · · · · · · · · · · · 11-17 11.2.34 Test 68: Real Time Clock Test· · · · · · · · · ·...
  • Page 10 B.3.1 Layout · · · · · · · · · · · · · · · · · · · · · · · · · · B.3.2 Pin-out Tables · · · · · · · · · ·...

  • Page 11: Table Of Figures

    Table of Figures Figure 1-1 Overview · · · · · · · · · · · · · · · · · · · · · · · · Figure 2-1 Default Jumper and Switch Settings · · · ·...
  • Page 12 Table of Tables Table 1-1 VME P2 Breakout Interfaces · · · · · · · · · · · · · · · · · · Table 5-1 VME Address Capture Read Register· · · · · · · ·...

  • Page 13: Introduction And Overview

    General This manual is a guide and reference handbook for engineers and system integrators who wish to use the Concurrent Technologies’ VP 110/01x ultra high-performance Pentium III Processor-M (Pentium III-M) single board computer. The board has been designed for high-speed multiprocessing applications using a PC-AT™ architecture operating in a VME Bus environment.

  • Page 14: The Vp 110/01X - Main Features

    Introduction and Overview The VP 110/01x - Main Features The VP 110/01x is a member of the Concurrent Technologies range of single-board computers for the VME bus architecture. It has been designed as a powerful single board computer based upon the Pentium III Processor-M (Pentium III-M) incorporating the following features: up to 1 Gbyte 133MHz SDRAM two IEEE P1386.1 PMC sites...

  • Page 15: Sdram

    Introduction and Overview 1.2.4 SDRAM The on-board SDRAM operates at 133MHz and features ECC data protection. The board is fitted with 512 Mbytes of soldered-on SDRAM. A 144-pin SODIMM socket is provided for memory expansion. This accepts a standard PC133 SDRAM module having a capacity up to 512 Mbytes.

  • Page 16: 1.2.14 Floppy Disk

    Introduction and Overview 1.2.14 Floppy Disk A floppy disk interface is provided by the Super I/O Controller for up to two floppy drives and is connected via the P2 connector. 1.2.15 Serial Communication The VP 110/01x has one RS232 serial data communication channel, accessible via a front panel mounted RJ45 connector.

  • Page 17: Additional Board Options

    Introduction and Overview Additional Board Options Two on-board mass storage options are available, namely; A 2.5” EIDE hard disk drive of at least 10 Gbyte capacity. ® ™ A CompactFlash carrier that supports the IBM Microdrive Only one of these mass storage options may be fitted at a time. Refer to the VP 110/01x datasheet for ordering information.
  • Page 18 Introduction and Overview This page has been left intentionally blank VP 110/01x...

  • Page 19: Hardware Installation

    Hardware Installation General This chapter contains general information on unpacking and inspecting the VP 110/01x after shipment, and information on how to configure board options and install the board into a VME chassis. CAUTION It is strongly advised that, when handling the VP 110/01x and its associated components, the user should at all times wear an earthing strap to prevent damage to the board as a result of electrostatic discharge.

  • Page 20: Unpacking And Inspection

    Once unpacked, the board should be inspected carefully for physical damage, loose components etc. In the event of the board arriving at the customer’s premises in an obviously damaged condition, Concurrent Technologies or its authorized agent should be notified immediately.

  • Page 21: Default Jumper Settings

    Hardware Installation Default Jumper Settings VGA Console Mode Section 6.1 & 6.2 Not Used Mode - BIOS Section 9.1 User Switch - ‘1’ Section 8.1 Front Panel Switch Function - Reset Watchdog - Disabled Section 8.4 Section 2.4.6 LK4 PMC V(I/O) LK3 SRAM LK5 CMOS Clear LK2 Flash Program...

  • Page 22: Front Panel Indicators And Controls

    Hardware Installation Front Panel Indicators and Controls When installing or removing the board for the first time, or when checking it’s operation, it can be very useful to note the behavior of the LEDs on the front panel. Figure 2-2 shows the location of the LEDs, and their purpose is outlined below.

  • Page 23: External Reset

    Hardware Installation Switch 3 - Front Panel Switch Function ON - Reset (Default) OFF - No Action Switch 4 - Front Panel Switch Function ON - NMI OFF - No Action (Default) Figure 2-3 Front Panel Reset and NMI Switch Selecting the Reset jumper position will cause the board to be reset when the front panel switch is operated.

  • Page 24: Installation Of On-Board Mass Storage

    Hardware Installation Installation of On-Board Mass Storage If an on-board mass storage option has been ordered, it will be necessary to install the option at this time. The mass storage option plugs into the 44-way header S1 and is secured via screws and spacers using the four mounting holes as shown in Figure 2-4 below.

  • Page 25: Hard Disk Storage Kit (Ad Cp1/Dr1)

    Hardware Installation 2.5.1 Hard Disk Storage Kit (AD CP1/DR1) The option kit comprises: A 2.5” EIDE disk drive. A ribbon cable assembly. Four M3 x 10mm screws. Four M3 x 5mm spacers. The ribbon cable assembly has a 50-way connector at one end and a 44-way connector at the other end.

  • Page 26: Compactflash Storage Kit (Ad 200/001)

    Hardware Installation 2.5.2 CompactFlash Storage Kit (AD 200/001) The option kit comprises: A CompactFlash carrier module. Four M3 panhead screws. CompactFlash Carrier Module CompactFlash Sites Site 1 Site 2 Pillars Figure 2-6 CompactFlash Carrier Module Installation The M3 panhead screws may be loosely screwed into the end of the pillars, if so unscrew them.

  • Page 27: Adding Or Replacing Dram Modules

    Hardware Installation Adding or Replacing DRAM Modules The VP 110/01x accepts standard 144-pin SODIMM modules fitted with 3.3V PC133 DRAM. One socket is provided and will accommodate SODIMMs of 256 Mbytes and 512 Mbytes capacities. NOTE SODIMMs using 256Mbit DRAMs with 8K refresh are required. Figure 2-7 shows shows the way in which SODIMMs are fitted or removed.

  • Page 28: Installing And Replacing The Battery

    Hardware Installation Installing and Replacing the Battery The on-board Real-Time Clock, CMOS memory and Non-volatile SRAM are powered by a 3.3V Lithium battery when the board is powered off. It is advisable, though not essential, for the battery to be fitted prior to using the board. Figure 2-8 shows how to do this. One battery is supplied with the board, but it is not normally fitted.
  • Page 29 Hardware Installation CAUTION When replacing the battery, proper anti-static precautions must be observed. WARNING Dispose of battery properly. DO NOT BURN. If the battery is disconnected with out any other power, the date and time settings will need to be initialized and SRAM data will be lost.

  • Page 30: Installing Or Removing A Pmc Module

    Hardware Installation Installing or Removing a PMC Module Before installing a PMC module, check that the VP 110/01x board PMC V(I/O) voltage is configured to match the requirements of the PMC module. If two PMC modules are fitted, their V(I/O) requirements must be the same. CAUTION If the VP 110/01x is not correctly configured to match the PMC module V(I/O) requirements, it may result in damage to the module or the VP 110/01x.

  • Page 31: Figure 2-10 Pmc V(I/O) Jumper

    Hardware Installation 3.3V V(I/O) Key LK4 PMC V(I/O) 5V = or 5V keys or 3.3V key 3.3V = 5V V(I/O) Key Figure 2-10 PMC V(I/O) Jumper VP 110/01x 2-13...

  • Page 32: Installing The Board In A Vme Backplane

    If power-up does not follow the sequence described above this will indicate that the board is not operational. NOTE This sequence of events assumes the VP 110/01x has Concurrent Technologies standard BIOS firmware and that the board is configured to the factory setting described in Section 2.3.

  • Page 33: Software Installation

    Software Installation In most cases, installing operating system software on the VP 110/01x board follows the same sequence as installing on a PC. However, there are some additional points to note. The sections below summarize the special actions required for a few common operating systems. All but VxWorks require that a PMC VGA adapter is fitted for the duration of the installation process.

  • Page 34: Bootloading From Cd-Rom

    Software Installation Bootloading from CD-ROM Operating systems which install on the target hardware will generally install from CD-ROM, or may require both a CD-ROM and floppy disk. Bootloading from floppy disk requires no special steps other than to connect the drive using an appropriate cable. To bootload from CD-ROM, use the following procedure: While the BIOS is running its memory test, press the <ESC>...

  • Page 35: Installing Windows Nt

    Software Installation ® Installing Windows NT To install Windows NT from CD-ROM, set up the board initially using the steps outlined in Sections 3.1 and 3.2 above, ensuring that all the necessary drives are connected. Then follow the procedure below. Obtain the Ethernet driver from the Intel web site, starting from the following address: http://developer.intel.com/design/network/drivers and selecting the 82551ER and 82559ER NDIS4 drivers.

  • Page 36: Installing Windows ® 2000

    Software Installation ® Installing Windows 2000 To install Windows 2000 from CD-ROM, set up the board initially using the steps outlined in Sections 3.1 and 3.2 above, ensuring that all the necessary drives are connected. Then follow the procedure below. Obtain the Ethernet driver from the Intel web site, starting from the following address: http://developer.intel.com/design/network/drivers and selecting the 82551ER and 82559ER NDIS4 drivers.

  • Page 37: Installing Redhat ® Linux

    Software Installation ® ® Installing RedHat Linux To install RedHat Linux 7.2 from CD-ROM, set up the board initially using the steps outlined in Sections 3.1 and 3.2 above, ensuring that all the necessary drives are connected. Then follow the procedure below. Follow the standard RedHat installation instructions, but at the screen following the selection of monitor type, ensure that a “Text”...

  • Page 38: Using Vxworks 5.4 With Tornado

    Software Installation Using VxWorks 5.4 with Tornado 2 Applications using this operating system are not developed on the target hardware. Concurrent Technologies can supply on request a separate Board Support Package (BSP) for this board and many others. Read the “readme” file provided with this package for details of how to configure and run VxWorks on the VP 110/01x board.

  • Page 39: Mass Storage Interfaces

    Mass Storage Interfaces The VP 110/01x board has three interfaces which can be used to attach mass storage devices: a floppy disk interface is accessible via the VME P2 connector. a Primary EIDE (ATA100) interface is accessible via the VME P2 connector. a Secondary EIDE (ATA100) interface supporting on-board Mass Storage option kits.

  • Page 40: Eide Interfaces

    Mass Storage Interfaces EIDE Interfaces The board supports two EIDE (ATA100) interfaces. The Primary EIDE interface connects via the CompactPCI J5 connector of the PP 110/01x board, or through the Transition Module. Up to two EIDE peripherals may be connected to this interface.

  • Page 41: Rom Disk

    Mass Storage Interfaces ROM Disk The BIOS can optionally provide a ROM disk, which uses the Application Flash Memory to store user code and data in a robust, but easily accessible format. Either Drive A: or B: may be configured as a ROM disk via the BIOS Setup screen: Main|ROM/RAM Disk (A:) or Main|ROM/RAM Disk (B:).

  • Page 42: Ram Disk

    Mass Storage Interfaces RAM Disk The BIOS can optionally provide a RAM disk, which uses the Battery-Backed SRAM to store user code and data in a robust, but easily accessible format that is also writeable without the need to erase and program flash memory. Drive B: may be configured as a RAM disk via the BIOS Setup screen: Main|ROM/RAM Disk (B:).

  • Page 43: Vme Bus Interface Features

    VME Interface The VP 110/01x board is fitted with a Tundra Universe II PCI-to-VME bus bridge device together with additional support logic. This hardware implements a flexible interface to and from the VME bus with the following key characteristics. VME Bus Interface Features The VP 110/01x can be programmed as a VME master supporting off-board VME memory addressing accessible by any PCI bus master.

  • Page 44: Vme Byte Swapping

    VME Interface VME Byte Swapping The VP 110/01x provides hardware that performs fast byte swapping for aligned D16, D32 and D64 VME transfers. Byte swapping can be enabled separately for master and slave transfers under software control, using Status & Control Register 0 (see Section 9.1 for further details). Swapping is performed as follows:- D16 (Double Byte 2 - 3): D[31...24]...

  • Page 45: Vme Bus Error Interrupt

    VME Interface VME Bus Error Interrupt The VP 110/01x contains hardware to detect bus errors for VME bus cycles in which the Universe is the bus master. The hardware is controlled by Status and Control Register 1 (see Section 8.3). The bus error interrupt is connected to the Universe LINT0 interrupt, so software to deal with the VME bus error interrupt can be added to the normal Universe interrupt handler.

  • Page 46: Table 5-1 Vme Address Capture Read Register

    VME Interface 5.4.1 VME Address Capture Read Register (Read Only) |________|________|_________|________|_________|_________|_________|_________| CAPTURE STATUS Bit 3-0: Captured Address The VME address is sequentially read as follows following a captured bus error event. Read Cycle LWORD AM05 AM04 AM03 AM02 AM01 AM00 Table 5-1 VME Address Capture Read Register The sequence will repeat for subsequent read accesses and is only readable after a bus error address capture.

  • Page 47: Table 5-2 Vme Address Modifier Codes

    VME Interface AM05 AM04 AM03 AM02 AM01 AM00 Access Type A64 64-bit MBLT A64 single transfer A64 BLT A64 lock command (LCK) A32 lock command (LCK) A32 non-privileged 64-bit MBLT A32 non-privileged data A32 non-privilege program A32 non-privileged BLT A32 supervisory 64-bit MBLT A32 supervisory data A32 supervisory program A32 supervisory BLT...

  • Page 48: Table 5-2 Vme Address Modifier Codes (Continued)

    VME Interface AM05 AM04 AM03 AM02 AM01 AM00 Access Type A16 non-privileged A16 lock command (LCK) A16 supervisory Control/Status register A24 lock command (LCK) A24 non-privileged 64-bit MBLT A24 non-privileged data A24 non-privileged program A24 non-privileged BLT A24 supervisory 64-bit MBLT A24 supervisory data A24 supervisory program A24 supervisory BLT...

  • Page 49: Figure 6-1 Console Mode Switch

    Other Interfaces Many additional standard interfaces are provided on the VP 110/01x board. These interfaces consist primarily of those found in a regular desktop or mobile PC, and are outlined below. Serial Port A single RS232 serial interface is provided, and connects via the front panel The front panel connector is an RJ45 type, and an adapter cable is required to convert to a D-type connector of the appropriate size and gender.

  • Page 50: Keyboard And Mouse Ports

    Other Interfaces Keyboard and Mouse Ports A single 8-way x 0.1 inch, board mounted header provides connections for a PC keyboard and a PS/2 mouse. The pin-out of the front panel connector is detailed in Section A.5.4. Power for the keyboard and mouse interfaces is protected by a 0.75A self-resetting current limiting circuit.
  • Page 51 Other Interfaces Ethernet Controllers The VP 110/01x supports two 10/100Mbits Ethernet interfaces via two RJ45 connectors on the front panel. The interfaces are provided by two Intel 82559ER devices. These interfaces are pre-configured in the factory with unique IEEE addresses which are identified by two labels fixed to the board.

  • Page 52: Real-Time Clock

    Other Interfaces Real-Time Clock A conventional PC Real-Time Clock is included on this board. This is Year 2000 compliant and can be powered by an additional Lithium battery when main power to the board is removed. See Section 2.7 for more details of how to fit or replace the battery. The Clock device also provides 256 bytes of CMOS RAM, in which the PC BIOS keeps much of its setup screen data and other information.

  • Page 53: Universal Serial Bus (Usb)

    Other Interfaces Universal Serial Bus (USB) A single USB 1.0 interface is provided on this board, and is accessed via the VME P2 connector or a Breakout Module. This channel can operate at 1.5Mbits/s or 12Mbits/s. VP 110/01x...

  • Page 54: Power On Self Test Led/Speaker

    Other Interfaces Power On Self Test LED/Speaker The Power On Self Test (POST) LED is connected to the PC Speaker port. The LED will light when the speaker port is driven. The VP 110/01x is not fitted with an audio/speaker output. VP 110/01x...

  • Page 55: Figure 7-1 Memory Map

    Memory The board supports several combinations of the following memory: SDRAM BIOS/VSA Flash EPROM StrataFlash EPROM Battery backed SRAM The specific memory provision is determined by suffixes to the part number. FFFFFFFFh 512K BIOS/VSA Flash EPROM FFF80000h 512K SRAM/Strata Flash EPROM FFF00000h Unused FFE00000h...
  • Page 56 Memory SDRAM The VP 110/01x board supports a large amount of ECC SDRAM. 512 Mbytes is soldered onto the board, and a single 144-pin SODIMM site allows an additional 256 Mbytes or 512 Mbytes to be fitted either at the factory or in the field, giving a maximum size of 1 Gbyte. Section 2.6 describes how to fit this SODIMM, and details the types supported.

  • Page 57: Flash Eprom

    PC BIOS firmware. This EPROM will not normally be reprogrammed by the user, but Concurrent Technologies has programming software which allows BIOS updates to be carried out in the field when necessary, perhaps to add new features. Contact Concurrent Technologies for a copy of this software, and for the BIOS reprogramming information, if you believe that such an update is required.

  • Page 58: Figure 7-2 Flash Program Jumper

    Memory Application Flash EPROM The board is fitted with between 16 and 64 Mbytes of Intel StrataFlash EPROM which is free for use by application software. The memory is connected to the CSB5 X-Bus interface and is accessible in protected mode via a paged 512 Kbyte window (refer to Figure 7-1). This window is shared with the battery backed SRAM.

  • Page 59: Figure 7-3 Sram Backup Power Jumper

    Memory Battery backed SRAM The board can be fitted with 512K to 2 Mbytes of Static RAM. This SRAM is non volatile as data can be automatically retained via the on-board battery when the board is not powered. The memory is connected to the CSB5 X-Bus interface and is accessible via a paged 512 Kbyte window (refer to Figure 7-1).
  • Page 60 Memory This page has been left intentionally blank VP 110/01x...

  • Page 61: Table 8-1 I/O Address Map

    Additional Local I/O Functions The VP 110/01x supports a variety of I/O functions whose addresses are summarized in Table 8-1. I/O Address Range Description 0000-000Fh Master DMA Controller (CSB5 LPC host) 0020-0021h Master Interrupt Controller (CSB5) 002E-002Fh Configuration Index & Data Registers (Super I/O) 0040-0043h Timers 0-2 (CSB5) 0060h...
  • Page 62 Additional Local I/O Functions There are 13 byte wide status and control registers. They are accessed at the following I/O addresses: 210h for Status & Control Register 0; 211h for Status & Control Register 2; 212h for Status & Control Register 1; 213h for VME Address Capture Data &...

  • Page 63: Status & Control Register 0 (I/O Address 210H)

    Additional Local I/O Functions Status & Control Register 0 (I/O address 210h) |________|________|_________|________|_________|_________|_________|_________| CONSOLE USER BYTE BYTE BYTE BOARD BOARD BOARD SWITCH SWITCH SWAP SWAP SWAP REV 2 REV 1 REV 0 Bits 2 - 0: Hardware Revision Strapping (Read Only) 000 = Rev A 001 = Rev B Etc...

  • Page 64: Status & Control Register 2 (I/O Address 211H)

    Additional Local I/O Functions Status & Control Register 2 (I/O address 211h) NOTE Bit 4 of this register is device locked. |________|________|_________|________|_________|_________|_________|_________| PC BUS BIOS THERM SPEED CLOCK ALERT STEP UNLOCK UNLOCK UNLOCK UNLOCK SELECT ENABLE Bits 3 - 0: Device Lock (Write Only) These bits control the Device Lock function.

  • Page 65: Status & Control Register 1(I/O Address 212H)

    Additional Local I/O Functions Status & Control Register 1(I/O address 212h) |________|________|_________|________|_________|_________|_________|_________| FRONT UNIVERSE VME BUS VME BUS PANEL LINT1 ERROR ERROR EXP’N EXP’N SITE 2 SITE 1 FLAG INTERRUPT SLOT 2 SLOT 1 ENABLE Bits 3 - 0: PMC Mode 1 Status of PMC Modules (Read Only) Bit 0 and 1 = On Board PMC Site 1 &...

  • Page 66: Figure 8-1 Watchdog Timer Switch

    Additional Local I/O Functions Watchdog Timer The VP 110/01x board includes a hardware Watchdog timer which can be used by the operating software to monitor the normal operation of the system. The timer is enabled by a board switch (see Figure 8-1) and controlled by software. Once enabled it must be restarted at regular intervals.

  • Page 67: Watchdog Status & Control Register (I/O Address 214H)

    Additional Local I/O Functions 8.4.1 Watchdog Status & Control Register (I/O address 214h) |________|________|_________|________|_________|_________|_________|_________| SYSTEM ENABLE STATUS RESET ENABLE LINK RESET ENABLE Bits 1- 0: Watchdog Restart Bits (Read/Write) Refer to the following description on watchdog configuration. Bit 2: Select Watchdog Action (Read/Write) This bit selects the following actions when the watchdog times out.

  • Page 68: Watchdog Configuration

    Additional Local I/O Functions 8.4.2 Watchdog Configuration The watchdog circuitry contains features to safeguard against accidental use through faulty or unintended software actions. To enable the watchdog the following sequence of events needs to be performed. Read the watchdog register. Check the status of the watchdog enable jumper (bit 4). If it reads ‘low’...
  • Page 69 Additional Local I/O Functions 8.4.4 Programming the Watchdog The following functions show how to use the watchdog facility available through the Status and Control registers. It is worth noting that the Software Enable bit in the Watchdog Status and Control register does not read back the value last written;...
  • Page 70 Additional Local I/O Functions bTemp = inbyte (WATCHDOG_STATCTL); bTemp &= ~WD_ACTION_MASK; /* set watchdog action to NMI */ bTemp |= WD_ACTION_NMI; bTemp &= ~WD_SW_ENABLE; /* software disable the watchdog */ outbyte (WATCHDOG_STATCTL, bTemp | WD_PAT_1); /* set and pat twice */ outbyte (WATCHDOG_STATCTL, bTemp | WD_PAT_2);...

  • Page 71: Status & Control Register 4 (I/O Address 215H)

    Additional Local I/O Functions Status & Control Register 4 (I/O address 215h) |________|________|_________|________|_________|_________|_________|_________| PMC SITE PMC SITE BATTERY BANK BANK STATUS SELECT 1 SELECT 0 EREADY EREADY Bits 0,1: Select Flash Bank (Read/Write) Bit 1 Bit 0 Bank/Device Bit 2: Backup Battery Status (Read Only) 0 = Backup battery power is normal 1 = Backup battery is below level for data retention Bits 5 - 3: Reserved...

  • Page 72: Memory Page And Status Register (I/O Address 216H)

    Additional Local I/O Functions Memory Page and Status Register (I/O address 216h) |________|________|_________|________|_________|_________|_________|_________| FLASH MEMORY PAGE 5 PAGE 4 PAGE 3 PAGE 2 PAGE 1 PAGE 0 PROG/EN SELECT STATUS Bits 5 - 0: Application Flash and SRAM page select (read/write) NOTE The Flash devices used are 128 Mbits (16 Mbytes), using page bits 0 to 4.

  • Page 73: Status & Control Register 3 (I/O Address 217H)

    Additional Local I/O Functions Status & Control Register 3 (I/O address 217h) |________|________|_________|________|_________|_________|_________|_________| MODE VID4 VID3 VID2 VID1 VID0 JUMPER SYSTEM RESET ENABLE Bits 4 - 0: VME64x slot number (Read Only) These bits indicate the state of the VME Geographic Address pins (GA4-GA0) of the VME P1 connector.

  • Page 74: Long Duration Timer/Periodic Interrupt Timer

    NOTE 1 1MHz is selected by the BIOS as the default clock frequency (SIO set to 4MHz) as this is the clock frequency used on other Concurrent Technologies boards. NOTE 2 Although the LFCLK can be configured to 1Hz it also drives other circuitry. It is recommended that the LFCLK be left at 32.768kHz for future compatibility.

  • Page 75: Long Duration Timer/Periodic Interrupt Timer Low Byte

    Additional Local I/O Functions 8.8.1 Long Duration Timer/Periodic Interrupt Timer Low Byte |________|________|_________|________|_________|_________|_________|_________| LDT7 LDT6 LDT5 LDT4 LDT3 LDT2 LDT1 LDT0 Bits 7 - 0: Low Byte of LDT/PIT (Read/Write) Reading this register causes the current value of the LDT to be transferred to a holding register. This allows a stable 4-byte count to be read.

  • Page 76: Ldt/Pit Status & Control Register

    Additional Local I/O Functions 8.8.5 LDT/PIT Status & Control Register |________|________|_________|________|_________|_________|_________|_________| CLOCK INTERRUPT MODE MODE MODE SELECT FLAG Bit 0: LDT/PIT Run (Read/Write) This bit controls whether the LDT/PIT runs or is stopped. 0 = stop (default) 1 = run Bits 3 - 1: LDT/PIT Mode (Read/Write) These bits set the mode of the timer as follows: 000 = LDT...

  • Page 77: Programming The Ldt/Pit

    Additional Local I/O Functions 8.8.6 Programming the LDT/PIT The following code fragments illustrate how the system software, by using the on-board hardware, can create accurate time delays and measure elapsed times, accurate to 1µs, irrespective of the CPU’s operating frequency. The LDT and PIT control registers and operational modes are defined thus: #define TIMER_BYTE_0 (0x0218U)
  • Page 78 Additional Local I/O Functions It is possible to implement delays of 5ms, 2ms, 1ms, 500µs, 200µs and 100µs by utilizing other PIT modes. The PIT can generate an interrupt whenever the PIT rolls over. The system programmer must initialize the interrupt vector, enable PIC interrupts, etc. The following code fragment shows the basic interrupt handling function.
  • Page 79 Additional Local I/O Functions outbyte (CONTROL_STATUS, MODE_STOP); dElapsedTime (UINT32) inbyte (TIMER_BYTE_0); dElapsedTime |= ((UINT32) inbyte (TIMER_BYTE_1)) << 8; dElapsedTime |= ((UINT32) inbyte (TIMER_BYTE_2)) << 16; dElapsedTime |= ((UINT32) inbyte (TIMER_BYTE_3)) << 24; printf ("Elapsed time = %u.%06u seconds\n", dElapsedTime / 1000000U, dElapsedTime % 1000000U); The TIMER_BYTE_0, TIMER_BYTE_1, TIMER_BYTE_2 and TIMER_BYTE_3 control registers are at successive addresses and form a 32-bit register in “little endian”...
  • Page 80 Additional Local I/O Functions Port 80 A header has been provided for monitoring data written to I/O Port 80. The PC BIOS writes status bytes to Port 80 that indicate a boot progress status and/or highlight any faults found. Data written to this port can be monitored using a Logic State Analyzer (LSA) or seven segment hexadecimal displays.

  • Page 81: Figure 9-1 Mode Switch

    PC BIOS The VP 110/01x board is fitted with PC BIOS firmware that performs many of the functions of a standard desktop PC. It also includes additional features specifically tailored for the VME bus environment. In addition to the core BIOS firmware, the board is fitted with BIOS Extensions for remote bootload capability via either of the on-board Ethernet channels.
  • Page 82 PC BIOS this switch. A VT100-compatible serial terminal or emulator program should be used. By default the serial line is programmed to operate at 9600 Baud with 8 data bits, 1 stop bit and no parity (8N1). There is no flow control. For fast terminals, the baud rate can be increased via the Serial Console Baud Rate field of the Main Setup menu.

  • Page 83: The Pc Bios Startup Sequence

    PC BIOS The PC BIOS Startup Sequence When the board starts up without operator intervention, it will run a basic Power-On Self-Test (POST) sequence, including ECC DRAM initialization and a DRAM test. The full DRAM test will be omitted on subsequent restarts if the BIOS configuration settings have not been changed.

  • Page 84: Boot Device Selection

    PC BIOS Boot device selection The order in which the PC BIOS searches for a bootable medium is pre-configured but may be altered by the operator using the Boot setup menu. When the order is changed using this menu it will be retained in non-volatile memory so that the order is maintained after a restart. It is also possible to specify a one-time override of the boot device when the board starts, by pressing the <ESC>...

  • Page 85: Pci Bus Resource Management

    PC BIOS PCI Bus Resource Management The local bus structure of the VP 110/01x is quite complex, and is based around two independent PCI busses. In some cases the user may need to understand this structure and in particular how the PC BIOS firmware allocates addresses and interrupt signals to the available hardware resources.

  • Page 86: Table 9-1 Configurable Pci Bus Interrupts

    PC BIOS Table 9-1 lists the configurable interrupts for this board. The actual allocation of PCI bus interrupts to available interrupt controller inputs will depend on both the default “Plug-and-play” settings programmed by the PC BIOS, and the way in which the user has overridden them using the Setup screens.

  • Page 87: Table 9-2 Pci Device Numbers

    PC BIOS 9.4.2 PCI Device IDs Each PCI bus, and each device on an individual PCI bus, has a unique ID. For the VP 110/01x, the bus and device IDs are listed in Table 9-2. The ServerWorks chipset includes two PCI bus bridges to interface to the 64-bit and 32-bit on-board PCI busses, and these bridges are identified by the same PCI device ID but with different function codes.
  • Page 88 PC BIOS This page has been left intentionally blank VP 110/01x...
  • Page 89 I/O may be examined or modified. PCI devices can also be identified and their configuration registers displayed and changed. VSA allows all Concurrent Technologies’ boards in a system to be tested from a single console connected to the System Controller. This console can be a standard VGA screen connected via a PMC module and a keyboard, or a serial terminal connected to COM1.

  • Page 90: Starting The Master Test Handler

    The tests available in VSA mode are described as Built-In Self-Tests (BISTs). 10.2.4 Remote Testing from the System Controller In a system comprising more than one Concurrent Technologies’ CPU board, only the system controller board will provide a console interface; however, this board can be used to test the other VSA configured boards through their Slave Test Handlers.

  • Page 91: Bist Execution

    VME System Architecture Test Handler 10.2.6 BIST Execution BIST execution is started using the TEST command. While a test is executing, no further commands may be entered. It is possible to specify more than one BIST for execution using the “;” separator, for example: T14;T15;T20,4 Execute Test 14, Test 15 and Test 20.

  • Page 92: Mth Command Reference

    [No short command] Displays a list of boards in the system, their status and the active default slot number. Boards are identified by logical slot number. Only Concurrent Technologies boards, configured for VSA mode will be identified by this command.
  • Page 93 VME System Architecture Test Handler [No short command] Prints the pass and fail counts for all BISTs available on the default slot. SUM # [No short command] - test number, in the range 0-255 Prints the pass and fail count, for the BIST indicated, on the default slot. TEST # [Short command T] - test number, in the range 0-255...

  • Page 94: Utility Commands

    VME System Architecture Test Handler 10.3.3 Utility Commands IRO, IRR, ICR, ICW These commands are reserved for factory testing. They report and modify the state of the VSA board communication data structures. INB port_address read a byte from the specified I/O address INW port_address read a word from the specified I/O address IND port_address...
  • Page 95 Some of the text descriptions below refer to “interconnect” registers. These are locations in shared memory on the Concurrent Technologies boards operating in VSA mode, and are used extensively for inter-board communication and control.

  • Page 96: Bist Descriptions

    VSA Mode Diagnostics 11.2 BIST Descriptions The following is a list of the tests that are available in the firmware set installed on this board, together with an overview of the function of each test. A description of each possible error condition, with its code, is given for each test. 11.2.1 Test 1: Test Initialization Routine This pseudo-test performs no actual testing of the board.

  • Page 97: Test 6: Interconnect Image Check

    VSA Mode Diagnostics 11.2.4 Test 6: Interconnect Image Check This BIST reads and verifies the vendor ID and the board name from the Header Record of the local Interconnect Template. The interconnect template is a data structure used by VSA to communicate between boards.

  • Page 98: Test 12: Local Ram Fixed Pattern Test

    VSA Mode Diagnostics 11.2.8 Test 12: Local RAM Fixed Pattern Test This BIST performs a short test on local RAM. The range of memory to be tested depends upon the test handler from which the BIST was invoked. When the test is executed from the power-up test handler, it is necessary to limit execution time; therefore the test range is limited to the block of RAM before the video memory hole, i.e.
  • Page 99 VSA Mode Diagnostics 11.2.11 Test 20: Universe NMI Test This BIST checks the ability of the universe to generate a NMI to the processor using the software generated interrupt via LINT1. Error codes: 0406h - no interrupt generated or spurious interrupt 11.2.12 Test 22: RAM Data and Address Bus Test This BIST checks RAMs data and address bus.

  • Page 100: Test 25: Local Ram Dual Address Test

    VSA Mode Diagnostics 11.2.14 Test 25: Local RAM Dual Address Test This BIST checks for Dual Addressing in the RAM. The range of memory to be tested depends upon the test handler from which the BIST was invoked. When the test is executed from the slave test handler, e.g. during soak testing, the test range is limited to 64 Mbytes;...
  • Page 101 VSA Mode Diagnostics 11.2.16 Test 28: SCC Interrupt Test This BIST checks that the serial channel on the board is capable of generating an interrupt. A null character is transmitted on the channel to generate a transmit interrupt from that channel. If the interrupt occurs, checks are made to ensure that there is a transmit interrupt pending on the serial device.
  • Page 102 The Universe slave image and Byte swapping is disabled at the end of the test. When testing is performed using a Concurrent Technologies soak master, this test will operate as a co-operating BIST where two boards perform the Byte Swapping test on each others memory simultaneously.
  • Page 103 VSA Mode Diagnostics 11.2.23 Test 37: Bus Error Detection Test This BIST checks the operation of the VME Bus Error Detection facilities available on the VP 100/01x board. This BIST is composed of a series of sub-tests. The sub-test number is selected by a BIST parameter;...

  • Page 104: Test 39: Watchdog Test

    VSA Mode Diagnostics 11.2.24 Test 39: Watchdog Test This BIST checks the watchdog facilities available on the VP 110/01x board. The BIST is composed of a series of sub-tests. The sub-test number is selected by a BIST parameter; when run without parameters, a default series of sub-tests is performed. The available sub-tests are listed below, a (D) against the test indicates that it is executed by default when no parameters are supplied.
  • Page 105 VSA Mode Diagnostics 11.2.25 Test 40: LDT and PIT Test This BIST checks the operation of the LDT (Long Duration Timer) and the PIT (Periodic Interrupt Timer) facilities available on the VP 110/01x board. This BIST is composed of a series of sub-tests.
  • Page 106 VSA Mode Diagnostics 11.2.28 Test 41: StrataFlash Test This BIST checks the programmability of each StrataFlash device on the board. Each sub-test first identifies the device and reports the part number, then an erase/program/verify test is performed for all sectors in the StrataFlash. The original contents of the device are preserved and restored on successful completion.
  • Page 107 VSA Mode Diagnostics 11.2.29 Test 42: Non-Volatile RAM Test This BIST checks the operation of the non-volatile SRAM on the VP 110/01x board. The BIST is composed of a series of sub-tests. The sub-test number is selected by a BIST parameter; when run without parameters, a default series of sub-tests is performed.
  • Page 108 VSA Mode Diagnostics 11.2.30 Test 56: IDE Controller Test This BIST checks the operation of the embedded IDE controller that forms part of the CSB5 south bridge. This test consists of a number of sub-tests, which can be selected via a command line parameter.
  • Page 109 VSA Mode Diagnostics 11.2.31 Test 58: IDE Fixture Test This BIST checks the operation of the on-board IDE controller by means of an external test fixture. This fixture is identified as “TF0169”. There are no sub-commands or parameters relevant to this test. This fixture tests the following features of the IDE interface: Register Address Lines Chip Select Lines...
  • Page 110 VSA Mode Diagnostics 11.2.32 Test 63: PS/2 Mouse Test This BIST tests the PS/2 port and PS/2 mouse (if connected). The PS/2 port test includes opening the auxiliary port on keyboard controller, sending an echo to the auxiliary port and testing the auxiliary bus.
  • Page 111 VSA Mode Diagnostics 11.2.33 Test 64: PC Keyboard Test This BIST performs checks on the keyboard controller, the test also determines whether a keyboard is present. First, the keyboard controller’s output buffer is flushed and a ‘keyboard present’ test is performed.
  • Page 112 VSA Mode Diagnostics 11.2.34 Test 68: Real Time Clock Test This BIST tests the PC compatible, real time clock. The BIST provides a number of sub-tests, which are selected by a command parameter. If no parameter is supplied the current time and date is displayed, the interrupt signal is tested and the non-destructive NVRAM test performed.
  • Page 113 VSA Mode Diagnostics 11.2.35 Test 69: 82559ER Test This BIST tests the operation of both 82559ER Ethernet controllers on the baseboard. The BIST is split into a series of sub-tests. By default, only the device checks and internal loopback tests are performed, however the other sub-tests can be selected from the MTH command line using BIST parameters.
  • Page 114 VSA Mode Diagnostics 11.2.36 Test 70: Maxim 1617 Thermal Sensor Test This BIST checks the operation of the Maxim 1617 Thermal Sensor. This test consists of a number of sub-tests, which can be selected via a command line parameter. If the BIST is invoked without parameters, only basic diagnostics and CPU over-heat are checked.
  • Page 115 VSA Mode Diagnostics 11.2.36.4 Change Update Frequency This option allows the user to change the update frequency of the Maxim 1617 Thermal Sensor. All possible options are listed below: Value Update Frequency (Hz) 0.0625 0.125 0.25 Alarms will only trigger when an update occurs. Should there be a temperature spike between readings it will not trigger an alarm.
  • Page 116 VSA Mode Diagnostics 11.2.36.5 Full Readout This option reads and displays the data currently available from the Maxim 1617 Thermal Sensor. The display is in the following format. !ALERT mask S/w standby Conv. rate : 0.0625Hz Chip busy CPU OPEN CPU SHORT CPU VCC Temp.
  • Page 117 0300h - see error message for details. 11.2.38 Test 80: SCSI Based PMC Site Test This BIST uses a Concurrent Technologies SC PMC/825 or SC PMC/875 PMC SCSI module to verify the operation of any PMC sites connected to the board. Both baseboard and carrier-based PMC sites are tested.
  • Page 118 VSA Mode Diagnostics 11.2.40 Test 101: Display Memory Utility This BIST allows any area of the target board’s local memory to be examined and displayed by the test master. This utility requires command-line parameters to function correctly, so it should only be run in an interactive manner by a local or remote test master.
  • Page 119 VSA Mode Diagnostics 11.2.43 Test 104: I/O Write Utility This BIST allows modification of any I/O register on the target board. This utility requires command-line parameters to function correctly, so it should only be run in an interactive manner by a local or remote test master. The parameters are: 16-bit I/O address (default 0), value to write to register (default 0),...
  • Page 120 VSA Mode Diagnostics 11.2.46 Test 107: Cache Control Utility This BIST allows the status of DRAM and EPROM caching on the target board to be interrogated or configured. If the utility is invoked without parameters, the default action is to display the state of DRAM and EPROM caching.
  • Page 121 VSA Mode Diagnostics 11.2.48 Test 121: PCI Read Utility This BIST allows PCI configuration registers to be examined on the target board. This utility requires command-line parameters to function correctly, so it should only be run in an interactive manner by a local or remote test master. The parameters are: Device number = 0 to 31 - default = 0...
  • Page 122 VSA Mode Diagnostics This page has been left intentionally blank 11-28 VP 110/01x...

  • Page 123: Specifications

    Specifications Functional Specification Processor: • 800MHz or 1.2GHz Pentium III-M with 32 Kbyte Level 1 cache. Level 2 Cache: • 512 Kbytes on-die RAM operating at core frequency. Memory: • 512 Kbytes Flash EPROM for PC BIOS using socketed 28SF040 device. •...
  • Page 124 Specifications Environmental Specification A.2.1 Temperature Range Operating . 0 to +55ºC @ 400LFM air flow Storage . -40 to +70ºC NOTE If the on-board hard disk drive option is fitted, the operating temperature range will be restricted to +5 to +55ºC and the storage temperature range will be restricted to -40 to +65ºC.

  • Page 125: Figure A-1 Connector Layout

    Specifications Connectors Figure A-1 Connector Layout COM1 PMC Site 2 PMC Site 1 Ethernet CH0 Ethernet CH1 Ground External Reset Figure A-2 Front Panel Connectors VP 110/01x...

  • Page 126: Table A-1 Vme Interface Pin-Outs

    Specifications A.5.1 VME Interface (P1) Pin-outs The VME interface connector P1 consists of a 160-pin connector with pins assigned as follows: Pin No. Row Z Row A Row B Row C Row D BBSY BCLR ACFAIL BG0IN BG0OUT BG1IN BG1OUT BG2IN BG2OUT SYSCLK...

  • Page 127: Table A-2 P2 Connector Pin-Outs (64 Pmc I/O Signals)

    Specifications A.5.2 Auxiliary Connector (P2) Pin-outs The auxiliary connection P2 consists of a 160-pin connector. The pin assignments are as shown in Table A-2. Pin No. Row Z Row A Row B Row C Row D DRVDEN0 PMC Slot 1 I/O 2 PMC Slot 1 I/O 1 IDERST PMC Slot 1 I/O 4...

  • Page 128: Table A-3 Pmc I/O Connector (P0) Pin-Outs

    Specifications A.5.3 PMC I/O Connector (P0) Pin-outs Some VP 110/01x variants are fitted with a P0 connector. This is a 95-way (5-row x 19-position) IEC 61076-4-101 2mm pitch connector. It carries all 64 I/O signals from PMC Site 2. The pin assignments conform to the P4V0-64 mapping defined in the ANSI/VITA 35-2000 standard and are shown below.

  • Page 129: Figure A-3 Keyboard And Mouse Header Lk1 Polarization

    Specifications A.5.4 Keyboard and Mouse Header (LK1) Pin-outs The keyboard and mouse interface signals are routed to a 2 row x 4-way 0.1 inch pitch header, which is located behind the serial port connector. The pin assignments are shown in Table A-4. Connector location and pin orientation is detailed in Figure A-3.

  • Page 130: Figure A-4 Serial Port Rj45 Connector (Front View)

    Specifications A.5.5 Serial Interface (J9) Pin-outs The COM1 RS232 serial interfaces use 8-way RJ45 connectors with the following pinouts. 1 2 3 4 5 6 7 8 Figure A-4 Serial Port RJ45 Connector (Front View) Pin No. Signal Name Direction RTS - Request To Send Output from board DTR - Data Terminal Ready...

  • Page 131: Figure A-5 Ethernet Rj-45 Connector (Front View)

    Specifications A.5.6 Ethernet Interface (J15 and J16) Pin-outs The Ethernet Interfaces use 8-way RJ45 connectors with the following pin-out: 1 2 3 4 5 6 7 8 Figure A-5 Ethernet RJ-45 Connector (Front View) Pin No. Signal Name Transmit (+) Transmit (-) Receive (+) Not used...

  • Page 132: Table A-8 On-Board Mass Storage Option Interface Pin-Outs

    Specifications A.5.7 On-Board Mass Storage Option Connector (S1) Pin-outs Pin No. Signal Name Pin No. Signal Name IDE_RST SDD7 SDD8 SDD6 SDD9 SDD5 SDD10 SDD4 SDD11 SDD3 SDD12 SDD2 SDD13 SDD1 SDD14 SDD0 SDD15 +3.3 SDREQ SDIOW SDIOR SIORDY SDDACK INT15 SDA1 PDIAG...

  • Page 133: Table A-9 Pmc J11 Connector Pin-Outs

    Specifications A.5.8 PMC Site 1 Connectors (J11, J12, J13 and J14) Pin-outs Signal assignments on the PMC connectors for PMC Site 1 are shown in Tables A-9, A-10, A-11 and A12. Pin No. Signal Name Pin No. Signal Name -12V INTB# INTC# INTD#...

  • Page 134: Table A-10 Pmc J12 Connector Pin-Outs

    Specifications Pin No. Signal Name Pin No. Signal Name +12V +3.3V†† +3.3V RST# +3.3V AD(30) AD(29) AD(26) AD(24) +3.3V IDSEL AD(23) +3.3V AD(20) AD(18) AD(16) C/BE(2)# IDSEL B TRDY# +3.3V STOP# PERR# +3.3V SERR# C/BE(1)# AD(14) AD(13) M66EN AD(10) AD(08) +3.3V AD(07) REQ B#...

  • Page 135: Table A-11 Pmc J13 Connector Pin-Outs

    Specifications Pin No. Signal Name Pin No. Signal Name C/BE(7)# C/BE(6)# C/BE(5)# C/BE(4)# V(I/O) PAR64 AD(63) AD(62) AD(61) AD(60) AD(59) AD(58) AD(57) V(I/O) AD(56) AD(55) AD(54) AD(53) AD(52) AD(51) AD(50) AD(49) AD(48) AD(47) AD(46) AD(45) V(I/O) AD(44) AD(43) AD(42) AD(41) AD(40) AD(39) AD(38)

  • Page 136: Table A-12 Pmc J14 Connector Pin-Outs

    Specifications Pin No. Signal Name Pin No. Signal Name I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19...

  • Page 137: Table A-13 Pmc J21 Connector Pin-Outs

    Specifications A.5.9 PMC Site 2 Connectors (J21, J22, J23 and J24) Pin-outs Signal assignments on the PMC connectors for PMC Site 2 are shown in Tables A-13, A-14, A-15 and A-16. Pin No. Signal Name Pin No. Signal Name -12V INTC# INTD# INTA#...

  • Page 138: Table A-14 Pmc J22 Connector Pin-Outs

    Specifications Pin No. Signal Name Pin No. Signal Name +12V +3.3V†† +3.3V RST# +3.3V AD(30) AD(29) AD(26) AD(24) +3.3V IDSELC AD(23) +3.3V AD(20) AD(18) AD(16) C/BE(2)# IDSEL D TRDY# +3.3V STOP# PERR# +3.3V SERR# C/BE(1)# AD(14) AD(13) M66EN AD(10) AD(08) +3.3V AD(07) REQ D#...

  • Page 139: Table A-15 Pmc J23 Connector Pin-Outs

    Specifications Pin No. Signal Name Pin No. Signal Name C/BE(7)# C/BE(6)# C/BE(5)# C/BE(4)# V(I/O) PAR64 AD(63) AD(62) AD(61) AD(60) AD(59) AD(58) AD(57) V(I/O) AD(56) AD(55) AD(54) AD(53) AD(52) AD(51) AD(50) AD(49) AD(48) AD(47) AD(46) AD(45) V(I/O) AD(44) AD(43) AD(42) AD(41) AD(40) AD(39) AD(38)

  • Page 140: Table A-16 Pmc J24 Connector Pin-Outs

    Specifications Pin No. Signal Name Pin No. Signal Name I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19...

  • Page 141: Table A-17 30-Way Debug Connector Pin-Outs

    Specifications A.5.10 Processor Debug Port (J1) Pin-outs The processor debug port, which is supported by a number of emulator devices, is accessible via an Intel specified 30-way receptacle connector with the following pin-out. Pin No. Signal Name CPU Reset Debug Reset CPU TCK CPU TDI CPU TMS...

  • Page 142: Figure A-6 Port 80 Connector

    Specifications A.5.11 Port 80 (J3) Pin-outs Figure A-6 Port 80 Connector Pin No. Signal Name Not Connected Port 80 Select Not Connected +5 Volts Table A-18 Port 80 Connector Pin-outs A-20 VP 110/01x...

  • Page 143: Table B-1 Breakout Modules List

    Breakout Modules Introduction This section details all the available breakout modules available for use with the VP 110/01x. Each breakout module provides a means of connecting interface cables to the rear I/O of the VP 110/01x. An overview of each breakout module is given with a reference to a pin-out table for each of the connectors identified.

  • Page 144: Figure B-1 Ad Vp2/004-10 P2 Breakout Connectors

    Breakout Modules AD VP2/004-10 The AD VP2/004-10 product is a 3-row P2 breakout board designed for use with the VP 110/01x-1x VME board. It provides two IDC connectors for the PMC I/O signals on P2, and also makes all these signals available via a single 68-way high-density D-type socket. This breakout requires one slot width behind the backplane.

  • Page 145: Figure B-2 Ad Vp2/004-20 P2 Breakout Connectors

    Breakout Modules AD VP2/004-20 The AD VP2/004-20 product is a 5-row P2 breakout board designed for use with the VP 110/01x-3x VME board. It provides two IDC connectors for the PMC I/O signals on P2, and also makes all these signals available via a single 68-way high density D-type socket. It also provides IDC connectors for the EIDE and floppy disk interfaces, and provides a USB connector.

  • Page 146: Figure B-3 Ad Vp2/005-00 P2 Breakout Connectors

    Breakout Modules AD VP2/005-00 The AD VP2/005-00 product is a P0 and 5-row P2 breakout board designed for use with the VP 110/01x-2x VME board. It provides IDC connectors for the PMC I/O signals on P0 and P2 and standard PC connectors for the EIDE, floppy disk and USB interfaces on P2. B.5.1 Layout Figure B-3 shows the position of connectors and headers.

  • Page 147: Table B-2 Floppy 34-Way Idc Header

    Breakout Modules Header/Connector Configuration Tables The headers and connectors are designed to enable use of standard P.C. Interface cables wherever possible. Detailed below are the pin-outs of the headers and connectors used on the breakout modules. Pin No. Signal Name Pin No.

  • Page 148: Table B-4 Usb Connector Pin-Outs

    Breakout Modules Pin No. Signal Name DATA (-) DATA(+) Table B-4 USB Connector Pin-outs Pin No. Signal Name Pin No. Signal Name I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12...

  • Page 149: Table B-7 P5 68-Way D-Type Connector Pin-Outs

    Breakout Modules Pin No. Signal Name Pin No. Signal Name I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18...
  • Page 150 Breakout Modules This page has been left intentionally blank VP 110/01x...

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