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Celoxica RC200 Manual

Platform developer’s kit
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Platform Developer's Kit
RC200/203 Manual

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Summary of Contents for Celoxica RC200

  • Page 1 Platform Developer’s Kit RC200/203 Manual...
  • Page 2 This document is intended only to assist the reader in the use of the product. Celoxica Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any incorrect use of the product.

  • Page 3: Table Of Contents

    RC200/203 Manual Contents 1 RC200/203 ....................8 BOARD 2 RC200/203 ....................9 OVERVIEW 2.1 S ...................... 9 TANDARD KIT 2.2 P ..................... 10 ROFESSIONAL KIT 2.3 E ......................10 XPERT KIT 2.4 RC200/203 ................ 11 SUPPORT SOFTWARE ..................12 NSTALLATION AND SET ..................
  • Page 4 4.24 D ..............34 ATA SHEETS AND SPECIFICATIONS 5 RC200/203 PSL ..................36 REFERENCE 5.1 U RC200 PSL ..................36 SING THE 5.2 C .................... 36 LOCK DEFINITIONS 5.2.1 Specifying a clock source...................... 37 5.2.2 Specifying a clock rate ......................37 5.2.3 Checking the clock rate ......................
  • Page 5 RC200/203 Manual 5.12.1 Video input management tasks ................... 51 5.12.2 Selecting the video input ..................... 51 5.12.3 Selecting the colour-encoding standard................51 5.12.4 Reading a pair of YCrCb pixels ................... 52 5.12.5 Reading a pair of RGB pixels ....................52 5.12.6 Reading a single RGB pixel ....................
  • Page 6 RC200/203 Manual Conventions The following conventions are used in this document. Warning Message. These messages warn you that actions may damage your hardware. Handy Note. These messages draw your attention to crucial pieces of information. Hexadecimal numbers will appear throughout this document. The convention used is th...
  • Page 7 RC200/203 Manual Assumptions & Omissions This manual assumes that you: • have used Handel-C or have the Handel-C Language Reference Manual • are familiar with common programming terms (e.g. functions) • are familiar with your operating system (Linux or MS Windows) This manual does not include: •...

  • Page 8: Rc200/203 Board

    Supporting software includes PAL, DSM, the RC200 PSL, and the FTU2 File Transfer Utility. The only difference between the RC200 and RC203 platforms is the FPGA fitted, a 2V1000-4 on the RC200 and a larger 2V3000-4 on the RC203.

  • Page 9: Rc200/203 Overview

    (see page 14). Note: the Xilinx Virtex II device on the RC203 has part number XC2V3000-FG676. 2.1 Standard kit • Virtex-II 2V1000-4 (RC200) or 2V3000-4 (RC203) FPGA • Ethernet MAC/PHY with 10/100baseT socket • 2 banks of ZBT SRAM providing a total of 4-MB •...

  • Page 10: Professional Kit

    Perspex top and bottom covers • Universal 110/240V power supply (IEC Mains lead not included) • Celoxica Platform Developer’s Kit including: • Platform Support Library for RC200/203 • Platform Abstraction Layer for RC200/203 • Data Stream Manager for MicroBlaze soft-core microprocessor •...

  • Page 11: Rc200/203 Support Software

    RC200/203 board 2.4 RC200/203 support software The following software support for the RC200/203 is provided as part of the Platform Developer's Kit: • RC200 Platform Support Library (PSL) • RC200 Platform Abstraction Layer (PAL) implementation • Data Stream Manager (DSM) implementation for MicroBlaze soft-core microprocessor •...

  • Page 12: Installation And Set-Up

    Peripheral devices should be connected before the RC200/203 Board is turned on. Otherwise the devices may not function correctly. LED D2 will light up when the power is on. This is the lower of the 2 LEDS to the left of the Celoxica copyright printed on the board.

  • Page 13: Hardware Description

    Installation and set-up 4 Hardware description This section describes the devices on the RC200, how to program the FPGA and how to transfer data between the host, SmartMedia and FPGA. Schematics for the board are available in InstallDir\PDK\Documentation\PSL\RC200\RC200VBDOC.pdf for the RC200 or in InstallDir\PDK\Documentation\PSL\RC203\RC203VBDOC.pdf for the RC203 (for installations...

  • Page 14: Rc200/203 Connectors

    4.3.1 Control and data pins The RC200 CPLD has 10 control lines and 8 data lines. 3 of the control lines are used as an address bus. The control lines have two meanings, depending on the FPGA operation mode (see page 19).

  • Page 15: Cpld Clock

    YAB20 4.3.2 CPLD clock The RC200 CPLD has a clock input of 50MHz from a 50MHz crystal oscillator module. This is divided by 2 to give an internal clock speed of 25MHz. 4.3.3 Register map in the CPLD for the FPGA...

  • Page 16: Cpld / Parallel Port Interface

    Read from this address to start reprogramming of the FPGA from SmartMedia 4.3.4 CPLD / parallel port interface The RC200 CPLD supports an EPP (Enhanced Parallel Port) interface. The parallel port is connected to the CPLD on the following pins: Page 16...
  • Page 17 Bit 3: SmartMedia nBUSY signal Bit 4: SmartMedia Detect (1 = SmartMedia inserted) Bit 5: SmartMedia not Write Protect Bit 6: SmartMedia state machine disable status Bit 7: PLL data line (I C bus) Write status of signals: Page 17 www.celoxica.com...

  • Page 18: Fpga

    Not used Not used Not used CPLD version ID (0x51) 4.4 FPGA The RC200 board has a Xilinx Virtex-II FPGA (part: XC2V1000-4FG456C on RC200 and XC2V3000-4FG676 on RC203). The device has direct connections to the following devices: • CPLD •...

  • Page 19: Fpga Operation Modes

    The function of the other CPLD control lines changes, depending on whether P9 is high or low. 4.4.2 Programming the FPGA using the FTU2 program Celoxica provides a File Transfer Utility program, FTU2, which simplifies the process of programming the RC200 FPGA via the parallel port.

  • Page 20: Programming The Fpga From Smartmedia

    4.4.4 Programming the FPGA from SmartMedia You can program the RC200 Virtex-II from BIT files loaded onto the SmartMedia device. The BIT files can be in exactly the same format as if you were programming from the parallel port. There is no need to change or remove the header.

  • Page 21: Writing Data To The Cpld From The Fpga

    4.4.9 Using the FPGA in parallel port control mode When the CPLD control line P9 is set low the RC200 FPGA has direct control over the parallel port. The nRDWR signal (CPLD control line P2) defines the direction of the databus.

  • Page 22: Smartmedia Flash Memory

    Installation and set-up 4.6 SmartMedia Flash memory The RC200/203 has a socket for a SmartMedia Flash memory device (connector CN7 at the top left of the board). The Professional and Expert versions of the RC200/203 are provided with a 16-MB SmartMedia card.

  • Page 23: Parallel Port Access Of Smartmedia

    You need to carry out steps 1 to 4 for any access to the SmartMedia. 4.7 ZBT SRAM banks The RC200/203 is fitted with 2 ZBT RAM banks, capable of operating at up to 100MHz. The RC200/203 Standard and Professional boards have two 2-MB banks fitted and the RC200/203 Expert has two 4-MB banks.

  • Page 24: Clock Generator (Pll)

    S1C4 - S1C7 Not Byte Enable pins D6, C6, C4, C5 F8, E8, E6, E7 4.8 Clock generator (PLL) The RC200/203 board has a Cypress CY22393 Programmable Clock Generator. The generator is programmed to provide the following clocks: Page 24 www.celoxica.com...

  • Page 25: Programming The Pll Via The Parallel Port Or Fpga

    4.8.1 Programming the PLL via the parallel port or FPGA The RC200 PLL chip can be soft programmed by either the FPGA or the parallel port. It reverts to factory settings on a power on reset. The PLL chip supports a form of I If you are programming from the parallel port, the FPGA should be disabled by asserting nPROG if there is any chance of it interfering with the programming of the PLL.

  • Page 26: Ethernet

    The RC200/203 is fitted with a Standard Microsystems Corporation LAN91C111 Ethernet device. It supports 8-bit and 16-bit access to the FPGA. The device has a clock input of 25MHz, generated from the CPLD. For more information about the device refer to the RC200 data sheets (see page 34). Ethernet pins...

  • Page 27: Video Output Processors

    Installation and set-up 4.11 Video output processors The RC200/203 can convert digital RGB input into outputs for a VGA screen, a TV (PAL or NTSC) or an LCD screen. VERVIEW OF VIDEO OUTPUT PROCESSING 4.11.1 Digital / Analogue converter The Analog Devices ADV7123 High speed video DAC can convert 30-bit digital input to VGA output or RGB input for the NTSC/PAL encoder.

  • Page 28: Rgb To Ntsc/Pal Encoder

    Installation and set-up 4.11.2 RGB to NTSC/PAL encoder The RC200/203 has an Analog Devices AD725 RGB to NTSC/PAL Encoder. This receives RGB input from the video DAC. For more information on this device, please refer the RC200 data sheets (see page 34).

  • Page 29: Mouse And Keyboard Ps/2 Ports

    4.14 Mouse and keyboard PS/2 ports The RC200/203 board has two PS/2 ports, labelled Mouse and Keyboard on the PCB. These are 6-pin mini DIN sockets that will accept any standard PS/2 mouse or keyboard. The DATA and CLK lines of these sockets are mapped directly through to the FPGA.

  • Page 30: Ata / Expansion Header

    4.16 ATA / Expansion header The RC200/203 has a 50-pin expansion header including 34 general I/O pins, 3 power pins (+12V, +5V, +3.3V) and 2 clock pins. You can also use 40 of the pins for ATA, but only UDMA4 or higher devices are supported.
  • Page 31 Installation and set-up Expansion ATA function Expansion header RC200 RC203 header pins function FPGA pins FPGA pins Reset IO10 IO12 IO11 IO14 IO13 IO16 IO15 Keypin Pin removed DMARQ IO17 nDIOW IO18 nDIOR IO19 IORDY IO20 CSEL IO21 nDMACK IO22...

  • Page 32: Leds

    +12v +12v (0.5Amps max) CLK1 CLK1 AA13 4.17 LEDs The RC200 board has two blue LEDs that can be directly controlled from the FPGA. These are connected as follows: LED pins RC200 FPGA Pins RC203 FPGA Pins Blue0 Blue1 The LED pins should be set high to turn the LEDs on.

  • Page 33: Reset Button

    Installation and set-up 4.19 Reset button The reset button on the RC200/203 is next to the power input. It clears the FPGA program, and reboots the FPGA from SmartMedia, if a SmartMedia card is present. 4.20 JTAG connector The JTAG connector on the RC200/203 is next to the reset button. JTAG connector pinout is as follows: JTAG Function VCC (+3.3V)

  • Page 34: Bluetooth Module

    Installation and set-up 4.22 Bluetooth module A Mitsumi WML-C09 Bluetooth module is provided on the RC200/203 Expert board. It is connected directly to the FPGA. Bluetooth pins Function RC200 FPGA pins RC203 FPGA pins RX pin AA15 TX pin AB15...
  • Page 35 Cirrus Logic Audio Codec http://www.cirrus.com/en/pubs/proDatasheet/cs4202-1.pdf Crystal CS4202-JQ MAXIM MAX3222 RS-232 http://pdfserv.maxim-ic.com/arpdf/MAX3222-MAX3241.pdf Serial Transceiver AT Attachment storage http://www.t13.org/ interface specification Mitsumi Bluetooth module http://www.mitsumi.co.jp/Catalog/ WML-C09 hifreq/commun/wml/c09/text01e.pdf Fujitsu Components http://www.fceu.fujitsu.com/pdf/Datasheet_4Wire_TouchPanels.pdf N010-0554-T042 touch screen Burr Brown Products TSC2200 http://www-s.ti.com/sc/ds/tsc2200.pdf Touch Screen controller Page 35 www.celoxica.com...

  • Page 36: Rc200/203 Psl Reference

    The RC200 Platform Support Library (PSL) simplifies the process of programming the FPGA to target the devices connected to it on the RC200 board. It also allows you to configure the FPGA from SmartMedia, and send data between the FPGA and host PC.

  • Page 37: Specifying A Clock Source

    To use CLKUSER (the FPGA clock) or one of the expansion header clocks, define one of the macros above before you include rc200.hch in your source code. The specified clock will be used by any subsequent void main (void) definition.

  • Page 38: Led Macros

    Expert boards. 5.4 LED macros The LED macros target the blue LEDs on the RC200. The green LEDs on the RC200 are controlled by the CPLD and cannot be programmed. To turn the blue LEDs on and off, you can either use RC200LEDWrite() and set Index to 0 to target LED0 or to 1 to target LED1, or you can use one of the RC200LED*Write() macros to target a specific LED.

  • Page 39: Push Button Macros

    The seven-segment display macros allow you to write a specific hexadecimal digit to each display, or to specify which segments are lit up. SevenSeg0* macros target the left-hand display on the board and SevenSeg1* macros target the right-hand display. 5.6.1 Setting segments extern macro proc RC200SevenSeg0WriteShape (Shape); extern macro proc RC200SevenSeg1WriteShape (Shape); Page 39 www.celoxica.com...

  • Page 40: Writing Digits

    You need to call this in parallel with the rest of your RAM code. 2. Set the address for the read or write using one of the RC200PL1RAMXSetReadAddress or RC200PL1RAMXSetWriteAddress() macros. 3. Call one of the RC200PL1RAM*Read() or RC200PL1RAM*Write() macros. Page 40 www.celoxica.com...

  • Page 41: Ram Management Tasks

    RC200PL1RAM1SetWriteAddress (Address); Parameters: Address: Address of data to read/write on the next clock cycle, of type unsigned 19 on the Standard and Professional versions of the RC200, and unsigned 20 on Expert boards. Timing: 1 clock cycle.

  • Page 42: Reading From Ram

    Does not terminate in normal use. Description: Runs the device management tasks for the mouse. You must run this macro in parallel with accesses to the device. 5.8.2 Reading data from the mouse extern macro proc RC200PS2MouseRead (DataPtr); Page 42 www.celoxica.com...

  • Page 43: Writing Data To The Mouse

    DataPtr. Note that these are raw bytes from the keyboard. To do interpreted access (e.g. ASCII keyboard characters) you should use the PAL PS/2 API. 5.8.6 Writing data to the keyboard extern macro proc RC200PS2KeyboardWrite (Data); Page 43 www.celoxica.com...

  • Page 44: Rs-232 Port Macros

    Selecting the baud extern macro proc RC200RS232SetBaudRate (BaudRate); Parameters: BaudRate: A code selecting the baud (see below). 1 clock cycle. Timing: Changes the baud of the RS232 interface. BaudRate must be one of the codes Description: listed below. Page 44 www.celoxica.com...

  • Page 45: Hardware Description

    FlowControl: A code selecting the flow control. Possible values: RC200RS232FlowControlNone RC200RS232FlowControlSoft RC200RS232FlowControlHard These correspond to the following settings: No flow control; Software flow control (XON/XOFF); Hardware flow (RTS/CTS) Timing: 1 clock cycle. Description: Changes the flow control of the RS-232 interface. Page 45 www.celoxica.com...

  • Page 46: Reading From The Rs-232 Port

    Does not terminate in normal use. Description: Runs the device management tasks for the touch screen. You must run this macro in parallel with accesses to the device. 5.10.2 Touch screen position (raw) extern macro proc RC200TouchScreenReadRaw (XPtr, YPtr, TouchPtr); Page 46 www.celoxica.com...

  • Page 47: Touch Screen Position (Scaled)

    5.11 Video output macros To use the video output macros, you need to: 1. Run RC200VideoOutRun() in parallel with the rest of your video output code. 2. Call RC200VideoOutEnable(). 5.11.1 Video output management tasks extern macro proc RC200VideoOutRun (Mode, ClockRate); Page 47 www.celoxica.com...

  • Page 48: Enabling Video Output

    1152 x 864 @ 72Hz 100.000000 MHz 1280 x 1024 @ 75Hz 140.000000 MHz 720 x 576i @ 50Hz 13.846154 MHz 720 x 480i @ 60Hz 13.846154 MHz 5.11.2 Enabling video output extern macro proc RC200VideoOutEnable (); Page 48 www.celoxica.com...

  • Page 49: Querying Screen Sizes

    As a result, the return value is also a compile time constant. 5.11.4 Disabling video output extern macr o proc RC200Vi deoOut Disable (); Paramete None. Timing: Typically 1 clock cycle. escription: Disables the video output. Page 49 www.celoxica.com...

  • Page 50: Writing A Pixel

    5.11.8 Horizontal and vertical sync status extern macr o expr RC20 0VideoOutGetHSync (); extern macr o expr RC200VideoOutGetVSync (); arameters: None. Macro expressions that return the horizontal or vertical sync status of the current Description: scan position, as type unsigned 1. Page 50 www.celoxica.com...

  • Page 51: Video Input Macros

    (CVBS) input; Camera input; S-Video input. The default value is RC200VideoInInputComposite. 1 or more clock cycles. Timing: Description: Selects one of the three video inputs to sample. 5.12.3 Selecting the colour-encoding standard extern macro proc RC200VideoInSetStandard (Standard); Page 51 www.celoxica.com...

  • Page 52: Reading A Pair Of Ycrcb Pixels

    720 pixels. The value returned in YPtr varies from 0 to the number of visible lines – 1: 0-575 for PAL and 0-479 for NTSC. 5.12.5 Reading a pair of RGB pixels extern macro proc RC200VideoInReadPixelPairRGB (XPtr, YPtr, LeftRGBPtr, RightRGBPtr); Page 52 www.celoxica.com...

  • Page 53: Reading A Single Rgb Pixel

    The chrominance and luminance values range from 0 to 255. The value in XPtr ranges from 0 to 719 for an entire video line of 720 pixels. The value returned in YPtr varies from 0 to the number of visible lines - 1: 0-575 for PAL and 0-479 for NTSC. Page 53 www.celoxica.com...

  • Page 54: Audio I/Omacros

    Boost: Data value of type unsigned 2. 1 or more clock cycles. Timing: Description: Sets the boost level of the microphone input amplifier, in +10dB steps, from 0 to +30dB. 5.13.4 Setting the gain level extern macro proc RC200AudioInSetGain (Mute, LeftVol, RightVol); Page 54 www.celoxica.com...

  • Page 55: Setting The Input Sample Rate

    Reads a single stereo sample from the audio interface and stores it in the lvalue pointed at by DataPtr. The macro blocks until a new sample can be read. 5.13.7 Setting the output volume extern macro proc RC200AudioOutSetVolume (Mute, LeftVol, RightVol); Page 55 www.celoxica.com...

  • Page 56: Setting The Output Sample Rate

    Left and Right. The macro blocks until a new sample can be written. 5.14 Bluetooth macros To read from or write to the Bluetooth interface you need to: 1. Call RC200BluetoothRun(). 2. Call RC200BluetoothRead() or RC200BluetoothWrite() in parallel with this. You can reset the device using RC200BluetoothReset(). Page 56 www.celoxica.com...

  • Page 57: Bluetooth Management Tasks

    (BCSP) from Cambridge Silicon Radio. 5.15 SmartMedia macros The RC200 supports SmartMedia devices between 4 and 128 megabytes. For devices of 16 megabytes or more, you can use physical or logical addressing. You are recommended to use logical addressing, Page 57...

  • Page 58: Using The Smartmedia Macros

    5.15.1 Using the SmartMedia macros Accessing the SmartMedia card To use the RC200 PSL macros to access SmartMedia, you need to: 1. Call the RC200SmartMediaRun() macro in parallel with the other SmartMedia macros and in parallel to RC200CPLDRun().

  • Page 59: Smartmedia Management Tasks

    SmartMedia device can be determined after a successful call to RC200SmartMediaInit() by calling RC200SmartMe diaGetMakerCode() and RC200SmartMediaGetDeviceCode(). Both return valu es of type unsigned 8. For example: unsigned 8 Maker, Device; Maker = RC200SmartMediaGetMakerC ode (); Device = RC200SmartMediaGetDeviceCode (); Page 59 www.celoxica.com...

  • Page 60: Resetting The Smartmedia

    It preserves the CIS (Card Information Structure) and IDI (ID information) fields. If you overwrite these fields, the SmartMedia card may not work with other hardware. • It skips bad blocks, avoiding the risk of reading or writing invalid data. Page 60 www.celoxica.com...
  • Page 61 RC200SmartMediaSetAddress(). For information on how the phy sical layer control works, or to target SmartMedia without using the PSL, refer to the RC200 Hardware and Installation Guide, the documentation for your SmartMedia card, or http://www.ssfdc.or.jp/english/. Checkin g for a lo...

  • Page 62: Reading From And Writing To The Smartmedia

    The macro adjusts automatically for whether the address is in the first half of the page (address < 256), or the second half of the page (255 < address < 512). Reading from the SmartMedia extern macro proc RC200SmartMediaRead (DataPtr, LastData); Page 62 www.celoxica.com...
  • Page 63 To perform a real-time check for errors whilst the write is in progress, use RC200SmartMediaGetError(). A write process erases the entire contents of the block, even if you only write one byte. Completing a read or write operation extern macro proc RC200SmartMediaOperationEnd (ResultPtr); Page 63 www.celoxica.com...

  • Page 64: Ethernet Macros

    Once you start reading or writing a packet, you must finish it before accessing the network driver in any other way. For example, it is not permissible to overlap reading and writing of packets. 5.16.1 Ethernet management tasks extern macro proc RC200EthernetRun (ClockRate, MACAddress); Page 64 www.celoxica.com...

  • Page 65: Enabling The Ethernet Device

    RC200EthernetDisable (); Parameters: None. Timing: 1400 clock cycles or more. Puts the Ethernet device in isolation mode, and clears the transmit and receive Description: parameters. 5.16.5 Resetting the Ethernet device extern macro proc RC200EthernetReset (); Page 65 www.celoxica.com...

  • Page 66: Reading A Packet

    Data is read a byte at a time, but communications with the Ethernet chip are 16-bit, so a byte is buffered in the Ethernet data structure, until there are 16 bits to read. You must call RC200EthernetReadBegin() before this macro. Page 66 www.celoxica.com...

  • Page 67: Writing A Packet To The Network

    Result will be returned as 0 if successful, and 1 otherwise. If it is not successful, no further packet write commands should be issued, and you should try again to initiate the write. Writing a byte of data to a packet extern macro proc RC200EthernetWrite (Data, ResultPtr); Page 67 www.celoxica.com...

  • Page 68: Reconfiguring The Fpga

    The address is passed in as a logical address, which is the physical address on the SmartMedia + 1. This allows for the CIS (Card Information Structure) block. If no SmartMedia card is present, the macro returns, otherwise it enters a loop until the FPGA is reconfigured. Page 68 www.celoxica.com...

  • Page 69: Cpld Control

    You need to call this macro in parallel with RC200CPLDRun(), and before accesses to the CPLD. The macro waits until the CPLD is ready and then sets the CPLD internal mode to normal operation. Refer to the RC200 Hardware and Installation Manual for more details.

  • Page 70: Enabling The Send Protocol Driver

    1 clock cycle. Enables the Send Protocol driver. You cannot use this at the same time as the Description: RC200 SmartMedia macros. You need to call RC200CPLDRun() and RC200CPLDEnable() before calling this macro. You must call this macro before a ny calls to RC200SendProtocolWrite() or RC200SendProtocolRead().

  • Page 71: Expansion Port Pins

    You must call RC200SendProtocolEnable() before using this macro. 5.20 Expansion port pins extern macro expr RC200ExpansionPins; Description Pin list for the ATA-style expansion connector on the RC200. You can use this to create your own interface to this connector. Page 71 www.celoxica.com...

  • Page 73: Index

    RC200/203 PSL reference expansion port pins.........30, 73 6 Index Expert RC200 ..........36 FPGA ............70, 72 audio ............28, 55 operation modes audio clock reading data from host PCPC 21, 73 boosting input reading from 21, 73 gain level reconfiguring 19, 20, 70...
  • Page 74 RC200/203 PSL reference RC200............8, 36 RC200EthernetReadEnd ......68 board version RC200EthernetRun ........66 clock definitions RC200EthernetWrite........69 clock rate RC200EthernetWriteBegin ......69 connectors RC200EthernetWriteEnd ......70 data sheets RC200ExpansionPins........73 devices 13, 34 RC200LED*Write ..........38 installation RC200LEDWriteMask........38 overview 9, 13, 14 RC200PL1RAM*Read ........42 part numbers RC200PL1RAM*Run ........41...
  • Page 75 RC200/203 PSL reference RC200SmartMediaSetAddress ....62, 63 PnCS signal SmartMedia Detect signal RC200SmartMediaWrite....... 64 SmartMedia...........22 RC200TouchScreenReadRaw ..... 46 address structure RC200TouchScreenReadScaled ....47 checking for errors 63, 65 RC200TouchScreenRun ......46 completing a read or write 63, 65 RC200VideoInReadPixelPairYCrCb .... 52 configuring the FPGA RC200VideoInRun........
  • Page 76 RC200/203 PSL reference writing data Page 76 www.celoxica.com...

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