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Raymond Jimenez DSP56k User Manual

Raymond jimenez dsp56k mp3 player user’s manual
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The DSP56k MP3 Player User's Manual
Raymond Jimenez
June 8, 2011

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  • Page 1 The DSP56k MP3 Player User’s Manual Raymond Jimenez June 8, 2011...
  • Page 3 Introduction Congratulations! You’re the new owner of a DSP56k-based MP3 player. This unit was designed by Raymond Jimenez personally, with emphasis in mind audiophile-quality playback expandibility usability To get started, please flip to the Quick Start Guide on page 3, which guides you through the basics necessary just to listen to an MP3 file.
  • Page 4 INTRODUCTION...

  • Page 5: Table Of Contents

    Contents Introduction Quick Start Guide 1 Quick Start Guide User Guide 2 Basic Usage 2.1 The Display ......2.2 Playing Songs .
  • Page 6 CONTENTS 4.5 IDE ....... . 19 4.6 DRAM ....... 19 5 Memory Map and Registers 6 Timing 6.1 Timing Targets .
  • Page 7 CONTENTS 9 Release Notes/Errata 9.1 Known Bugs ......241 9.2 Known Limitations ......242...
  • Page 8 viii CONTENTS...
  • Page 9 List of Figures 1.1 Main MP3 Playback Unit ....1.2 MP3 Player’s Keypad ..... . . 1.3 LCD Display Unit .
  • Page 10 LIST OF FIGURES...
  • Page 11 List of Tables 4.1 DAC Startup Mode ......18...
  • Page 12 LIST OF TABLES...

  • Page 13: I Quick Start Guide

    Part I Quick Start Guide...

  • Page 15: Quick Start Guide

    Chapter 1 Quick Start Guide Your DSP56k MP3 player comes complete with one MP3 hard drive, one main playback unit (Fig 1.1), one keypad (Fig 1.2), one display unit (Fig 1.3), and one power supply. In order to play MP3s from the hard drive, connect the main playback unit to the keypad, display, and hard drive, and power up the hard drive using its own power supply.
  • Page 16 CHAPTER 1. QUICK START GUIDE Figure 1.1: Main MP3 Playback Unit...
  • Page 17 Figure 1.2: MP3 Player’s Keypad...
  • Page 18 CHAPTER 1. QUICK START GUIDE Figure 1.3: LCD Display Unit...

  • Page 19: User Guide

    Part II User Guide...

  • Page 21: Basic Usage

    Chapter 2 Basic Usage The Display This MP3 player comes with one main display unit, a 2x40 character liquid- crystal display (LCD). At all times, the display reflects the status of the unit, in addition to its current operation and song (Fig 2.1). 1.

  • Page 22: Playing Songs

    CHAPTER 2. BASIC USAGE 4. Status: This indicates the unit’s current status, and will be one of “Play” ”Stop” “Rev” “FFwd” or “Err”. An appropriate icon will also be displayed. 5. Volume: This indicates the current volume setting, in terms of atten- uation.

  • Page 23: Advanced Features

    Microsoft Windows [Version 6.1.7600] Copyright (c) 2009 Microsoft Corporation. All rights reserved. C:\Users\Raymond Jimenez> Then type H:\ where H is the drive letter of the newly attached drive. Move the music file that you would like to add to the drive, and then go back to the command prompt and type mksong "MP3 File.mp3"...

  • Page 24: Playing Non-Mp3 Files

    CHAPTER 3. ADVANCED FEATURES Playing non-MP3 files Due to the nature of our player, non-MP3 files are no different than MP3 files. In order to add a non-MP3 file, follow the steps above and the song should appear normally, available for play. When adding the non-MP3 files, keep in mind: If a file’s bitrate is too high, it may stutter or not play Only stereo 16-bit, 48000Hz audio (or less) is supported...

  • Page 25: Developer Documentation

    Part III Developer Documentation...

  • Page 27: System Overview

    Chapter 4 System Overview Introduction to Architecture A general overview of the system’s architecture can be seen from Figure 4.1. Since our main purpose is to play music, not to act as a multipurpose appliance, we can make several assumptions: 1.

  • Page 28: Mp3 Decoder

    CHAPTER 4. SYSTEM OVERVIEW Figure 4.1: Overall System Block Diagram When the MP3 decoder requests more data via an interrupt, we begin sending it data via a serial port, which is handled via DMA. We then begin manually fetching data in a polling loop from the hard drive, as before, to fill another buffer.
  • Page 29 4.3. MP3 DECODER Figure 4.2: Main Board Components...

  • Page 30: Dac/Analog Stage

    CHAPTER 4. SYSTEM OVERVIEW Parameter Value Upsampling Rate 96kHz Input Word Length 16-bit Digital Filter Response 3 Attenuation -27dB Volume Ramp Auto Detect MCLK Anti-Clip Mode Table 4.1: DAC Startup Mode of board space. DAC/Analog Stage The DAC and analog stage have been optimized for high-quality, audiophile- grade audio output;...

  • Page 31: Ide

    4.5. IDE Our MP3 decoder’s maximum I S output is 96kHz, 16-bit stereo with a 12.288MHz master clock (MCLK = 128fs), so the input parameters were set accordingly. The digital filter was set for the best sound (response 3 is a minimum-phase, slow-rolloff...
  • Page 32 CHAPTER 4. SYSTEM OVERVIEW Figure 4.3: DRAM Block Diagram...
  • Page 33 4.6. DRAM 8. deassert CAS, RAS, both latch OE’s Due to the fact that we use TA, the DRAM timings are specified not in the CPU but by the CPLD. For more details, please see the CPLD DRAM code on page 73.
  • Page 34 CHAPTER 4. SYSTEM OVERVIEW...

  • Page 35: Memory Map And Registers

    Chapter 5 Memory Map and Registers...
  • Page 36 DSP56k memory map Program space Address X space Address Y space Address 0xFFFFFF - 0xFFFFFF - 0xFFFFFF Internal I/O 0xFFFF80 Internal I/O 0xFFFF80 Reserved 0xFF00C0 Bootstrap ROM 0xFF0000 Internal Reserved 0xFFEFFF Internal Reserved 0xFFEFFF 0xFF0000 0xFF0000 0xD3FFFF Boot ROM (256k x 8 bits)
  • Page 37 DSP56k memory map Register Value Comments Hex Equiv. - mode 9, most options turned off, 1000 0000 0000 no TA OMR Register: 1000 0000 1001 synchronization 0x100809 - using 20MHz crystal, we have a multiplication factor of 4. external driven...
  • Page 38 CHAPTER 5. MEMORY MAP AND REGISTERS...

  • Page 39: Timing

    Chapter 6 Timing There are a number of timing diagrams that we have worked on in order to make sure our circuit works. However, these timing diagrams may not reflect reality due to parasitic effects that we haven’t taken into account; the wait states presented here are simply minimum settings.
  • Page 40 -10ns 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 80MHz quart [18..0] address ACSDel ACSDel RDNA quart [15..0] data RDtoVAL data sampled [15..0]...
  • Page 41 Page 3 SRAM Read, CPU SYMBOL DEFINITION DESCRIPTION 12.5ns 12.5ns 12.5ns Clock Period (80MHz) 3.125ns 3.125ns 3.125ns =ENG(NOM("Tc")/4) 1/4 clock period quart wait states address to chip select delay ACSDel RD deassertion to data not valid (data hold time) 21ns 21ns =ENG((NOM("Ws") + 1) * address valid width...
  • Page 42 Page 4 SRAM Read, SRAM SYMBOL DEFINITION DESCRIPTION 15ns Address Access Time 15ns Chip Select Access Time Output Enable Low to Output Valid Output Hold from Address Change...
  • Page 43 -40ns -20ns 20ns 40ns 60ns 80MHz quart [15..0] address ACSDel ACSDel [15..0] data out...
  • Page 44 Page 3 SRAM Write, CPU SYMBOL DEFINITION DESCRIPTION 12.5ns 12.5ns 12.5ns Clock Period (80MHz) 3.125ns 3.125ns 3.125ns =ENG(NOM("Tc")/4) quarter-clock period quart 33.5ns 33.5ns 33.5ns =ENG((NOM("Ws") + 1) * Address valid NOM("Tc")-4000) wait states Address to chip select delay ACSDel 7.375ns 7.375ns =ENG( (3*NOM("Tc")/4) - Address and AA valid to WR...
  • Page 45 Page 4 SRAM Write, SRAM SYMBOL DEFINITION DESCRIPTION 15ns write cycle time 10ns address valid to end of write 10ns chip select low to end of 10ns write pulse width data valid to end of write...

  • Page 46: Rom

    CHAPTER 6. TIMING 6.1.2...
  • Page 47 -40ns -20ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns 200ns220ns 80MHz quart [18..0] address ACSDel ACSDel RDNA quart [15..0] data RDtoVAL data sampled [15..0]...
  • Page 48 Page 2 ROM Read, CPU SYMBOL DEFINITION DESCRIPTION 12.5ns 12.5ns 12.5ns Clock Period (80MHz) 3.125ns 3.125ns 3.125ns =ENG(NOM("Tc")/4) 1/4 clock period quart wait states address to chip ACSDel select delay RD deassertion to data not valid (data hold time) 146ns 146ns =ENG((NOM("Ws") address valid width...
  • Page 49 Page 3 ROM Read, ROM SYMBOL DEFINITION DESCRIPTION 120ns Address to Output Delay 120ns Chip Select Access Time 50ns Output Enable Low to Output Valid Output Hold from Address Change...

  • Page 50: Dram

    CHAPTER 6. TIMING 6.1.3 DRAM...
  • Page 51 -20ns 20ns 40ns 60ns 80ns 100ns 120ns [15..0] A[0−18] RDNA BDELAY BDELAY [15..0] AB[0−18] BDELAY BDELAY CPLD−DELAY CPLD−DELAY CPLD−CAS CPLD−CASW CPLD−ROW CPLD−COLUMN BDELAY CPLD−RC−INTER DRAM addr [15..0] DRAM data [15..0] BDELAY DB[0−24] to CPU [15..0]...
  • Page 52 Page 3 CPU timing SYMBOL DEFINITION DESCRIPTION 4.1ns general buffer delay BDELAY 108.5ns address cycle time 12.5ns clock period -13.625ns 117 - RD RDNA deassertion to address not valid wait states 15ns average CPLD CPLD-DELAY gate delay for combinatorials 12.5ns intervening time CPLD-RC-INTER between row...
  • Page 53 Page 4 DRAM timing - 70ns FPM SYMBOL DEFINITION DESCRIPTION 70ns 10000ns RAS pulse width row address setup data hold time 10ns row address hold 70ns RAS to data 15ns 10000ns CAS pulse width 35ns column addr to data 20ns CAS to data...
  • Page 54 -20ns 20ns 40ns 60ns 80ns 100ns [15..0] A[0−18] WRNA BDELAY BDELAY [15..0] AB[0−18] BDELAY BDELAY CPLD−DELAY CPLD−DELAY CPLD−CAS CPLD−CASW CPLD−ROW CPLD−COLUMN BDELAY CPLD−RC−INTER DRAM addr [15..0] [15..0] D[0−23] BDELAY BDELAY [15..0] DB[0−23]...
  • Page 55 Page 3 CPU timing SYMBOL DEFINITION DESCRIPTION 4.1ns general buffer delay BDELAY -68.875ns data setup time 96ns address cycle time 13.625ns data hold time 12.5ns clock period -11.625ns 103 - WR WRNA deassertion to address not valid wait states 15ns average CPLD CPLD-DELAY gate delay for...
  • Page 56 Page 4 DRAM timing - 50ns EDO SYMBOL DEFINITION DESCRIPTION 50ns 10000ns RAS pulse width row address setup row address hold 10000ns CAS pulse width data setup column address hold data hold...

  • Page 57: Ide

    6.1. TIMING TARGETS 6.1.4...
  • Page 58 -60ns -40ns -20ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns [15..0] A[0−2] delay delay [15..0] AB[0−2] AD−AAR AD−AAR AAR0 AAR−CS AAR−CS RDANV delay delay DIOR...
  • Page 59 Page 2 CPU timings SYMBOL DEFINITION DESCRIPTION 4.5ns address buffer delay delay between AD-AAR address bus and 15ns delay between AAR AAR-CS and CS (CPLD) 12.5ns CPU clock period Wait states -54.25ns RD deassertion to RDANV address not valid -117.625ns RD pulse width 146ns address pulse...
  • Page 60 Page 3 IDE timings SYMBOL DEFINITION DESCRIPTION 25ns address valid to DIOR/DIOW setup 120ns cycle time 145ns minimum address assertion...

  • Page 61: Dac (Via Sci)

    6.1. TIMING TARGETS 6.1.5 DAC (via SCI) Please note that these timings are not actually in effect; we decided to in- terface via ESSI instead, which is adjustable enough that we were able to directly tune DSP parametrs to fit DAC timing.
  • Page 62 -1us -800ns -600ns -400ns -200ns 200ns 400ns 600ns 800ns 1.2us 1.4us 1.6us siclk 1MHz sclk SIIDS hold setup SIIDS [15..0]...
  • Page 63 Page 2 CPU output SYMBOL DEFINITION DESCRIPTION 12.5ns 12.5ns internal clock 243.75ns hold time after hold rising edge serial clock period sc c -239.25ns setup time before setup falling edge...
  • Page 64 Page 3 decoder requirements SYMBOL DEFINITION DESCRIPTION 960ns clock requirement siclk 50ns data setup time SIIDS 50ns data hold time SIIDH...

  • Page 65: Mp3 Decoder (Via Sci)

    6.1. TIMING TARGETS 6.1.6 MP3 Decoder (via SCI) Please note that these timings are not actually in effect; we decided to in- terface via ESSI instead, which is adjustable enough that we were able to directly tune DSP parametrs to fit MP3 decoder timing. Additionally, SCI did not support DMA, so we switched to ESSI for a speed boost.
  • Page 66 -1us -800ns -600ns -400ns -200ns 200ns 400ns 600ns 800ns 1.2us 1.4us 1.6us siclk 1MHz sclk SIIDS hold setup SIIDS [15..0]...
  • Page 67 Page 2 CPU output SYMBOL DEFINITION DESCRIPTION 12.5ns 12.5ns internal clock 243.75ns hold time after hold rising edge serial clock period sc c -239.25ns setup time before setup falling edge...
  • Page 68 Page 3 decoder requirements SYMBOL DEFINITION DESCRIPTION 960ns clock requirement siclk 50ns data setup time SIIDS 50ns data hold time SIIDH...

  • Page 69: Lcd Display

    6.2. TIMING SIMULATION (CPLD) 6.1.7 LCD Display Please note that there are no current timing diagrams for the LCD display; our current design uses latches and the CPLD to interface between the LCD and the rest of the system. Timing Simulation (CPLD) For insurance that our CPLD design would work, we simulated several sce- narios.
  • Page 70 0.0 ns 200.0 ns 400.0 ns 600.0 ns 800.0 ns 1,000.0 ns 1,200.0 ns 1,400.0 ns CLOCK DISPCS DREFRESH DRAS DCAS DCOLL DROWL DLATCHEN RESETCPU 0.0 ns 200.0 ns 400.0 ns 600.0 ns 800.0 ns 1,000.0 ns 1,200.0 ns 1,400.0 ns Z:\cpld\INPUT Page 1 of 1...

  • Page 71: Schematics

    Chapter 7 Schematics Prototyping Board/CPU...
  • Page 72 0.1 uf 0.1 uf 0.1 uf 0.1 uf 0.1 uf 0.1 uf 0.1 uf 0.1 uf 0.1 uf 0.1 uf 0.47 uf Title DSP56k MP3 Main Board 10 uf 10 uf Size Number Revision CON6 Date: 2011/06/13 Sheet File: Z:\documentation\..\56k3.sch...

  • Page 73: Cpld

    7.2. CPLD CPLD...
  • Page 74 MP3 Data Request I/O31 Y1/RESET Y2/SCLK Vcc5 Res1 Res1 ISPEN Vcc5 ISPLSI1016CC LED0 0.1 uf 0.1 uf SW-SPST Vcc5 Res1 Res1 MAX809 Man. RESET RESET Title CPLD/Reset Logic Size Number Revision Letter Date: 2011/06/13 Sheet File: Z:\documentation\..\cpld.SchDoc Drawn By: Raymond Jimenez...

  • Page 75: Mp3 Decoder Daughterboard

    7.3. MP3 DECODER DAUGHTERBOARD MP3 Decoder Daughterboard...
  • Page 76 Vcc18 Vcc33 Vcc18 Res1 4.99k .1uF .1uF .1uF .1uF Res1 Cap Pol3 Cap Pol3 LM317KC Cap Pol3 10uF 10uF 10uF Res Adj1 2.5k Title MP3 Decoder Daughterboard Size Number Revision Letter Date: 2011/06/13 Sheet File: Z:\documentation\..\mp3daughter.SchDoc Drawn By: Raymond Jimenez...

  • Page 77: Dac/Analog Out

    7.4. DAC/ANALOG OUT DAC/Analog Out...
  • Page 78 100pF 220pF Vcc5 Vcc475 Vcc5 VccAud33 Vcc475 VccAud33 100nF 100nF 100nF Cap Pol1 Cap Pol1 100pF 100pF 100nF 100nF TPS973475 TPS97333 100nF 100nF Title DAC/Analog Output Stage Size Number Revision Letter Date: 2011/06/13 Sheet File: Z:\documentation\..\analogout.SchDoc Drawn By: Raymond Jimenez...

  • Page 79: Display/Keypad

    7.5. DISPLAY/KEYPAD Display/Keypad...
  • Page 80 CPLD I/O 9 LCD DB[0-7] 74ALS573 RPot 74ALS573 CPLD I/O 13 LCD-DIP MTC-S40200XRGHS w/o backlight CPU DB[0-23] KEYPAD4X4 CPLD I/O 10 CPLD I/O 19 0.1u 74C923 Title LCD Display/Keypad Size Number Revision Letter Date: 2011/06/13 Sheet File: Z:\documentation\..\display.SchDoc Drawn By: Raymond Jimenez...

  • Page 81: Ide Interface

    7.6. IDE INTERFACE IDE Interface...
  • Page 82 DIOR Ground IORDY CSEL DMACK Ground INTRQ (obsolete) CPU AB9 PDIAG/CBLID LED0 CPU AB8 CPU AB10 CPU AB11 CPU AB12 DASP Ground IDE Connector Title IDE Interface Size Number Revision Letter Date: 2011/06/13 Sheet File: Z:\documentation\..\ide.SchDoc Drawn By: Raymond Jimenez...

  • Page 83: Dram & Address Multiplexing

    7.7. DRAM & ADDRESS MULTIPLEXING DRAM & Address Multiplexing...
  • Page 84 PRD4 DQ30 CPLD I/O 26 DQ31 CPLD I/O 27 DQ32 CPU BWR DRAM4MX32 CPU DB[0-23] Vcc5 100nF 100nF 100nF 100nF 100nF 100nF Title DRAM & Address Multiplexing Size Number Revision Letter Date: 2011/06/13 Sheet File: Z:\documentation\..\dram.SchDoc Drawn By: Raymond Jimenez...

  • Page 85: Annotated Code

    Chapter 8 Annotated Code CPLD Code The CPLD code acts as the glue that holds the system’s chip select and arbitration logic together. As a result, we have several very important files: main.abl ties everything together. It ties the logical blocks that follow with real pins;...
  • Page 86 main.abl 2011/03/30 // main glue for CPLD logic MODULE main; TITLE 'Main CPLD Logic'; reset interface (Reset1, Reset2 -> Reset); chipsel interface (AA0, AA2, AB14, AB13, AB12, BRD, BWR, Clock -> DispCS, KeypadCS, IDERD, IDEWR, DataDir, DispEnable); interrupt interface (InIRQ3, InIRQ2, InIRQ1, InIRQ0, Reset, Clock -> IRQ3, IRQ2, IRQ1, IRQ0);...
  • Page 87 main.abl 2011/03/30 DLatchEn // I/O pin 22 // I/O pin 23 DRefresh // I/O pin 24 DRAS // I/O pin 25 DCAS // I/O pin 26 DRowL // I/O pin 27 DColL // I/O pin 28 // I/O pin 29 // I/O pin 30 MP3Dreq // I/O pin 31...
  • Page 88 main.abl 2011/03/30 // active high per the MM74C923 datasheet. // DRAM takes up a lot of stuff... d1.CS = AA2; d1.Reset = r1.Reset; d1.BWR = BWR; d1.BRD = BRD; d1.RefreshEn = DRefresh; d1.Clock = Clock; DRowL = d1.RowLatch; DColL = d1.ColLatch; DRAS = d1.RAS;...
  • Page 89 2011/02/14 //////////////////////////////////////////////////////////////////////// // ABEL file for DSP56k board RESET logic // for the Lattice ispLSI 2016E CPLD // Author: Raymond Jimenez... original file from Alexander Hu/Suresh Situala // Revision History: April 18, 2009 Initial Revision April 24, 2009 Retracted comment about pin numbers. The...
  • Page 90 2011/03/22 /////////////////////////////////////////////////////////////////////// // ABEL file for DSP56k board chip select logic // for the Lattice ispLSI 1016E CPLD // Author: Raymond Jimenez... original file from Alexander Hu/Suresh Situala // Revision History: April 18, 2009 Initial Revision April 24, 2009 Retracted comment about pin numbers.
  • Page 91 chipsel.abl 2011/03/22 // our address set Addr = [AB14, AB13, AB12] //state counter S1..S0 node ISTYPE 'reg'; // display enable state counter DispState = [S1..S0]; // we have 4 states pretty much. define using a gray code to minimize terms. EnableSetup = [0,0];...
  • Page 92 chipsel.abl 2011/03/22 // selected. IDEWR = AA0 & ((Addr == # (Addr == & BWR; IDERD = AA0 & ((Addr == # (Addr == & BRD; // we now deal with the display enable. our display is pretty // slow, so we do this manually. DispState.CLK = Clock;...
  • Page 93 2011/02/13 //////////////////////////////////////////////////////////////////////// // ABEL file for DSP56k board interrupt logic // for the Lattice ispLSI 2016E CPLD // Author: Raymond Jimenez... original file from Alexander Hu/Suresh Situala // Revision History: April 18, 2009 Initial Revision April 24, 2009 Retracted comment about pin numbers. The...
  • Page 94 interrpt.abl 2011/02/13 interrupt...
  • Page 95 2011/03/27 //////////////////////////////////////////////////////////////////////// // ABEL file for DSP56k board DRAM controller // for the Lattice ispLSI 2016E CPLD // Author: Raymond Jimenez... original file from Alexander Hu/Suresh Situala // Revision History: April 18, 2009 Initial Revision April 24, 2009 Retracted comment about pin numbers. The...
  • Page 96 dram.abl 2011/03/27 Clock pin; scount = [QS2..QS0]; //counter for multiple clock cycles, setup time hcount = [QH2..QH0]; //counter for hold timing EQUATIONS hcount.clk = Clock; hcount.ar = Reset; scount.clk = Clock; scount.ar = Reset; sreg.clk = Clock; sreg.ar = Reset; BG.clk = Clock;...
  • Page 97 dram.abl 2011/03/27 IF(BRD) then rw_RAS with {scount := ELSE IF(BWR) then rw_RAS with {scount := ELSE rw_rowsetup; STATE rw_RAS: RAS = 1; CAS = 0; RowLatch = 1; TA := 0; WE = 0; (scount == then rw_colsetup with scount := 0; ELSE rw_RAS with...
  • Page 98 dram.abl 2011/03/27 ELSE rw_PC with {scount := scount + 1; STATE CBR_CAS_LOW: TA := 1; RAS = 0; CAS = 1; WE = 0; RowLatch = 1; (scount == then CBR_RAS_LOW with {scount :=0 ELSE (CBR_CAS_LOW) with {scount := scount + STATE CBR_RAS_LOW: TA := 1;...

  • Page 99: Bootup Code (Crt0.Asm)

    8.2. BOOTUP CODE (CRT0.ASM) Bootup Code (crt0.asm) crt0.asm contains the system’s bootloader; this code is executed first and copies all of the system code from RAM into ROM in order to match the compiler’s expectations. Please note that when booting via this code, program space is over- written with ROM contents unless the ROM-copy procedures are com- mented out.
  • Page 100 ; This file is the initial bootup code that's executed from ROM. ; This file is heavily adopted from the standard crt0.asm ; that was included with the DSP56k developer toolkit. ; Perhaps most importantly, this file also incorporates the memory map ;...
  • Page 101 crt0.asm 2011/06/13 global F__stack_safety F__stack_safety 1024 TOP_OF_MEMORY $a07fff ;this is the top of our memory in X space; anything below this is SRAM ; and is writable BOTTOM_OF_MEMORY $a00000 ;and then DSIZE is the bottom of our memory in X space. ;...
  • Page 102 crt0.asm 2011/06/13 movep #$d00609,x:$fffff8 ; AA1 = ROM (forced due to mode 9) movep #$200431,x:$fffff7 ; AA2 = DRAM (via our own controller) movep #$a00831,x:$fffff6 ; AA3 = SRAM end_xload ;now that we can access the ROM, unpack x-space constants down there ;judiciously adapated from the bootcode of the DSP56309 per the user manual move #$5400,a0...
  • Page 103 crt0.asm 2011/06/13 stop ; all done endsec section time_counter global F__time F__time endsec section io_primitives global F__send F__send global F__receive F__receive endsec ; The following section, dummy_call, is used for doing command-line ; function calls on the ADS and simulator. If you aren't going to use ;...
  • Page 104 crt0.asm 2011/06/13 ; called function (because of the prologue code which is after the jsr ; in dummy_call). ; The prologue code decrements r6 by the amount used by the arguments ; to the target function plus one (to move us back to where the return ;...
  • Page 105 crt0.asm 2011/06/13 movem p:(r0)+,r2 ; source start movem p:(r0)+,r3 ; size of expicitly initialized block movem p:(r0)+,r4 ; size of zero initialized block r3,_lab2 movem p:(r2)+,x0 move x0,x:(r1)+ _lab2 r4,_lab3 move a1,x:(r1)+ _lab3 _lab1 endsec ; we reserve memory space here to prevent things from going awry. ;...
  • Page 106 crt0.asm 2011/06/13 $700000 ;0xa00000 - 0x300000 endsec ;cover the DRAM for now because it is not functional section dram_temp_reservation x:$200000 ;starts at 0x200000 $100000 ;0x300000 - 0x200000 (1MByte ostensibly) endsec ;cover the gap between DRAM and peripherals section x_memory_reserved2 x:$104000 ;starts at 0x104000 $fc000 ;0x200000 - 0x104000...

  • Page 107: Queues (Queues.asm)

    8.3. QUEUES (QUEUES.ASM) Queues (queues.asm) queues.asm contains basic circular queue code. This code is used mainly by the display code.
  • Page 108 - checks if a queue is full ; enqueue - adds a word to the back of the queue ; dequeue - grabs the word from the front of the queue ; Raymond Jimenez ; EE/CS 52 ; February 16, 2011 ; Revision history: ; 2011/2/16...
  • Page 109 ; Data Structures: None. ; Registers changed: None. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global queue_init ;prologue queue_init: ;assembly entry point ;save registers we use: move r3,ssh...
  • Page 110 ; Registers changed: None. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global queue_empty queue_empty: ;assembly entry point ;we use the accumulators due to CMP, so save them: PUSH_ACC...
  • Page 111 ; Registers changed: None. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global queue_full queue_full: ;assembly entry point ;we use the accumulators due to CMP/SUB, so save them: PUSH_ACC ;save x0, x1...
  • Page 112 queues.asm 2011/02/22 #>1,a ;we increment the pointer to the next address x1,a ;we see if the pointer is too large (x1<a) queue_full_nowrap ;if tail >= size, wrap to zero ;jgt queue_full_wrap queue_full_wrap: ;we reset our tail pointer to 0 to wrap queue_full_nowrap: x0,a ;test to see if they are the same...
  • Page 113 ; Registers changed: a2, a1, a0 (a) ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global dequeue dequeue: ;assembly entry point ;we use the accumulators due to CMP/INC, so save them: PUSH_ACC ;and now save x0 &...
  • Page 114 ; Known Bugs: None. ; Special Notes: much of this code is ill-defined as to what to do when ; interrupted, so we block of interrupts for the update portion. ; Revision History: 2011/02/16 Raymond Jimenez first revision global enqueue...
  • Page 115 queues.asm 2011/02/22 enqueue: ;assembly entry point ;save all registers we use so we can restore later ;we use the accumulators due to CMP/SUB, so save them: PUSH_ACC ;then we used n0/x0, so save them: move x0,ssh move n0,ssl ;check if there is any space left to queue enqueue_block_loop: queue_full ;check if queue is full...
  • Page 116 queues.asm 2011/02/22 ;return from subroutine ;end function endsec...

  • Page 117: Display (Display.inc, Display.asm)

    8.4. DISPLAY (DISPLAY.INC, DISPLAY.ASM) Display (display.inc, display.asm) display.inc contains important defines and constants for the display code, located in display.asm. display.asm contains the display code. We assume a HD44780-compatible LCD that is connected to the CPLD and address/data busses as in the LCD schematic.
  • Page 118 ; display.inc ; This file offers several key includes for the display functionality, ; such as size of memory buffers and constants, etc. ; Revision History: ; 2011/2/15 Raymond Jimenez initial revision ; 2011/6/12 Raymond Jimenez cleaned up for documentation ;allocate 256 words for the LCD queue...
  • Page 119 ; void display_update(void) -- updates the LCD; should be called from a timer interrupt ; void display_init(void) - initializes the LCD structures and hardware; should be called before any other display calls are made ; Revision History: ; 2011/2/15 Raymond Jimenez initial revision ; 2011/6/12 Raymond Jimenez cleaned up for documentation section display ;here's our declaration for our file...
  • Page 120 display.asm 2011/06/13 clear_artist_str: 1234567890123456789012345678901234567890 " " ,$00 clear_title_str: 1234567890123456789012345678901234567890 " " ,$00 clear_time_str: 1234567890123456789012345678901234567890 " ",$00 clear_vol_str: 1234567890123456789012345678901234567890 " ",$00 time_minute_sep: ":",$00 time_tenths_sep: ".",$00 atten_prefix: "-",$00 atten_suffix: "dB",$00 ;we have several constants corresponding to what to display ; for a given status: status_play_str: "|>...
  • Page 121 display.asm 2011/06/13 status_fastfwd_str ;1 - fastfwd status_reverse_str ;2 - reverse status_idle_str ;3 - idle status_illegal_str ;4 - illegal ; PROGRAM CODE STARTS HERE ;and finally, program code global display_update display_update: ;assembly entry only ; we are here from an interrupt, so be quick and careful ;...
  • Page 122 ; Data Structures: None. ; Registers changed: None. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/17 Raymond Jimenez first revision global Fdisplay_init Fdisplay_init: ;C entry point ;standard C-caller prologue move #0,n6 ; k is the amount of local space needed.
  • Page 123 display.asm 2011/06/13 display_init_loop_end : ;set our output mode: display on move #>$0c,a enqueue move #>$38,a ;and make 2-line mode a thing. enqueue ;and let the display interrupt take care of it ;end of body code, now restore all registers move ssl,r1 ;restore r1 move...
  • Page 124 ; Registers changed: None. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global display_write_string display_write_string : ;assembly entry point ;save all registers we use so we can restore later...
  • Page 125 display.asm 2011/06/13 POP_ACC move ssl,r1 ;restore r1 move ssh,r0 ;restore r0 ;end of body code, now restore all registers ;return from subroutine ;end display_write_string ; display_set_loc ; Functional Specification ; Description: display_set_loc allows one to control the location of ; where a string will be blit onto the LCD display. For simplicity, it takes ;...
  • Page 126 2011/06/13 ; Revision History: 2011/02/16 Raymond Jimenez first revision global display_set_loc display_set_loc: ;assembly entry point ;save all registers we use so we can restore later move r0,ssh ;we use r0 of course. ;and we change the accumulator PUSH_ACC ;alright, we alter a to include our nice bit-mask ;...
  • Page 127 ; Data Structures: None. ; Registers changed: None. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global Fdisplay_status Fdisplay_status: ;C entry point ;standard C prologue move #0,n6 ; k is the amount of local space needed.
  • Page 128 ; Data Structures: None. ; Registers changed: None. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global Fdisplay_title Fdisplay_title: ;C entry point ;standard C prologue move #0,n6 ; k is the amount of local space needed.
  • Page 129 display.asm 2011/06/13 move ssh,x:(r6)+ ; save the return address. move (r6)+n6 ; allocate local stack space of size k. ;save all registers we use so we can restore later move r0,ssh move r1,ssl ;we also change b, so preserve it PUSH_ACC ;we first clear the title field in the 2nd row move...
  • Page 130 ; Data Structures: None. ; Registers changed: None. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global Fdisplay_artist Fdisplay_artist: ;C entry point ;standard C prologue move #0,n6 ; k is the amount of local space needed.
  • Page 131 ; Outputs: Time on the screen. ; Error Handling: None. ; Algorithm: None. ; Data Structures: None. ; Registers changed: None. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision...
  • Page 132 display.asm 2011/06/13 global Fdisplay_time Fdisplay_time: ;C entry point ;standard C prologue move #0,n6 ; k is the amount of local space needed. move ssh,x:(r6)+ ; save the return address. move (r6)+n6 ; allocate local stack space of size k. ;save all registers we use so we can restore later PUSH_ACC PUSH_ACC move...
  • Page 133 display.asm 2011/06/13 move #>600,x0 imod_x0a ; a = a%600 ;we divide by ten to get seconds: move #>10,x0 idiv_x0a ; a = floor(a/10) ;and we turn this into a string and blit it: move #convert_temp_buf,r0 dec2string display_write_string ;we write the divider between tenths and seconds: move #time_tenths_sep,r0 display_write_string...
  • Page 134 ; Data Structures: None. ; Registers changed: None. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global Fdisplay_volume Fdisplay_volume ;C entry point ;standard C prologue move #0,n6 ; k is the amount of local space needed.
  • Page 135 display.asm 2011/06/13 get_atten ;we now work with the attenuation #ATTEN_SHIFT,a,a ;shift over to get integer dB ;and we convert to a number and write it to the screen move #convert_temp_buf,r0 dec2string display_write_string ;this is followed by writing the " dB" move #atten_suffix,r0 display_write_string...

  • Page 136: Keypad (Keyfunc.inc, Keyfunc.asm)

    CHAPTER 8. ANNOTATED CODE Keypad (keyfunc.inc, keyfunc.asm) keyfunc.inc contains important definitions for the keypad code, mostly keyscan code definitions. keyfunc.asm contains the keypad processing code and the event handler installed to handle the keypad IRQ.
  • Page 137 ; keyfunc.inc ; This file contains several important definitions that the keypad code ; depends on, such as the definitions for the keycodes. ; Revision History ; 2011/2/16 Raymond Jimenez initial revision ; 2011/6/12 Raymond Jimenez cleaned up for documentation ;if our translated key value is equal to this, don't...
  • Page 138 ; Fkey_available - call to see if there is a new key available for processing ; Fgetkey - call to get a key; blocks on key input ; Revision History ; 2011/2/16 Raymond Jimenez initial revision ; 2011/6/12 Raymond Jimenez cleaned up for documentation...
  • Page 139 keyfunc.asm 2011/06/13 key_trans_table: KEY_NOP ;key 0 - don't do anything KEY_NOP ;key 1 - don't do anything KEY_NOP ;key 2 - don't do anything KEY_NOP ;key 3 - don't do anything KEY_NOP ;key 4 - don't do anything KEY_TRACKUP ;key 5 - track up KEY_VOLUP ;key 6 - increase volume KEY_RPTPLAY...
  • Page 140 ; Registers changed: None. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global keypad_handler keypad_handler: ;assembly entry point ;remember to save all registers changed! interrupt handler, so very ; important!
  • Page 141 ; Data Structures: None. ; Registers changed: a. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global Fkey_init Fkey_init: ;C entry point ;standard C prologue move #0,n6 ; k is the amount of local space needed.
  • Page 142 ; Data Structures: None. ; Registers changed: a. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global Fkey_available Fkey_available: ;C entry point ;standard C prologue move #0,n6 ; k is the amount of local space needed.
  • Page 143 ; Error Handling: None. ; Algorithm: None. ; Data Structures: None. ; Registers changed: a. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global Fgetkey Fgetkey: ;C entry point...
  • Page 144 keyfunc.asm 2011/06/13 ;standard C prologue move #0,n6 ; k is the amount of local space needed. move ssh,x:(r6)+ ; save the return address. move (r6)+n6 ; allocate local stack space of size k. ;save all of the registers we use move r0,ssh ;save both r0/n0...

  • Page 145: Ide Interface

    8.6. IDE INTERFACE IDE Interface ide.inc contains important definitions for the IDE code, mostly IDE standard definitions. ide.asm contains the IDE block reading code, as well as the initialization code.
  • Page 146 ide.inc 2011/03/30 ;the various IDE register addresses ; some are read only, others write only, ; most r/w. please check the ATA spec for details. ;the addresses come from how we've wired up the ; bus to the IDE connector. IDE_DATA_REG $103000 IDE_FEATURE_REG...
  • Page 147 ; Inputs: None. ; Outputs: None. ; Error Handling: None. ; Algorithm: None. ; Data Structures: None. ; Registers changed: None. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/03/08 Raymond Jimenez first revision...
  • Page 148 ide.asm 2011/03/30 global Fsetup_ide Fsetup_ide: ;C entry point ;standard C prologue move #0,n6 ;k is the amount of local space move ssh,x:(r6)+ ;save the return address move (r6)+n6 ;allocate local stack space of size k ;save all registers we use so we can restore later move r0,ssh ;wait until the drive is ready for selecting...
  • Page 149 ; Registers changed: None. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/03/08 Raymond Jimenez first revision global wait_for_ide wait_for_ide: ;assembly entry point ;save all registers we use so we can restore later move...
  • Page 150 ; Data Structures: None. ; Registers changed: a ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/03/08 Raymond Jimenez first revision global Fget_blocks Fget_blocks: ;C entry point ;standard C prologue move #0,n6 ;k is the amount of local space...
  • Page 151 ide.asm 2011/03/30 ; go to IDE_CYL_LOW #IDE_REG_LENGTH,a,a move a0,x:IDE_CYL_LOW_REG ;and then [23:16] go to IDE_CYL_HIGH #IDE_REG_LENGTH,a,a move a0,x:IDE_CYL_HIGH_REG ;and then we need to put [27:24] in the last 4 bits of ; IDE_DEV_HEAD_REG #IDE_REG_LENGTH,a,a move a0,a1 #>$ff,a #>IDE_SELECT_0_LBA,a move a1,x:IDE_DEV_HEAD_REG ;now execute the command move #>IDE_READ_SEC,r0...
  • Page 152 ide.asm 2011/03/30 #>(1<<IDE_STAT_DRQ),b ;check the DRQ bit get_all_blocks_end ;if equal, get out of here, no more ; blocks to read ;spacing nop get_all_blocks get_all_blocks_end: ;restore registers POP_ACC move ssl,r1 move ssh,r0 ;standard C epilogue move #0+1,n6 move (r6)-n6 ;deallocate local stack space, set ccr flags move x:(r6),ssh ;get return address...

  • Page 153: Sound (Dac & Mp3 Decoder)

    8.7. SOUND (DAC & MP3 DECODER) Sound (DAC & MP3 Decoder) sound.inc contains most of the register definitions and command definitions for both the MP3 decoder (VS1053b) and the DAC (WM8741). sound.asm contains the DMA handling code, the interrupt handling code, and the interface code for the MP3 player.
  • Page 154 sound.inc 2011/04/01 ; the following are helpful constants when dealing with ESSI0, the ; VLSI VS1053b MP3 decoder chip. data and control are both run over ; ESSI0. ; START DECODER SECTION ;the ESSI ports expect left aligned data, so we shift over this number of bits: ESSI_BYTE_SHIFT ;we deal with 16-bit words in SCI mode ESSI_SCI_SHIFT...
  • Page 155 sound.inc 2011/04/01 (STD) enabled (will do later) ; ---- ---- 0--- ---- ---- ---- TX1 (SC0) disabled ; ---- ---- -0-- ---- ---- ---- TX2 (SC1) enabled (will do later) ; ---- ---- --0- ---- ---- ---- normal mode ; ---- ---- ---1 ---- ---- ---- synchronous mode ;...
  • Page 156 sound.inc 2011/04/01 ; ---- --0- ---- ---- ---- ---- RX disabled ; ---- ---0 ---- ---- ---- ---- TX0 (STD) enabled (will do later) ; ---- ---- 0--- ---- ---- ---- TX1 (SC0) disabled ; ---- ---- -0-- ---- ---- ---- TX2 (SC1) disabled ;...
  • Page 157 sound.inc 2011/04/01 enabled ; ---- ---- ---- ---- ---- --0- SC1 enabled ; ---- ---- ---- ---- ---- ---0 SC0 disabled ;see errata for mask 4H80G, we find that GPIO pins need to be programmed to output ; anyway. this is probably why our shit's not working OTL. ESSI0_PRRC $00003f ;...
  • Page 158 sound.inc 2011/04/01 ; ---0 0--- ---- ---- no turbo mode, running at max ; ---- -000 0000 0000 12.288 MHz crystal (default) SCI_VOL_VALUE ($0000<<ESSI_SCI_SHIFT) ;max volume, DAC does vol control SCI_MODE_VALUE ($0800<<ESSI_SCI_SHIFT) ;allow SDI tests SCI_MODE_CANCEL_VALUE ($0808<<ESSI_SCI_SHIFT) ;cancel current playback SCI_AIADDR_VALUE ($4022<<ESSI_SCI_SHIFT) ;sine sweep test...
  • Page 159 sound.inc 2011/04/01 ;constants for our DMA/transfer logic NEEDS_KICKSTART NO_KICKSTART DREQ_CTL_PRIO %110 ;set to edge-trigger, priority 1, we can transmit up to ; 32 bytes safely due to safety zone, even after DREQ is ; lowered NO_BUFFER_LEN ;the following are helpful constants when dealing with our DAC, the Wolfson ;...
  • Page 160 sound.inc 2011/04/01 ; ---- ---- --1- ---- ---- ---- network (on-demand) mode ; ---- ---- ---1 ---- ---- ---- synchronous mode ; ---- ---- ---- 1--- ---- ---- clock out data on falling edge ; ---- ---- ---- -1-- ---- ---- negative edge triggers word (positive is end of word) ;...
  • Page 161 sound.inc 2011/04/01 DAC_ADDR_SHIFT ;we shift 9 bits over as our addresses comprise ; the first 7 bits of our data word DAC_DATA_SHIFT ;the data goes in the last 8 bits of the 16 bit word ;here are a bunch of appropriately shifted and masked addresses to use with our system DAC_LLSB_ADDR ($0<<DAC_ADDR_SHIFT)
  • Page 162 sound.asm 2011/04/02 noidw so,xr page 132,66,3,3 ; sound.asm ; This file offers interfacing code to the sound subsystem: the MP3 decoder and ; the DAC. section sound INCLUDE 'DSP_EQU.inc' INCLUDE 'sound.inc' INCLUDE 'macros.inc' INCLUDE 'general.inc' ;VOLATILE declarations go here ; sound_atten is our volume attenuation in 10 bits, in -0.125dB steps. sound_atten: ;here are all our pointers/etc for the audio update system curbuf:...
  • Page 163 ; Data Structures: None. ; Registers changed: None. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global Fsetup_mp3 Fsetup_mp3: ;C entry point ;standard C prologue move #0,n6 ;k is the amount of local space...
  • Page 164 sound.asm 2011/04/02 move #>ESSI0_PCRC_SCI,r0 move r0,x:M_PCRC move #>ESSI0_PRRC,r0 move r0,x:M_PRRC move #>ESSI0_PDRC,r0 move r0,x:M_PDRC ;we load first data move #>$ffff00,r0 move r0,x:M_TX00 ; (TX02 control XCS) move #XCS_HIGH,r0 move r0,x:M_TX02 ;now enable transmitters bset #M_SSTE0,x:M_CRB0 bset #M_SSTE2,x:M_CRB0 bset #M_SSRE,x:M_CRB0 ;we wait for mp3 to become ready again move #>SET_CLOCK_WAIT,r0 sleep...
  • Page 165 sound.asm 2011/04/02 move r0,x:M_TX02 ;now enable transmitters bset #M_SSTE0,x:M_CRB0 bset #M_SSTE2,x:M_CRB0 bset #M_SSRE,x:M_CRB0 ; 2) enable I2S output ;to enable I2S, we turn GPIO to output and turn on I2S ;set GPIO flags: move #>(SCI_WRITE_CMD|SCI_WRAMADDR),r0 ;we need to set where ;...
  • Page 166 sound.asm 2011/04/02 move #SCI_AIADDR_VALUE,r1 write_sync_mp3_sci move #>SET_AIADDR_WAIT,r0 sleep ; 5) we now switch to data mode mp3_to_data_mode ;and we setup the DMA control registers as we'll be using ; them in the future move #>DCR2,r0 move r0,x:M_DCR2 move #>M_TX00,r0 move r0,x:M_DDR2 ;we also install the interrupt handlers we'll be using move...
  • Page 167 sound.asm 2011/04/02 jclr #M_TDE,x:M_SSISR0,* ;wait until transmitted move #>$0,r1 move r1,x:M_TX00 ;shill write to TX00 ;wait for delay jclr #M_TDE,x:M_SSISR0,* ;wait until transmitted ;end of body code, now restore all registers POP_ACC move ssl,r1 move ssh,r0 ;standard C epilogue move #0+1,n6 move (r6)-n6...
  • Page 168 ; Known Bugs: None. ; Special Notes: This function turns off ESSI0's interrupts. It does not ; enable the DREQ/IRQ1 interrupt. ; Revision History: 2011/03/28 Raymond Jimenez first revision global mp3_to_data_mode mp3_to_data_mode: ;assembly entry point ;save all registers we use so we can restore later...
  • Page 169 ; Known Bugs: None. ; Special Notes: This function turns off ESSI0's interrupts. It does not ; enable/disable the DREQ/IRQ1 interrupt. ; Revision History: 2011/03/28 Raymond Jimenez first revision global mp3_to_control_mode mp3_to_control_mode : ;assembly entry point ;save all registers we use so we can restore later...
  • Page 170 sound.asm 2011/04/02 jclr #M_TDE,x:M_SSISR0,* ;wait until transmitted ;need to temporarily disable ESSI pins otherwise they retain functionality move #>0,r0 move r0,x:M_PCRC ;we then reconfigure ESSI0 to give us automatic frame syncs ; (auto XDCS) move #ESSI0_CRA_SCI,r0 move r0,x:M_CRA0 move #ESSI0_CRB_SCI,r0 move r0,x:M_CRB0 ;first, we set the GPIO pins as necessary...
  • Page 171 ; prevent us from having to transfer into a, and then rotate. it's much faster ; this way, and since we mostly transmit constants to SCI, we can just ; pre-compose commands via macros. ; Revision History: 2011/02/16 Raymond Jimenez first revision global write_sync_mp3_sci write_sync_mp3_sci: ;assembly entry point...
  • Page 172 sound.asm 2011/04/02 ;we first want to make sure XCS is turned on for these words, ; so set up TX10/TX20 appropriately move #XCS_HIGH,r2 move r2,x:M_TX02 ;we first make sure the transmitter is empty ;we have a two-cycle pipeline delay after we write these registers ;...
  • Page 173 ; prevent us from having to transfer into a, and then rotate. it's much faster ; this way, and since we mostly transmit constants to SCI, we can just ; pre-compose commands via macros. ; Revision History: 2011/03/27 Raymond Jimenez first revision global read_sync_mp3_sci read_sync_mp3_sci: ;assembly entry point...
  • Page 174 sound.asm 2011/04/02 transmits) START_CRITICAL ;we first make sure the transmitter is empty jclr #M_TDE,x:M_SSISR0,* ;keep on jumping here until TDE is set move r0,x:M_TX00 ;transmit first 16 bits: command, address ;we first want to make sure XCS is turned on for these words, ;...
  • Page 175 sound.asm 2011/04/02 jclr #M_TDE,x:M_SSISR0,* ;wait until transmitted move r1,x:M_TX00 ;shill write to TX00 move #XCS_HIGH,r2 move r2,x:M_TX02 END_CRITICAL ;end of body code, now restore all registers move ssh,r2 ;pipeline cache issue (see errata) ;return from subroutine ;end read_sync_mp3_sci ; Faudio_play ;...
  • Page 176 2011/04/02 ; Revision History: 2011/02/16 Raymond Jimenez first revision global Faudio_play Faudio_play: ;C entry point ;standard C prologue move #0,n6 ;k is the amount of local space move ssh,x:(r6)+ ;save the return address move (r6)+n6 ;allocate local stack space of size k ;save all registers we use so we can restore later...
  • Page 177 sound.asm 2011/04/02 move b1,x:M_IPRC ;and then finally, we enable the DMA and get going bset #M_DE,x:M_DCR2 ;set enable, since DMA is DE-enabled ;at this point we should be going at full tilt: ; if the buffer runs out, the DMA done interrupt will handle it ;...
  • Page 178 ; Data Structures: None. ; Registers changed: None. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global Faudio_halt Faudio_halt: ;C entry point ;standard C prologue move #0,n6 ;k is the amount of local space...
  • Page 179 sound.asm 2011/04/02 #2052,write_endfillbyte move a1,x:M_TX00 ;write endfillbyte ;account for pipeline delay jclr #M_TDE,x:M_SSISR0,* ;keep on jumping here until transmitted ;spacing nops write_endfillbyte: mp3_to_control_mode ;we now need to shift to control mode to ; set SM_CANCEL move #>(SCI_WRITE_CMD|SCI_MODE),r0 move #>SCI_MODE_CANCEL_VALUE write_sync_mp3_sci move #>SET_MODE_WAIT,r0 sleep...
  • Page 180 None known. 1046 1047 ; Known Bugs: None. 1048 1049 ; Special Notes: 1050 1051 ; Revision History: 2011/02/16 Raymond Jimenez first revision 1052 1053 global end_mp3_dma_handler 1054 end_mp3_dma_handler : ;assembly entry point 1055 1056 ;save all registers we use so we can restore later...
  • Page 181 sound.asm 2011/04/02 1064 1065 ;since we're called if DE has also been hand-deasserted 1066 ; (as in DREQ stopping our data transfer), we 1067 ; check to see if we were at the end of the transfer by comparing 1068 ;...
  • Page 182 sound.asm 2011/04/02 1121 end_mp3_dma_no_buf: ;we're guaranteed to have no buffers to move in 1122 ;since we have no next buffer, we mark the current buffer 1123 ; used as well. 1124 move x:curbuf,r0 1125 1126 move r0,x:usedbuf 1127 1128 ;we invalidate the current buffer by setting it to NO_BUFFER_LEN 1129 move a1,x:curbuflen...
  • Page 183 None known. 1185 1186 ; Known Bugs: None. 1187 1188 ; Special Notes: 1189 1190 ; Revision History: 2011/02/16 Raymond Jimenez first revision 1191 1192 global dreq_asserted_handler 1193 dreq_asserted_handler : ;assembly entry point 1194 1195 ;save all registers we use so we can restore later...
  • Page 184 None known. 1251 1252 ; Known Bugs: None. 1253 1254 ; Special Notes: 1255 1256 ; Revision History: 2011/02/16 Raymond Jimenez first revision 1257 1258 global dreq_deasserted_handler 1259 dreq_deasserted_handler : ;assembly entry point 1260 1261 ;save all registers we use so we can restore later...
  • Page 185 ; Data Structures: None. 1334 1335 ; Registers changed: None. 1336 1337 ; Limitations: None known. 1338 1339 ; Known Bugs: None. 1340 1341 ; Special Notes: 1342 1343 ; Revision History: 2011/02/16 Raymond Jimenez first revision 1344 1345 global Fupdate...
  • Page 186 sound.asm 2011/04/02 1346 Fupdate: ;C entry point 1347 1348 ;standard C prologue 1349 move #0,n6 ;k is the amount of local space 1350 move ssh,x:(r6)+ ;save the return address 1351 move (r6)+n6 ;allocate local stack space of size k 1352 1353 1354 ;save all registers we use so we can restore later...
  • Page 187 sound.asm 2011/04/02 1401 update_end 1402 1403 update_empty_curbuf_new : ;scenario #3: we have all empty buffers, and new data 1404 move x0,x:curbuf ;place in the new buffer 1405 move x1,x:curbuflen 1406 process_mp3_buffer ;and process the buffer when we place it in 1407 ;(r0-r1 set up top) 1408...
  • Page 188 ; Registers changed: None. 1503 1504 ; Limitations: None known. 1505 1506 ; Known Bugs: None. 1507 1508 ; Special Notes: 1509 1510 ; Revision History: 2011/02/16 Raymond Jimenez first revision 1511 1512 global process_mp3_buffer 1513 process_mp3_buffer: ;assembly entry point...
  • Page 189 sound.asm 2011/04/02 1514 1515 ;save all registers we use so we can restore later 1516 PUSH_ACC 1517 PUSH_ACC 1518 move r0,ssh 1519 move x0,ssl 1520 1521 1522 r1,process_buffer_loop 1523 1524 1525 move x:(r0),a ;we copy into a/b so we can do bitshifts. 1526 1527 move...
  • Page 190 ; Limitations: None known. 1591 1592 ; Known Bugs: None. 1593 1594 ; Special Notes: None. 1595 1596 ; Revision History: 2011/3/25 Raymond Jimenez first revision 1597 1598 global Fsetup_dac 1599 Fsetup_dac: ;C entry point 1600 1601 ;standard C prologue 1602...
  • Page 191 sound.asm 2011/04/02 1627 ;enable transmitter 1628 bset #M_SSTE0,x:M_CRB1 1629 1630 1631 ;now that the ESSI port is setup, we can go ahead and write our initial 1632 ; reg values 1633 move #>(DAC_RESET_ADDR),r0 1634 write_sync_dac ;reset the chip to a known state 1635 1636 1637...
  • Page 192 We require the strange bitfield structure of r0 to make 1713 ; things faster; since we mostly deal with pre-composed constants, we can use 1714 ; macro shifts to pre-calculate everything. 1715 1716 ; Revision History: 2011/03/25 Raymond Jimenez first revision 1717 1718 global write_sync_dac 1719 write_sync_dac: ;assembly entry point...
  • Page 193 ; Limitations: None known. 1769 1770 ; Known Bugs: None. 1771 1772 ; Special Notes: 1773 1774 ; Revision History: 2011/03/27 Raymond Jimenez first revision 1775 1776 global Fvol_up 1777 Fvol_up: ;C entry point 1778 1779 ;standard C prologue 1780...
  • Page 194 sound.asm 2011/04/02 1793 x0,a ; subtract (smaller atten == louder) 1794 1795 #>MIN_ATTEN,a ;see if it's too loud, nowhere to go 1796 vol_up_done ;too loud, so go don't make any changes 1797 1798 1799 move a1,x:sound_atten ;store the change 1800 1801 #>ATTEN_MASK,a ;we now have our desired attenuation...
  • Page 195 ; Limitations: None known. 1878 1879 ; Known Bugs: None. 1880 1881 ; Special Notes: 1882 1883 ; Revision History: 2011/03/27 Raymond Jimenez first revision 1884 1885 global Fvol_down 1886 Fvol_down: ;C entry point 1887 1888 ;standard C prologue 1889...
  • Page 196 sound.asm 2011/04/02 1904 #>MAX_ATTEN,a ; see if it's too soft. 1905 vol_down_done ;too soft, so go don't make any changes 1906 1907 1908 move a1,x:sound_atten ;store the change 1909 #>ATTEN_MASK,a ;we now have our desired attenuation 1910 ; in a1, so we use masks to get it to 1911 ;...
  • Page 197 None known. 1987 1988 ; Known Bugs: None. 1989 1990 ; Special Notes: 1991 1992 ; Revision History: 2011/02/16 Raymond Jimenez first revision 1993 1994 global get_atten 1995 get_atten: ;assembly entry point 1996 1997 ;save all registers we use so we can restore later...

  • Page 198: Timing

    CHAPTER 8. ANNOTATED CODE Timing timing.inc contains definitions for timing, such as how many loop iterations cor- respond to a minimum of 1 millisecond, etc. timing.asm provides several timing functions, such as Felapsed time and others.
  • Page 199 timing.inc 2011/03/24 TICKS_PER_MS SLEEP_CYCLES...
  • Page 200 None. ; Outputs: None. ; Error Handling: None. ; Algorithm: None. ; Data Structures: None. ; Registers changed: None. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global Felapsed_time...
  • Page 201 timing.asm 2011/03/24 Felapsed_time: ;C entry point ;standard C prologue move #0,n6 ;k is the amount of local space move ssh,x:(r6)+ ;save the return address move (r6)+n6 ;allocate local stack space of size k ;save all registers we use so we can restore later move r0,ssh move...
  • Page 202 ; Registers changed: None. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global time_elapsed_update time_elapsed_update : ;assembly entry point ;save all registers we use so we can restore later...
  • Page 203 ; Registers changed: None. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global sleep sleep: ;assembly entry point ;save all registers we use so we can restore later move...

  • Page 204: Interrupts

    CHAPTER 8. ANNOTATED CODE Interrupts intrrpts.asm contains the interrupt installation/initalivation code.
  • Page 205 intrrpts.asm 2011/04/02 ; intrrupts.asm ; This file offers interrupt setup and handler routines. ; void setup_timer0(void) -- sets up timer 0, currently used for processing display commands at 500ns intervals. ; void install_timer0_handler(void) -- installs timer0 handler (currently calls display function only) ;...
  • Page 206 2011/04/02 ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global Fstart_intr_setup Fstart_intr_setup: ;C entry point ;standard C prologue move #0,n6 ;k is the amount of local space move ssh,x:(r6)+ ;save the return address...
  • Page 207 intrrpts.asm 2011/04/02 movep a1,x:M_IPRP ;write back to the register ;setup the prescaler timer to have 4 cycles. ;@ 40MHz = 80/2 MHz, this gives us 1us resolution movep #40,x:M_TPLR ;we want to have 200 cycles -> 200us command cycle time for the display movep #200,x:M_TCPR0 ;initialize the timer start count to zero, too...
  • Page 208 intrrpts.asm 2011/04/02 ; 1ms per tick. ; additionally, we base our MP3 timing off of this routine, ; down to millisecond accuracy, so don't change! movep #1000,x:M_TCPR1 ;initialize the timer start count to zero, too movep #0,x:M_TLR1 ;set timer 1 to be enabled and in event counting mode, continuously ;...
  • Page 209 intrrpts.asm 2011/04/02 ;(SR interrupt bits are already set by crt0) ; this should have been setup already by timer0_setup. ; 15us per tick. ; dram refresh, so it's important that this works properly. movep #400,x:M_TCPR2 ;initialize the timer start count to zero, too movep #0,x:M_TLR2 ;set timer 2 to be enabled and in GPIO mode, continuously...
  • Page 210 intrrpts.asm 2011/04/02 ; save registers we use move r0,ssh move r1,ssl move r2,ssh move #$200000,r0 ;we just grab the first 32 words of dram into ; (it's important that it's dram due to DMA contention) ;we disable DMA during refresh. move x:M_DCR2,r2 bclr...
  • Page 211 ; Data Structures: None. ; Registers changed: None. ; Limitations: None known. ; Known Bugs: None. ; Special Notes: ; Revision History: 2011/02/16 Raymond Jimenez first revision global Fsetup_keypad_irq Fsetup_keypad_irq: ;assembly entry point ;standard C prologue move #0,n6 ;k is the amount of local space...
  • Page 212 intrrpts.asm 2011/04/02 #~M_IAL,a ;clear the mode mask of IRQA #(1<<M_IAL2)|(1<<M_IAL0),a ;we set it to be edge-triggered (M_IAL2 = 1) ; and priority 1 (M_IAL[0-1] = 1 move a1,x:M_IPRC ;and replace back ;end of body code, now restore all registers POP_ACC move ssh,x0 ;restore x0...
  • Page 213 2011/04/02 ; Revision History: 2011/02/16 Raymond Jimenez first revision global Fend_intr_setup Fend_intr_setup: ;C entry point ;standard C prologue move #0,n6 ;k is the amount of local space move ssh,x:(r6)+ ;save the return address move (r6)+n6 ;allocate local stack space of size k ;save all registers we use so we can restore later (we don't use any)

  • Page 214: User Interface

    CHAPTER 8. ANNOTATED CODE 8.10 User Interface Several portions of the provided code were modified in order to interface with the assembly code. They are provided as follows: keyproc.h was updated to include volume-changing functions. interfac.h was modified to reflect our current system, and was also updated to take into account the two volume up/down keys.
  • Page 215 Initial revision (from the 3/6/99 version of keyproc.h for the Digital Audio Recorder Project). 6/5/08 Glen George Added declarations for dec_FFRev_rate() and inc_FFRev_rate() functions. 3/3/11 Raymond Jimenez Added declarations for do_VolUp() and do_VolDown(). #ifndef I__KEYPROC_H__ #define I__KEYPROC_H__ /* library include files */ /* none */...
  • Page 216 keyproc.h 2011/06/14 enum status do_TrackDown(enum status); /* go to the previous track */ enum status do_VolUp(enum status); /* increase volume */ enum status do_VolDown(enum status); /* decrease volume */ enum status start_Play(enum status); /* begin playing the current track */ enum status begin_Play(enum...
  • Page 217 interfac.h 2011/04/02 /****************************************************************************/ INTERFAC.H Interface Definitions Include File MP3 Jukebox Project EE/CS 52 /****************************************************************************/ This file contains the constants for interfacing between the C code and the assembly code/hardware. This is a sample interface file to allow test compilation and linking of the code. Revision History: 6/3/00 Glen George...
  • Page 218 interfac.h 2011/04/02 #define SUBDIR_CHAR '>' #define STATUS_PLAY #define STATUS_FASTFWD #define STATUS_REVERSE #define STATUS_IDLE #define STATUS_ILLEGAL #define IDE_BLOCK_SIZE /* 256 words/block */ #endif...
  • Page 219 mainloop.c 2011/04/02 /****************************************************************************/ MAINLOOP Main Program Loop MP3 Jukebox Project EE/CS 52 /****************************************************************************/ This file contains the main processing loop (background) for the MP3 Jukebox Project. The only global function included is: main - background processing loop The local functions included are: key_lookup - get a key and look up its keycode The locally global variable definitions included are: none...
  • Page 220 mainloop.c 2011/04/02 main Description: This procedure is the main program loop for the MP3 Jukebox. It loops getting keys from the keypad, processing those keys as is appropriate. It also handles updating the display and setting up the buffers for MP3 playback.
  • Page 221 mainloop.c 2011/04/02 idle play fast forward reverse no_update, update_Play, update_FastFwd, update_Reverse /* key processing functions (one for each system status type and key) */ static enum status const process_key[NUM_KEYCODES][NUM_STATUS])(enum status) Current System Status /* idle play fast forward reverse do_TrackUp, no_action, no_action, no_action...
  • Page 222 mainloop.c 2011/04/02 while(1) test_dram(); /* first initialize everything */ /* initalize FAT directory functions */ root_dir_start = init_FAT_system(); /* get the first directory entry (file/song) */ (root_dir_start != /* have a valid starting sector - get the first directory entry */ get_first_dir_entry (root_dir_start);...
  • Page 223 mainloop.c 2011/04/02 /* always remember the current status for next loop iteration */ prev_status = cur_status; /* done with main (never should get here), return 0 */ return key_lookup Description: This function gets a key from the keypad and translates the raw keycode to an enumerated keycode for the main loop.
  • Page 224 mainloop.c 2011/04/02 static const int keys[] /* array of key values */ /* order must match keycodes array exactly */ KEY_TRACKUP, /* <Track Up> KEY_TRACKDOWN, /* <Track Down> KEY_PLAY, /* <Play> KEY_RPTPLAY, /* <Repeat Play> KEY_FASTFWD, /* <Fast Forward> */ KEY_REVERSE, /* <Reverse>...
  • Page 225 keyupdat.c 2011/03/31 /****************************************************************************/ KEYUPDAT Miscellaneous Key Processing and Update Functions MP3 Jukebox Project EE/CS /****************************************************************************/ This file contains the key processing and update functions for operations other than Play, Record, Fast Forward, and Reverse for the MP3 Jukebox Project. These functions are called by the main loop of the MP3 Jukebox. The functions included are: do_TrackUp - go to the next track (key processing function)
  • Page 226 keyupdat.c 2011/03/31 no_action Description: This function handles a key when there is nothing to be done. It just returns. Arguments: cur_status (enum status) - the current system status. Return Value: (enum status) - the new status (same as current status). Input: None.
  • Page 227 keyupdat.c 2011/03/31 Algorithms: None. Data Structures: None. Shared Variables: None. Author: Glen George Last Modified: June 5, 2003 enum status do_TrackUp(enum status cur_status) /* variables */ /* none */ /* move to the previous directory entry, watching for errors */ (!get_previous_dir_entry /* successfully got the new entry, load its data */ setup_cur_track_info ();...
  • Page 228 keyupdat.c 2011/03/31 Data Structures: None. Shared Variables: None. Author: Glen George Last Modified: June 5, 2003 enum status do_TrackDown(enum status cur_status) /* variables */ /* none */ /* move to the next directory entry, watching for errors */ (!get_next_dir_entry()) /* successfully got the new entry, load its data */ setup_cur_track_info ();...
  • Page 229 keyupdat.c 2011/03/31 Shared Variables: None. Author: Glen George Last Modified: June 3, 2000 enum status stop_idle(enum status cur_status) /* variables */ /* none */ /* reset to the start of the current track */ init_track(); /* display the new time for the current track */ display_time(get_track_time());...
  • Page 230 None. Output: None. Error Handling: None. Algorithms: None. Data Structures: None. Shared Variables: None. Author: Raymond Jimenez Last Modified: Mar. 27, 2011 enum status do_VolUp(enum status cur_status) /* variables */ /* none */ vol_up(); /* vol_up doesn't take any arguments; it does the bounds checking */ display_volume();...
  • Page 231 None. Output: None. Error Handling: None. Algorithms: None. Data Structures: None. Shared Variables: None. Author: Raymond Jimenez Last Modified: Mar. 27, 2011 enum status do_VolDown(enum status cur_status) /* variables */ /* none */ vol_down(); /* vol_down doesn't take any arguments; it does the bounds checking display_volume();...
  • Page 232 test_dram.c 2011/06/14 #include <stddef.h> #include <stdio.h> #include "interfac.h" #include "mp3defs.h" #define BLOCK_SZ 0x2000 #define DRAM_SZ 0x4000 #define DRAM_START 0x200000 void test_dram() unsigned int lfsr = 1; unsigned int period = 0; volatile unsigned int *DRAMptr; char buffer[BLOCK_SZ]; char strbuf[80]; for(DRAMptr = (unsigned int *)(DRAM_START);\ DRAMptr <...
  • Page 233 test_dram.c 2011/06/14...

  • Page 234: Miscellaneous

    CHAPTER 8. ANNOTATED CODE 8.11 Miscellaneous DSP EQU.inc contains several system defines, such as critical memory addresses and register values. general.inc contains important definitons applicable to all code. macros.inc contains several important macros, such as a x86 PUSH/POP equiva- lent and critical code wrappers. Makefile allows us to build and package.
  • Page 235 DSP_EQU.inc 2011/01/28 ;******************************************************************************* ; EQUATES for 56302/3 I/O registers and ports ; Last update: June 11 1995 ;******************************************************************************* page 132,55,0,0,0 ioequ ident ;------------------------------------------------------------------------ EQUATES for I/O Port Programming ;------------------------------------------------------------------------ ; Register Addresses M_HDR $FFFFC9 ; Port B (host) GPIO data Register M_HDDR $FFFFC8 ;...
  • Page 236 DSP_EQU.inc 2011/01/28 M_HRDF ; Host Receive Data Full M_HTDE ; Host Receive Data Emptiy M_HCP ; Host Command Pending M_HF0 ; Host Flag 0 M_HF1 ; Host Flag 1 ; HPCR bits definition M_HGEN ; Host Port GPIO Enable M_HA8EN ;...
  • Page 237 DSP_EQU.inc 2011/01/28 M_TMIE ; Timer Interrupt Enable M_TIR ; Timer Interrupt Rate M_SCKP ; SCI Clock Polarity M_REIE ; SCI Error Interrupt Enable (REIE) ; SCI Status Register Bit Flags M_TRNE ; Transmitter Empty M_TDRE ; Transmit Data Register Empty M_RDRF ;...
  • Page 238 DSP_EQU.inc 2011/01/28 ; ESSI Control Register A Bit Flags M_PM ; Prescale Modulus Select Mask (PM0-PM7) M_PSR ; Prescaler Range M_DC $1F000 ; Frame Rate Divider Control Mask (DC0-DC7) M_ALC ; Alignment Control (ALC) M_WL $380000 ; Word Length Control Mask (WL0-WL7) M_SSC1 ;...
  • Page 239 DSP_EQU.inc 2011/01/28 ; ESSI Receive Slot Mask Register B M_SSRSB $FFFF ; ESSI Receive Slot Bits Mask B (RS16-RS31) ;------------------------------------------------------------------------ EQUATES for Exception Processing ;------------------------------------------------------------------------ ; Register Addresses M_IPRC $FFFFFF ; Interrupt Priority Register Core M_IPRP $FFFFFE ; Interrupt Priority Register Peripheral ;...
  • Page 240 DSP_EQU.inc 2011/01/28 M_S0L1 ; ESSI0 Interrupt Priority Level (high) M_S1L ; ESSI1 Interrupt Priority Level Mask M_S1L0 ; ESSI1 Interrupt Priority Level (low) M_S1L1 ; ESSI1 Interrupt Priority Level (high) M_SCL ; SCI Interrupt Priority Level Mask M_SCL0 ; SCI Interrupt Priority Level (low) M_SCL1 ;...
  • Page 241 DSP_EQU.inc 2011/01/28 ; Timer Control Bits M_TC0 ; Timer Control 0 M_TC1 ; Timer Control 1 M_TC2 ; Timer Control 2 M_TC3 ; Timer Control 3 ;------------------------------------------------------------------------ EQUATES for Direct Memory Access (DMA) ;------------------------------------------------------------------------ ; Register Addresses Of DMA M_DSTR $FFFFF4 ;...
  • Page 242 DSP_EQU.inc 2011/01/28 M_DSS ; DMA Source Space Mask (DSS0-Dss1) M_DSS0 ; DMA Source Memory space 0 M_DSS1 ; DMA Source Memory space 1 M_DDS ; DMA Destination Space Mask (DDS-DDS1) M_DDS0 ; DMA Destination Memory Space 0 M_DDS1 ; DMA Destination Memory Space 1 M_DAM $3f0 ;...
  • Page 243 DSP_EQU.inc 2011/01/28 M_PCOD ; PLL Clock Output Disable Bit M_PD $F00000 ; PreDivider Factor Bits Mask (PD0-PD3) ;------------------------------------------------------------------------ EQUATES for BIU ;------------------------------------------------------------------------ ; Register Addresses Of BIU M_BCR $FFFFFB ; Bus Control Register M_DCR $FFFFFA ; DRAM Control Register M_AAR0 $FFFFF9 ;...
  • Page 244 DSP_EQU.inc 2011/01/28 ; Zero ; Negative ; Unnormalized ; Extension ; Limit ; Scaling Bit M_I0 ; Interupt Mask Bit 0 M_I1 ; Interupt Mask Bit 1 M_S0 ; Scaling Mode Bit 0 M_S1 ; Scaling Mode Bit 1 M_SC ;...
  • Page 245 DSP_EQU.inc 2011/01/28 else I_VEC endif ;------------------------------------------------------------------------ ; Non-Maskable interrupts ;------------------------------------------------------------------------ I_RESET I_VEC+$00 ; Hardware RESET I_STACK I_VEC+$02 ; Stack Error I_ILL I_VEC+$04 ; Illegal Instruction I_DBG I_VEC+$06 ; Debug Request I_TRAP I_VEC+$08 ; Trap I_NMI EQU I_VEC+$0A ; Non Maskable Interrupt ;------------------------------------------------------------------------ ;...
  • Page 246 DSP_EQU.inc 2011/01/28 ;------------------------------------------------------------------------ ; SCI Interrupts ;------------------------------------------------------------------------ I_SCIRD I_VEC+$50 ; SCI Receive Data I_SCIRDE I_VEC+$52 ; SCI Receive Data With Exception Status I_SCITD I_VEC+$54 ; SCI Transmit Data I_SCIIL I_VEC+$56 ; SCI Idle Line I_SCITM I_VEC+$58 ; SCI Timer ;------------------------------------------------------------------------ ;...
  • Page 247 general.inc 2011/03/29 FALSE TRUE...
  • Page 248 macros.inc 2011/03/29 ; we place some convenient macros here to make our life easier: PUSH_ACC MACRO ;we're saving an accumulator to the stack. move ACC\0,ssh ;push acc0/acc1 onto stack in one location move ACC\1,ssl ;pushing acc0 already preincremented move ACC\2,ssh ;...
  • Page 249 Makefile.mak 2011/06/14 ############################################################################# # Makefile # EE/CS 52: DSP56K MP3/Ogg Jukebox Project # Revision History # 2/16/2010 Glen George Initial Revision # 3/10/2011 Raymond Jimenez now working for our build ############################################################################## ### VARIABLES ################################################################ # C Compiler Definition CC=g563c ASM=asm56300...
  • Page 250 Makefile.mak 2011/06/14 ### RULES #################################################################### # Specify Virtual Path for Object Files vpath %.cln $(OBJDIR) # Rule for Building Objects from C Sources %.cln: $(CC) $(CFLAGS) -c $(patsubst %.cln,%.c,$(<)) -o $(OBJDIR)\$@ ### COMMAND LINE TARGETS ##################################################### # Target for Building All Code #juke: $(SYSOBJS) $(JUKEOBJS) $(LINK) -f$(LINKCMD) $(HEXMAKE) -b jukebox.cld...
  • Page 251 Makefile.mak 2011/06/14 test_dram.cln: $(SYSDIR)/test_dram.c # Targets for Low-Level Code # user must supply these targets and dependencies # example defintions: keypad.cln: $(SYSDIR)/keypad.asm $(SYSDIR)/general.inc $(SYSDIR)/keypad.inc $(ASM) $(ASMFLAGS) -b$(OBJDIR)/keypad.cln $(SYSDIR)/keypad.asm crt0.cln : $(SYSDIR)/crt0.asm $(CC) -c $(patsubst %.cln,%.asm,$(<)) -o $(OBJDIR)\$@ intrrpts.cln : $(SYSDIR)/intrrpts.asm $(SYSDIR)/display.inc $(CC) $(CFLAGS) -c $(patsubst %.cln,%.asm,$(<))
  • Page 252 CHAPTER 8. ANNOTATED CODE...
  • Page 253 Chapter 9 Release Notes/Errata Known Bugs Due to bad soldering, the DRAM may not be always functional. To resolve this issue, one can resort to percussive maintenance or a “hot- plug” of the DRAM. In order to hotplug the DRAM, start the system as described in the Quick-Start guide.
  • Page 254 CHAPTER 9. RELEASE NOTES/ERRATA No fix is known at this time. Adding songs during Daylight Saving Time may not operate correctly. You may see songs with extremely long playtimes, such as 500 minutes. This is due to a bug in the MS-DOS song-adding program, which does not operate correctly given Daylight Saving Time.

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