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tracking will be directly proportional to the unbalance in the
quiescent output voltage An optional potentiometer may be
placed at pin 1 as shown in Figure 19 to null output offset
The unbalanced current output for the circuit of Figure 18 is
limited by the power dissipation of the package
In the case of sustained unbalanced excess loads the de-
vice will go into thermal limiting as the temperature sensing
circuit begins to function For instantaneous high current
loads or short circuits the device limits the output current to
approximately 1 3 amperes until thermal shut-down takes
over or until the fault is removed
HIGH INPUT IMPEDANCE CIRCUIT
The junction FET isolation circuit shown in Figure 20 raises
the input impedance to 22 MX for low frequency input sig-
nals The gate to drain capacitance (2 pF maximum for the
KE4221 shown) of the FET limits the input impedance as
frequency increases
FIGURE 20
At 20 kHz the reactance of this capacitor is approximately
j4 MX giving a net input impedance magnitude of 3 9 MX
b
The values chosen for R
R
1
2
circuit gain of at least 45 for the complete range of parame-
ters specified for the KE4221
When using another FET device the relevant design equa-
tions are as follows
R
1
A
e
V
R
a
1
g
g
1
e
m
m0
V
I
e
GS
DS
I
I
1
e
DS
DSS
The maximum value of R
is determined by the product of
2
the gate reverse leakage I
GSS
be 10 to 100 times smaller than V
of the FET source follower is
R
e
o
so that the determining resistance for the interstage RC
time constant is the input resistance of the LM380
TL H 7380– 23
and C
provide an overall
1
(50)
(7)
1
g
m
V
GS
b
(8)
V
p
R
(9)
1
2
V
GS
b
(10)
V
P
and R
This voltage should
2
The output impedance
P
1
(11)
g
m
BOOSTED GAIN USING POSITIVE FEEDBACK
For applications requiring gains higher than the internally
set gain of 50 it is possible to apply positive feedback
around the LM380 for closed loopgains of up to 300 Figure
21 shows a practical example of an LM380 in a gain of 200
circuit
FIGURE 21 Boosted Gain of 200
Using Positive Feedback
The equation describing the closed loop gain is
A
e
VCL
where A
is complex at high frequencies but is nominally
V(
0
)
the 40 to 60 specified on the data sheet for the pass band
of the amplifier If 1
R
a
A
the denominator of equation 12 approaches zero the
V(
0
)
closed loop gain increases toward infinity and the circuit
oscillates This is the reason for limiting the closed loop gain
values to 300 or less Figure 22 shows the loaded and un-
loaded bode plot for the circuit shown in Figure 21
FIGURE 22 Boosted Gain Bode Plot
The 24 pF capacitor C
shown on Figure 21 was added to
2
give an overdamped square wave response under full load
conditions It causes a high frequency roll-off of
f
e
2
The circuit of Figure 21 will have a very long (1000 sec) turn
on time if R
is not present but only a 0 01 second turn on
L
time with an 8X load
7
TL H 7380 – 24
A
b
0
V(
)
(12)
A
0
V(
)
1
b
R
1
1
a
R
2
R
approaches the value of
1
2
TL H 7380 – 25
1
(13)
q
2
R
C
2
2
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