Hitachi 42PMA225EZ Service Manual
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Hitachi 42PMA225EZ Service Manual

42” plasma tv
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Download this manual See also: Instructions for Use Manual
CAUTION:
Before servicing this chassis, it is important that the service technician read the "Safety
Precautions" and "Product Safety Notices" in this service manual.
ATTENTION:
Avant d'effectuer l'entretien du châassis, le technicien doit lire les «Précautions de sécurité»
et les «Notices de sécurité du produit» présentés dans le présent manuel.
VORSICHT:
Vor Öffnen des Gehäuses hat der Service-Ingenieur die „Sicherheitshinweise" und „Hinweise
zur Produktsicherheit" in diesem Wartungshandbuch zu lesen.
SPECIFICATIONS AND PARTS ARE SUBJECT TO CHANGE FOR IMPROVEMENT
SERVICE MANUAL
MANUEL D'ENTRETIEN
WARTUNGSHANDBUCH
Colour Television
September 2004
SM0065
42PMA225EZ
Data
contained
within
this
manual is subject to alteration for
improvement.
Les données fournies dans le présent
manuel d'entretien peuvent faire l'objet
de modifications en vue de perfectionner
le produit.
Die
in
diesem
Wartungshandbuch
enthaltenen Spezifikationen können sich
zwecks Verbesserungen ändern.
Service

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  • Page 1 SM0065 42PMA225EZ SERVICE MANUAL MANUEL D'ENTRETIEN WARTUNGSHANDBUCH CAUTION: Before servicing this chassis, it is important that the service technician read the “Safety Precautions” and “Product Safety Notices” in this service manual. Data contained within this Service manual is subject to alteration for improvement.

  • Page 2: Table Of Contents

    TABLE OF CONTENTS INTRODUCTION............................1 MULTI STANDARD SOUND PROCESSOR ....................1 VIDEO SWITCH TEA6415........................1 AUDIO AMPLIFIER STAGE WITH TDA8928ST ..................1 POWER SUPPLY (SMPS)........................1 MICROCONTROLLER..........................2 SERIAL ACCESS CMOS 4K x 8 (32K bit) EEPROM 24C32A ..............2 CLASS AB STEREO HEADPHONE DRIVER TDA1308................2 IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM................2 9.1.
  • Page 3 9.13. TDA1308............................15 General Description .......................15 9.13.1. 9.13.2. Features...........................15 9.13.3. Pinning.............................16 9.14. PI5V330 ............................16 General Description .......................16 9.14.1. 9.15. AD9883A............................16 General Description .......................16 9.15.1. 9.15.2. Features...........................16 Pin Descriptions ........................17 9.15.3. 9.16. SAA7118E ............................19 General Description .......................19 9.16.1. 9.16.2. Features...........................20 9.16.3. Pinning.............................21 9.17.

  • Page 4: Introduction

    1. INTRODUCTION 42” Plasma TV is a progressive TV control system with built-in de-interlacer and scaler. It uses a 852*480 panel with 16:9 aspect ratio. The TV is capable of operation in PAL, SECAM, NTSC (playback) colour standards and multiple transmission standards as B/G, D/K, I/I’, and L/L´ including German and NICAM stereo.

  • Page 5: Microcontroller

    transistor, it controls each portion of energy transferred to the second side such that the output voltage remains nearly independent of load variations. 6. MICROCONTROLLER The microprocessor is embedded inside PW181 chip which also handles scaling, frame rate conversion and OSD generation. The on-chip 16-bit microprocessor is a Turbo x86-compatible processor core with on-chip peripherals (timers, interrupt controller, 2-wire serial master/slave interface, UART, I/O ports, and more).

  • Page 6: Tea6415C

    TEA6415C 9.1. 9.1.1. General Description The main function of the IC is to switch 8 video input sources on 6 outputs. Each output can be switched on only one of each input. On each input an alignment of the lowest level of the signal is made (bottom of synch.

  • Page 7: Description

    - Standby current 1 mA typical at 5.0V • 2-wire serial interface bus, I compatible • 100 kHz and 400 kHz compatibility • Self-timed ERASE and WRITE cycles • Power on/off data protection circuitry • Hardware write protect • 1,000,000 Erase/Write cycles guaranteed •...

  • Page 8: Functional Descriptions

    9.2.4. Functional Descriptions The 24C32A supports a Bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus must be controlled by a master device which generates the Serial Clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24C32A works as slave.

  • Page 9: Pin Connections

    9.4.3. Pin connections DIP Pin connections CO Pin connections NC: Not connected Signal names Serial data Address Input/Output Serial Clock (I C mode) Supply voltage Ground VCLK Clock transmit only mode TLC7733 9.5. 9.5.1. Description The TLC77xx family of micro power supply voltage supervisors is designed for reset control, primarily in microcomputer and microprocessor systems.

  • Page 10: 74Lvc257A

    74LVC257A 9.6. 9.6.1. Features Wide supply voltage range of 1.2 to 3.6 V In accordance with JEDEC standard no. 8-1A CMOS lower power consumption Direct interface with TTL levels Output drive capability 50 _ transmission lines at 85°C 5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic 9.6.2.

  • Page 11: Pin Description

    9.7.4. Pin Description PIN NUMBER SYMBOL DESCRIPTION 1, 3, 5, 9, 11, 13 1A – 6A Data inputs 2, 4, 6, 8, 10, 12 1Y – 6Y Data outputs Ground (0V) Positive supply voltage TEA6420 9.8. 9.8.1. Features • 5 Stereo Inputs •...

  • Page 12: Applications

    9.9.3. Applications • SCSI-2 Active Terminator • High Efficiency Linear Regulators • Battery Charger • Post Regulation for Switching Supplies • Constant Current Regulator • Microprocessor Supply 9.9.4. Connection Diagrams TO-220 TO-263 10094802 Top View 10094804 Top View 9.10. LM1117 9.10.1.

  • Page 13: Ds90C385

    9.11. DS90C385 9.11.1. General Description The DS90C385 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signalling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted.
  • Page 14 DS90C385SLC SLC64A Package Pin Description-FPD Link Transmitter Pin Name Description TTL level input. TxIN Positive LVDS differentiaI data output. TxOUT+ TxOUT- Negative LVDS differential data output. TTL Ievel clock input. The rising edge acts as data strobe. Pin name TxCLK IN. TxCLKIN R_FB Programmable strobe select.

  • Page 15: Msp34X1G

    9.12. MSP34X1G MSP3411G Multistandard Sound Processor Family 9.12.1. Introduction The MSP 34x1G family of single-chip Multistandard Sound Processors covers the sound processing of all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip.

  • Page 16: Features

    9.12.2. Features • 3D-PANORAMA virtualizer (approved by Dolby Laboratories) with noise generator • PANORAMA virtualizer algorithm • Standard Selection with single I C transmission • Automatic Sound Selection (mono/stereo/bilingual), • Automatic Carrier Mute function • Interrupt output programmable (indicating status change) •...
  • Page 17 AVSUP Analog power supply 5V AVSUP Analog power supply 5V Not connected Not connected AVSS Analog ground AVSS Analog ground MONO_IN Mono input Not connected Reference voltage IF A/D VREFTOP converter SC1_IN_R SCART 1 input, right SC1_IN_L SCART 1 input, left ASG1 AHVSS Analog Shield Ground 1...

  • Page 18: Tda1308

    9.13. TDA1308 9.13.1. General Description The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 or a DIP8 plastic package. The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital audio applications.

  • Page 19: Pinning

    9.13.3. Pinning SYMBOL DESCRIPTION OUTA Output A INA(neg) Inverting input A INA(pos) Non-inverting input A Negative supply INB(pos) Non-inverting input B INB(neg) Inverting input B OUTB Output B Positive supply 9.14. PI5V330 9.14.1. General Description The PI5V330 is well suited for video applications when switching composite or RGB analog. A picture- in-picture application will be described in this brief.

  • Page 20: Pin Descriptions

    9.15.3. Pin Descriptions Complete Pinout list Pin Type Mnemonic Function Value Pin No. Inputs RAIN Analog Input for Converter R 0.0 V to 1.0 V GAIN Analog Input for Converter G 0.0 V to 1.0 V BAIN Analog Input for Converter B 0.0 V to 1.0 V HSYNC Horizontal SYNC Input...
  • Page 21 AD9883A. Vsync separation is performed via the sync separator.) SERIAL PORT (2-WIRE) Serial Port Data I/O Serial Port Data Clock Serial Port Address Input 1 For a full description of the 2-wire serial register and how it works, refer to the 2- Wire Serial Control Port section.

  • Page 22: Saa7118E

    trailing edge of the Hsync input. The logic sense of this pin is controlled by Clamp Polarity register 0FH, Bit 6. When not used, this pin must be grounded and Clamp Function programmed to 0. COAST Clock Generator Coast Input (Optional) This input may be used to cause the pixel clock generator to stop synchronizing with Hsync and continue producing a clock at its current frequency and phase.

  • Page 23: Features

    It is a highly integrated circuit for desktop video and similar applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into ITU 601 compatible colour component values. The SAA7118E accepts CVBS or S-video (Y/C) as analog inputs from TV or VCR sources, including weak and distorted signals as well as baseband component signals Y-P or RGB.

  • Page 24: Pinning

    • Two independent programming sets for scalar part, to define two ‘ranges’ per field or sequences over frames • Field wise switching between decoder part and expansion port (X-port) input • Brightness, contrast and saturation controls for scaled outputs. Vertical Blanking Interval (VBI) data decoder and slicer •...
  • Page 25 square wave clock signal I/pu test data input for boundary scan test; note 2 I/pu test clock for boundary scan test; note 2 data qualifier for expansion port XPD1 MSB - 6 of expansion port data XPD3 MSB - 4 of expansion port data XPD5 MSB - 2 of expansion port data XTRI...
  • Page 26 Digital ground 6 (core) SSD6 Digital supply voltage 6 (core) DDD6 HPD5 MSB - 2 of host port data I/O, extended C input for expansion port, extended C output for image port HPD6 MSB - 1 of host port data I/O, extended C input for expansion port, extended C output for image port...
  • Page 27 IGP0 general purpose output signal 0; image port (controlled by subaddresses 84H and 85H) AOUT analog test output (do not connect) ground for internal Clock Generation Circuit (CGC) SSA0 analog supply voltage (3.3 V) for internal clock generation DDA0 circuit Digital supply voltage 9 (peripheral cells) DDD9 Digital supply voltage 10 (core)

  • Page 28: Tps72501

    2. In accordance with the “IEEE1149.1” standard the pads TDI, TMS, TCK and TRST are input pads with an internal pull-up transistor and TDO is a 3-state output pad. 3. For board design without boundary scan implementation connect the TRST pin to ground. 4.

  • Page 29: Tsop1836

    • ±2% Output Voltage Tolerance over Line, Load, and Temperature (–40C to 125C) • Integrated UVLO • Thermal and Over Current Protection • 5-Lead SOT223–5 or DDPAK and 8–Pin SOP (TPS72501 only) Surface Mount Package 9.18. TSOP1836 9.18.1. Description The TSOP18.. – series are miniaturized receivers for infrared remote control systems. PIN diode and preamplifier are assembled on lead frame, the epoxy package is designed as IR filter.

  • Page 30: Pinning

    • Serial input/output via I 2 C-bus • Address by 3 hardware address pins • Sampling rate given by I 2 C-bus speed • 4 analog inputs programmable as single-ended or differential inputs • Auto-incremented channel selection • Analog voltage range from •...

  • Page 31: Applications

    • Copy Protection • Two-Wire Serial Interface 9.20.3. Applications For use with Digital Displays • Flat-Panel (LCD, DLP) TVs • Rear Projection TVs • Plasma Displays • LCD Multimedia Monitors • Multimedia Projectors 9.21. PW181 9.21.1. General Description The PW181 Image Processor is a highly integrated “system-on-a-chip” that interfaces computer graphics and video inputs in virtually any format to a fixed-frequency flat panel display.

  • Page 32: Sil151B

    • Multi-region, non-linear scaling • Hardware 2-wire serial bus support 9.21.3. Applications • Multimedia Displays • Plasma Displays • Digital Television 9.22. SIL151B 9.22.1. General Description The SiI 151B receiver uses Panel Link Digital technology to support high-resolution displays up to SXGA (25-112MHz).

  • Page 33: Features

    SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access.
  • Page 34 after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH.

  • Page 35: Flash 8Mbit

    9.24. FLASH 8MBit 9.24.1. Description The M29W800A is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a Byte-by-Byte or Word-by-Word basis using only a single 2.7V to 3.6V V supply. For Program and Erase operations the necessary high voltages are generated internally. The device can also be programmed in standard programmers.

  • Page 36: Service Menu Settings

    10. SERVICE MENU SETTINGS All system, geometry and white balance alignments are performed in production service mode. Before starting the production mode alignments, make sure that all manual adjustments are done correctly. To start production mode alignments enter the MENU by pressing “M” button and then press the buttons Mute, Dual, Wide and Red respectively.
  • Page 37 scart prescale By pressing ‘’ / ’’ button, select scart prescaler. Press ‘’ / ’’ button to set the scart prescaler. Scart prescale can be adjusted between 0 and 127. nicam prescale By pressing ‘’ / ’’ button, select nicam prescaler. Press ‘’ / ’’ button to set the nicam prescaler. Nicam prescale can be adjusted between 0 and 127.

  • Page 38: Calibration Menu

    10.2. calibration menu By pressing “◄/►” buttons select the second icon. calibration menu appears on the screen. calibrati on 55 00K 7500K 9300K use r colo r temp 6500 K vide o f ormat auto colo rspace test pattern no ne solid color vert bars colo r components...

  • Page 39: Deinterlacer Menu

    colour components By pressing ‘’ / ’’ button, select colour components. Press ‘’ / ’’ button to set the colour components. The options are: all, red, green and blue. solid field level By pressing ‘’ / ’’ button, select solid field level. Press ‘’ ’’ button to increase or ‘’ ’’ button to decrease the solid field level.
  • Page 40 deinterlacer bad cut nr threshold high noise reduction lai level sharpness sparkle right/left to adjust item film mode speed By pressing ‘’ / ’’ button, select film mode speed. Film mode speed can be set to 0, 1, 2 or 3 by pressing ‘’...

  • Page 41: Service Menu Factory Reset Values

    10.3. Service menu factory reset values SERVICE MENU BLANK COLOUR black SCART PRESCALE NICAM PRESCALE DISPLAY FM/AM PRESCALE SUBWOOFER CORNER SUBWOOFER LEVEL COLOUR TEMPERATURE 6500 COLOUR TEMPERATURE-USER 6500 VIDEO FORMAT AUTO COLOUR SPACE autodetected CALIBRATION TEST PATTERN none COLOUR COMPONENTS SOLID FIELD LEVEL INITIAL APS BLACK EXPANSION...

  • Page 42: Block Diagram

    11. BLOCK DIAGRAM GENERAL BLOCK DIAGRAM MAIN_L, MAIN BOARD AUDIO AMPL. BOARD MAIN_R, 6 LAYER 2 -LAYER AUDIO DECODING MSP34XX AUDIO MICRONAS AMPLIFIER TPA3002D AUDIO/VIDEO/GRAPHICS IN/OUT SAA7118E 16 -bit B 24 -bit VIDEO PROCESSOR PW1231 MAIN PICTURE 24 - bit RGB PHILIPS HS, VS, PW181...
  • Page 43 TUNER&IF BLOCK SC3_V_OUT A/V BOARD 6-layer SC1_V_OUT TO TEA6415 UV1316 TUN1_CVBS PHILIPS IF 1 VIDEO SWITCH Tuner 1 IF IC 1 TO MSP3411G Philips TUN1_QSS1 TDA9886 AUDIO PROCESSOR FOR MAIN SOUND TO TEA6415 PIP UV1316 TUN2_CVBS PHILIPS IF 2 VIDEO SWITCH Tuner 2 IF IC 2 TO MSP3411G...
  • Page 44 VIDEO MATRIXING Plasma TV Service Manual 11/01/2005...
  • Page 45 AUDIO MATRIXING Plasma TV Service Manual 11/01/2005...
  • Page 47 VIDEO & IMAGE PROCESSING VxtoSAA7118_MP SVIDEO1_C 24-bit SVIDEO1_Y 16-bit YUV PW1231 VRGB 7118 TXT/CC_FB TXT/CC_FB DE-INTERLACER TXT/CC_R TXT/CC_R TXT/CC_R TXT/CC_G TXT/CC_G TXT/CC_G TXT/CC_B TXT/CC_B TXT/CC_B PW181 Progressive or De-interlacer VxtoSAA7118_PIP Interlaced SVIDEO1_C 24-bit dual RGB, HS, VS, DE, SVIDEO1_Y Scaler PCLK, Parity SCART1 SCART1...
  • Page 48 TELETEXT DECODING & PIN8 SWITCHING TELETEXT TXT/CC_FB CVBS_ INTO SAA7118 FROM VIDEO SAA5264 TXT/CC_R for TELETEXT SWITCH TXT/CC_G RGB/FB PORTS PHILIPS TXT/CC_B SC1 PIN8 SC1 PIN8 PIN 8 SC2 PIN8 SC2 PIN8 I2C COMMUNICATION SWITCHING SC3 PIN8 SC3 PIN8 PCF8591 SC4 PIN8 SC4 PIN8 Plasma TV Service Manual...
  • Page 49 INPUT & OUTPUTS 1. SCART 1 CVBS INPUT 1. SCART 1 CVBS OUT 2. SCART 2 CVBS INPUT 2. SCART 2 CVBS OUT 3. SCART 1 RGB FB INPUT 3. AUDIO LINE OUT 4. SCART 2 RGB FB INPUT 5. FAV IN 6.

  • Page 50: Circuit Diagrams

    12. CIRCUIT DIAGRAMS...
  • Page 60 Fax: +46 (0) 8 562 711 13 Tel: +39 02 38073415 Servizio Clienti Email: csgswe@hitachi-eu.com Fax: +39 02 48786381/2 Email: customerservice.italy@hitachi-eu.com HITACHI EUROPE S.A.S HITACHI EUROPE LTD (Norway) AB Lyon Office STRANDVEIEN 18 B.P. 45, 69671 BRON CEDEX 1366 Lysaker FRANCE...

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