LG 55LW9500 Service Manual page 50

GP3 Backend block diagram (SG)
+3.3VD
+1.5V1
DC-DC Converter
DC-DC Converter
(AOZ1072AI)
(AOZ1072AI)
+1.5V1
Vol. Regulator
Vol. Regulator +0.75V_VTT1
(TPS51200)
(TPS51200)
VLCD_POWER
DPM/FLK
PMIC
PMIC
(TPS65168)
(TPS65168)
(0x42)
(0x42)
P_VCOM/
VCOMLFB/
VCOMRFB
80P mini-LVDS Output
Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
+3.3VD
DC-DC Converter +1.5V0
DC-DC Converter
(AOZ1072AI)
(AOZ1072AI)
+1.5V0
Vol. Regulator
Vol. Regulator +0.75V_VTT0
(TPS51200)
(TPS51200)
DDR1_A[12:0]/
DDR3 SDRAM BA[2:0]/CLK/CKE
DDR3 SDRAM
-
-
1Gbit (x16)
1Gbit (x16)
DDR1_DATA[15:0]
- 800MHz
- 800MHz
I2C_SCL
I2C_SDA
VCC_LCM/VDD_LCM/
VGH/VGL/HVDD/VCORE
VCOMLOUT/
VCOMROUT
I2C_SCL
I2C_SDA
Dual-link HF mini-LVDS
(@297MHz)
VCC_LCM/VDD_LCM/
HVDD
GMA[18:15],
GMA[9:5]
I2C_SCL P-GAMMA
P-GAMMA
IC
IC P_VCOM
(MAX9668B)
I2C_SDA
(MAX9668B)
(0xE8)
(0xE8)
RIGHT
DDR3 SDRAM
DDR3 SDRAM
-
-
1Gbit (x16)
1Gbit (x16)
- 800MHz
- 800MHz
DDR0_A[12:0]/
DDR0_DATA[15:0]
BA[2:0]/CLK/CKE
XTAL_IN
XTAL_OUT
(24.75Mhz)
SPI_DI
SPI_DO/CK/CS
LG1121
(0x1C, direct
0xB2, in-direct)
FRC_RESET
3D_SYNC_OUT
Octa-link LVDS
XTR
I2C_TCON_SCL
I2C_TCON_SDA
T-Con
(0x72)
Dual-link HF mini-LVDS
(@297MHz)
VCC_LCM/VDD_LCM/
HVDD
I2C_SCL P-GAMMA
P-GAMMA
(MAX9668B)
I2C_SDA
(MAX9668B)
(0xEA)
(0xEA)
Z_OUT
51Pin LVDS Input
2D 3D
to
X-Tal
(0x8E)
SPI FLASH
SPI FLASH
(4Mbit)
(4Mbit)
Dual-link LVDS(@74.25MHz)
+1.0V
EEPROM
EEPROM
(64kbit)
(64kbit)
+3.3VD
+2.5V
GMA[14:10],
GMA[4:1]
IC
IC
80P mini-LVDS Output
LEFT
VLCD_POWER
+1.0VD
DC-DC Converter
DC-DC Converter
(AOZ1072AI)
(AOZ1072AI)
I2C_SCL
I2C_SDA
VLCD_POWER
DC-DC Converter
DC-DC Converter
(AOZ1024DI)
(AOZ1024DI)
VLCD_POWER
DC-DC Converter
DC-DC Converter
(AOZ1072AI)
(AOZ1072AI)
+3.3VD
LDO Regulator
LDO Regulator
(AP2132MP)
(AP2132MP)
LGE Internal Use Only