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Apex Digital STX104 Reference Manual

16-bit analog i/o module with 1m sample fifo and dual 16-bit dacs
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  • Page 2 STX104 Reference Manual Analog I/O with 16-Bit Resolution Apex Embedded Systems 116 Owen Road Monona, WI 53716 Phone 608.256.0767 • Fax 608.256.0765 www.apexembeddedsystems.com customer.service@apexembeddedsystems.com Copyright Notice Copyright © 2009 by Apex Embedded Systems. All rights reserved.

  • Page 3: Table Of Contents

    STX104 Reference Manual Table of Contents Welcome Legal Notice Benefits and Features Executive Summary Photo Errata ESD Caution PC/104 Insertion Caution Definitions ADC-Sample ADC-Burst Analog Input Sample Event Frame Intra-Sample Analog Inputs Calibration Connectivity Single-Ended Differential Data Acquisition Modes Classic DAS16jr/16 Classic DAS1602 Copyright ©...
  • Page 4 STX104 Reference Manual Continuous High Speed Sampling Start/Stop-Trigger Encased Frame Groups N-Sample Collection Analog Input Sample Timing Triggering Subsystem Moving Average Filter CPU Readout Methods DMA Read Burst Read Single Read Analog Outputs Calibration Connectivity Hardware Configuration Base Address Table...
  • Page 5 STX104 Reference Manual DAC Channel-A MSB (Offset=5) DAC Channel-A (Offset=4) DAC Channel-B LSB (Offset=6) DAC Channel-B MSB (Offset=7) DAC Channel-B (Offset=6) Clear Interrupts (Offset=8) ADC Status (Offset=8) ADC Control (Offset=9) Pacer Clock Control (Offset=10) FIFO Status MSB (Offset=10) ADC Configuration (Offset=11) 8254 CT0 Data (Offset=12, RB='0'.
  • Page 6 STX104 Reference Manual Interrupt Threshold (Index=8, RB='1') Digital Output Configuration (Index=12, RB='1') Digital Input Configuration (Index=14, RB='1') Trigger Configuration (Index=16, RB='1') Trigger Start Delay (Index=20, RB='1') Analog Input General Configuration (Index=32, RB='1') Analog Input Frame Timer (Index=36, RB='1') Analog Input Burst Timer (Index=40, RB='1')

  • Page 7: Specifications

    STX104 Reference Manual Specifications Ordering Information Index Copyright © 2009 by Apex Embedded Systems. All rights reserved. Thursday, October 08, 2009...

  • Page 9: Welcome

    STX104 Reference Manual STX104 Reference Manual Welcome Dear Valued Customer: Thank you for your interest in our products and services. Apex Embedded Systems "Continuous improvement" policy utilizes customer feedback to improve existing products and create new product offerings based on needs of our customers.

  • Page 11: Legal Notice

    STX104 Reference Manual Legal Notice Apex Embedded Systems’ sole obligation for products that prove to be defective within 1 year from date of purchase will be for replacement or refund. Apex Embedded Systems gives no warranty, either expressed or implied, and specifically disclaims all other warranties, including warranties for merchantability and fitness.

  • Page 13: Benefits And Features

    • One interrupt per 512-samples is possible in FIFO mode • On-board LED to indicate that the STX104 is being addressed. By observing the LED you can quickly determine system activity. • Polarized locking I/O connector. This eliminates board failures due to incorrect connector orientation.
  • Page 14 • DIN3 and DIN1 ( see page 89) the user can reverse the swapped positions of these inputs. • An additional high speed FIFO can be enabled ( see page 104) between STX104 main memory and the ISA bus, further Copyright ©...

  • Page 15: Photo

    3.2 Photo STX104 Reference Manual reducing and/or eliminating wait state (IOCHRDY) conditions. • All status registers are properly latched as well to prevent change in values during a bus read cycle. • I/O Read line is digitally filtered to support noisy bus problems and eliminate the possibility of dropped analog input data.

  • Page 17: Errata

    STX104 Reference Manual Errata Addresses known board related issues and includes methods to work around the issues. Description none --- end Copyright © 2009 by Apex Embedded Systems. All rights reserved. Thursday, October 08, 2009...

  • Page 19: Esd Caution

    STX104 Reference Manual ESD Caution A discharge of static electricity from your hands can seriously damage certain electrical components on any circuit board. Before handling any board, discharge static electricity from yourself by touching a grounded conductor such as your computer chassis (your computer must be turned off).

  • Page 21: Pc/104 Insertion Caution

    STX104 Reference Manual PC/104 Insertion Caution Before powering up the PC/104 stack... and look for proper PC/104 connector alignment. This simple step will prevent permanent board damage. Helpful hint: During system prototyping install the spacers to help guide installation and provide another means of checking board alignment.

  • Page 23: Definitions

    Analog Input Sample Event Analog Input Sample Event is a signal that causes either an analog input sample or analog input burst, depending on how the STX104 is set up. Frame A Frame is a generalized term. This is the record that is deposited per frame time into the FIFO memory. Currently, a frame is the equivalent to an ADC-Burst in terms of the amount of samples stored in the FIFO.
  • Page 24 STX104 Reference Manual 7.5 Intra-Sample See Also Analog Input Burst Timer ( see page 97) Copyright © 2009 by Apex Embedded Systems. All rights reserved. Thursday, October 08, 2009...

  • Page 25: Analog Inputs

    8.2 Connectivity STX104 Reference Manual Analog Inputs Calibration Description Perform the following procedure to adjust ADC input. We recommend averaging ADC values over at least 256 samples in order to provide the most accurate calibration possible, reference the Voltage Input Conversion section under the ADC Data Register see page 45) description.

  • Page 26: Connectivity

    A single-ended input channel consists of one input. The output is the difference between the input and AGND (common). Jumper Setup J8 jumper must be installed for single-ended mode of operation. This also configures the STX104 card for sixteen analog input channels.

  • Page 27: Differential

    8.2 Connectivity STX104 Reference Manual Differential minimum settling time. More details can be found here ( see page 97). Input Ranges The input ranges for single-ended inputs. SINGLE-ENDED INPUT RANGE RESOLUTION UNIPOLAR/BIPOLAR (J9) ACFG.ADBU ACFG.G1 ACFG.G0 ( CHn) +/- 10 V...
  • Page 28 All analog inputs require a small amount of bias current, on the order of tens of nano-amps. If the sensor or signal source is not referenced to the STX104 AGND or system power supply then a resistor must be tied from one of the differential leads to AGND.
  • Page 29 If the negative side of the source driving the bridge is tied to the system supply that supplies power to the STX104, then the is not required because input bias currents have a complete DC path. If you are not sure whether your signal source is...

  • Page 30: Data Acquisition Modes

    Description The DAS16jr/16 mode is the simplest of all STX104 modes, and this mode is compatible with many other cards. In this case, as seen by the illustration below, sampling is equally spaced. If phase delay between channels is not important, this mode offers maximum settling time between channels.

  • Page 31: Classic Das1602

    8.3 Data Acquisition Modes STX104 Reference Manual Classic DAS1602 This mode typically uses the 8254 timer to set the sampling rate, however, other sampling sources can now be configured via the Analog Input General Configuration Register ( see page 93). The frame counter (...

  • Page 32: Continuous High Speed Sampling

    Continuous High Speed Sampling STX104 Reference Manual 8.3 Data Acquisition Modes This mode typically uses the 8254 timer to set the sampling rate, however, other sampling sources can now be configured via the Analog Input General Configuration Register ( see page 93). The frame counter (...

  • Page 33: Start/Stop-Trigger Encased Frame Groups

    8.3 Data Acquisition Modes STX104 Reference Manual Start/Stop-Trigger Encased Frame Groups See Also FIFO Status MSB ( see page 65) Interrupt Configuration ( see page 84) 8.3.4 Start/Stop-Trigger Encased Frame Groups • Start-Trigger to begin sampling, then Stop-Trigger to stop sampling. Repeat sequence.

  • Page 34: N-Sample Collection

    N-Sample Collection STX104 Reference Manual 8.3 Data Acquisition Modes See Also Trigger Configuration ( see page 90) Analog Input Frame Maximum ( see page 99) 8.3.5 N-Sample Collection • Start-Trigger to begin sampling, stop sampling when N-samples/-Frames reached (i.e. Stop-Trigger event).

  • Page 35: Analog Input Sample Timing

    8.4 Analog Input Sample Timing STX104 Reference Manual See Also Analog Input Frame Maximum ( see page 99) Analog Input Sample Timing Description The example below illustrates various methods of setting up analog input sample timing. There are two primary parameters needed to setup timing: time between frames, and time between samples (i.e.
  • Page 36 STX104 Reference Manual 8.4 Analog Input Sample Timing Method for configuring the Analog Input Frame Timer ( see page 95) and the Analog Input Burst Timer ( see page 97) registers. a) Our assumption is that ADC-burst mode will always be enabled, and is acceptable for all situations.
  • Page 37 8.4 Analog Input Sample Timing STX104 Reference Manual /*################################################################################## ANALOG INPUT TIMING FUNCTIONS /***************************************************************** ANALOG INPUT MINIMUM SETTLING TIME static unsigned long STX104_AI_Time_Settling_Minimum( float ai_capacitance_pf, float ai_resistance_ohms ) unsigned long settle_time_ns; //settle_time = ai_resistance_ohms * ai_capacitance_pf * pow10(-12) * 16 * ln(2) * pow10(9)

  • Page 38: Triggering Subsystem

    STX104 Reference Manual 8.5 Triggering Subsystem switch ( stx104_revision[board] ) case STX104_REVISION_080214: /* same as version 080407 */ case STX104_REVISION_090115: STX104_Set_Bank( board, 1 ); STX104_Write_Indexed_Data_Byte( board, STX104_BURST_FUNCTION_ENABLE_INDEXED, 0x40 STX104_Write_Indexed_Data_Byte( board, STX104_BURST_MODE_ENABLE_INDEXED, 0x40 STX104_Write_Indexed_Data_Byte( board, STX104_CONVERSION_DISABLE_INDEXED, 0x00 adc_burst_channel_count = (unsigned char)( 0x0F & ( stx104_ai_channel_last[board] - stx104_ai_channel_first[board] ) );...
  • Page 39 What is the purpose of the triggering subsystem? It allows precise control as to when analog input sampling can occur. It is possible to synchronize sampling to 60Hz line source or whatever is chosen. It is possible to configure the STX104 to trigger on an event and accumulate N-samples and then stop sampling.

  • Page 40: Moving Average Filter

    DMA Read STX104 Reference Manual 8.7 CPU Readout Methods See Also Trigger Configuration ( see page 90) Moving Average Filter Description Installing jumper M3 enables the 16-sample moving average filter for all channels. The filter can be reset (or cleared) by writing to the Channel Register.

  • Page 41: Burst Read

    ADC sampling. Writing 0x00 to the Conversion Disable Register ( see page 78) will allow ADC sampling to continue. In order to use DMA, you must set up the computer’s DMA controller and page registers before enabling DMA on the STX104 board.

  • Page 43: Analog Outputs

    9.2 Connectivity STX104 Reference Manual Analog Outputs Calibration Description Hardware configuration: 1. Select the desired output range by adjusting jumper settings at J5. 2. Install jumper M2 as required for the application (this jumper selects 16-bit versus 12-bit resolution). Calibration of DAC Channel-A: 1.

  • Page 45: Hardware Configuration

    10.1 Base Address Table STX104 Reference Manual Hardware Configuration 10.1 Base Address Table Card Base Address set via installing jumpers at J6 positions A9, A8, A7, A6, A5 and A4. Installing jumper M4 will reduce address I/O decode from a full 16-bits to 10-bits, this provides compatibility with CPU cards that only offer 10-address bits for I/O transactions.

  • Page 46: Compatibility Selection And Extended Functions

    10-BIT ADDRESS DECODE The STX104 now supports CPU cards which only present the first 10 address lines. Normally, the STX104 will decode all 16 address bits in order to fully decode an I/O command. For 10-bit address decode, the upper 6 address bits are ignored. A 10-bit address decode provides a typical I/O address space from 0x000 to 0x3FF.

  • Page 47: Cpu Limitation Accommodations

    The HSFIFOEN bit found in the FIFO Configuration ( see page 104) register can be used to enable a 2048 sample high speed pre-queueing FIFO buffer between STX104 main memory and the ISA bus. In general, this will reduce/eliminate IOCHRDY wait states and improve average system throughput.
  • Page 48 STX104 Reference Manual 10.3 CPU Limitation Accommodations • 10- or 16-bit Address decoding • 8- or 16-bit PC/104 data bus (without or with 40-pin connector, respectively). Copyright © 2009 by Apex Embedded Systems. All rights reserved. Thursday, October 08, 2009...

  • Page 49: Register Set

    11.1 Summary STX104 Reference Manual Register Set 11.1 Summary Overview of the STX104 register set. Description Register Name NOTE Mnemonic Size Direction Offset Index Bank (acr.rb) Software Strobe ( see page 44) (3)(4) BYTE ADC Data LSB ( see page 45)
  • Page 50 STX104 Reference Manual 11.1 Summary Index Data LSB ( see page 74) BYTE Index Data MSB ( see page 75) BYTE Index Data ( see page 75) data WORD Index Pointer ( see page 76) index BYTE ::::::::: DAS1602 Registers Section :::::::::...
  • Page 51 (3) Renamed register to reflect generalizations. (4) Additional functionality added (5) New register as of February 14, 2008 (6) New register as of January 15, 2009 Example /* STX104 Register Set Definitions */ #define STX104_SOFTWARE_STROBE /* offset (to be added to the base address) */...

  • Page 52: Software Strobe (Offset=0)

    STX104 Reference Manual 11.2 Software Strobe (Offset=0) #define STX104_INDEXED_DATA_MSB #define STX104_INDEX_DATA #define STX104_INDEX_POINTER // indexed register array #define STX104_GENERAL_CONFIGURATION /* index */ #define STX104_INTERRUPT_SOURCE_SELECT #define STX104_INTERRUPT_CONFIGURATION #define STX104_INTERRUPT_THRESHOLD #define STX104_DIGITAL_OUTPUT_CONFIGURATION #define STX104_DIGITAL_INPUT_CONFIGURATION #define STX104_TRIGGER_CONFIGURATION #define STX104_TRIGGER_START_DELAY #define STX104_ANALOG_INPUT_GENERAL_CONFIG #define STX104_ANALOG_INPUT_FRAME_TIMER...

  • Page 53: Adc Data Lsb (Offset=0)

    11.5 ADC Data (Offset=0) STX104 Reference Manual ADC-burst or trigger signalling as shown below. DATA VALUE WRITTEN TEN DESCRIPTION 0xXX (Don't care) Software controlled ADC-Sample or ADC-Burst 0x55 Software generated trigger start 0xAA Software generated trigger end (or stop) 0x5A...
  • Page 54 Data bandwidth between the STX104 and CPU (PC/104 ISA bus) can be doubled by simply reading the ADC register as a 16-bit register. Software examples are shown below. Further improvement in bus bandwidth can be had by limiting the CPU-burst readouts (i.e.
  • Page 55 This is usually available on many CPU cards. Limiting the size of the sample count to the STX104 data fragment buffer in the Insw() function call will eliminate I/O bus wait states and further enhance overall throughput.
  • Page 56 An example shown below illustrating how to set the gain and use it to determine the actual input voltage. /**************************************************************************** Apex Embedded Systems Revised: 03MAR08 STX104 Analog Input Demo Copyright © 2009 by Apex Embedded Systems. All rights reserved. Thursday, October 08, 2009...
  • Page 57 = 0x00; /* scan channel zero only */ /* base address set to factory default at 0x300 */ /* initialize STX104 */ outportb(0x309, 0x00); /* no interrupts, no DMA and s/w trigger */ /* Applies to firmware revision 080214H only: for non-zero first_channel please write to channel register twice to correct for errata issue.

  • Page 58: Adc Channel (Offset=2)

    STX104 Reference Manual 11.6 ADC Channel (Offset=2) ( y == 0 ) printf("10V, "); else if ( y == 1 ) printf(" 5V, "); else if ( y == 2 ) printf(" 2.5V, "); else if ( y == 3 ) printf(" 1.25V,");...
  • Page 59 The current-channel is presented as CH[3:0] in the ADC Status Register ( see page 60). If the STX104 is configured for differential input mode, the most significant bit of the current-channel (and therefore first- and last-channel) is ignored.

  • Page 60: Digital Outputs (Offset=3)

    STX104 Reference Manual 11.7 Digital Outputs (Offset=3) Errata ( see page 9) Example Example channel sequencing (all in hexadecimal values): a) LC[3:0] = D, FC[3:0] = 3 16-Channel, Single Ended: 3,4,5,6,7,8,9,A,B,C,D,3,4,5,... 8-Channel, Differential ( see page 19): 3,4,5,3,4,5,... b) LC[3:0] = 1, FC[3:0] = 9 16-Channel, Single Ended: 9,A,B,C,D,E,F,0,1,9,A,B,C,...

  • Page 61: Digital Inputs (Offset=3)

    11.8 Digital Inputs (Offset=3) STX104 Reference Manual BIT NAME DIRECTION CONNECTOR PIN PHYSICAL I/O TYPE POSITION DOUT3 ---> J7.5 LVTTL Output DOUT2 ---> J7.6 LVTTL Output DOUT1 ---> J7.7 LVTTL Output DOUT0 ---> J7.8 LVTTL Output Description Digital TTL Outputs.

  • Page 62: Dac Channel-A Lsb (Offset=4)

    DIN2 <--- J7.10 TTL Input DIN1 <--- J7.9 TTL Input DIN0 <--- J7.12 TTL Input Classic STX104 Configuration (supporting existing customers, Default mode) BIT NAME DIRECTION CONNECTOR PIN POSITION PHYSICAL I/O TYPE DIN3 <--- J7.9 TTL Input DIN2 <--- J7.10...

  • Page 63: Dac Channel-A (Offset=4)

    11.11 DAC Channel-A (Offset=4) STX104 Reference Manual 11.11 DAC Channel-A (Offset=4) DAC Channel-A Register Register Layout DAC Channel-A LSB. Offset=0x4, Byte 0. Offset=0x4, Word 0. DAC Channel-A MSB. Offset=0x5, Byte 1. Offset=0x4, Word 0. DA15 DA14 DA13 DA12 DA11 DA10...
  • Page 64 STX104 Reference Manual 11.11 DAC Channel-A (Offset=4) OUTPUT VOLTAGE CONVERSION OUTPUT DA1_UB DA1_R RESOLUTION NEG FULL POS FULL NEG FULL POS FULL SCALE SCALE SCALE SCALE RANGE J5 * J5 * VOLTAGE VOLTAGE +/- 10 Volts 305 uV -10.00 +10.00...

  • Page 65: Dac Channel-B Lsb (Offset=6)

    11.14 DAC Channel-B (Offset=6) STX104 Reference Manual 11.12 DAC Channel-B LSB (Offset=6) DAC Channel-B LSB. Please Refer to DAC Channel-B ( see page 57) Register Details. See Also Register Summary ( see page 41) 11.13 DAC Channel-B MSB (Offset=7) DAC Channel-B MSB. Please Refer to DAC Channel-B ( see page 57) Register Details.
  • Page 66 STX104 Reference Manual 11.14 DAC Channel-B (Offset=6) BIT STRING NAME DIRECTION CONNECTOR PIN POSITION PHYSICAL I/O TYPE DB[15:0] ---> J7.16 (DAC_OUT_2) Analog Output Description Each channel is updated once the MSB is written. Writing only the MSB will update the DAC channel output. The results of changing jumper settings at J5 will only take affect after writing the MSB on the DAC output.

  • Page 67: Clear Interrupts (Offset=8)

    11.15 Clear Interrupts (Offset=8) STX104 Reference Manual union { unsigned int word; unsigned char byte[2]; } dac_value; outp( base_address+6, dac_value.byte[0] ); outp( base_address+7, dac_value.byte[1] ); 16-Bit Write in C/C++: unsigned int dac_value; outpw( base_address+6, dac_value ); 11.15 Clear Interrupts (Offset=8)

  • Page 68: Adc Status (Offset=8)

    ADC Conversion (and/or ADC-Burst in DAS1602 mode) in progress. Writing to the Channel Register may cause the CNV bit to become active indicating that a STX104 internal reset is in progress (typically less than 1uS, and less than 10uS when moving average filter is enabled).
  • Page 69 11.17 ADC Control (Offset=9) STX104 Reference Manual Interrupt request status bit. 0 = No interrupt pending (default) 1 = Interrupt is pending; ADC trigger or ADC-Burst conversion has completed Note: ADC conversions continue to occur on schedule (via selected trigger source) regardless of whether this bit is cleared.

  • Page 70: Adc Control (Offset=9)

    STX104 Reference Manual 11.17 ADC Control (Offset=9) 11.17 ADC Control (Offset=9) ADC Control Register Register Layout Offset=0x9, Byte 0. EIS='1', Please refer to the Interrupt Configuration Register ( see page 84). IES3 IES2 IES1 IES0 FIE (a) DMAE ALSS1 (b) ALSS0 (b) Offset=0x9, Byte 0.
  • Page 71 11.17 ADC Control (Offset=9) STX104 Reference Manual ADC Interrupt Enable. 0 = Disable interrupt (default) 1 = Enable interrupt INTS[2:0] Interrupt select: 000 = Not valid, interrupts disabled (default) 001 = Not valid, interrupts disabled 010 = IRQ2 011 = IRQ3...

  • Page 72: Pacer Clock Control (Offset=10)

    ADC triggers (or sampling). Writing 0x00 to the Conversion Disable Register will allow ADC sampling to continue. In order to use DMA, you must set up the computer’s DMA controller and page registers before enabling DMA on the STX104 board.

  • Page 73: Fifo Status Msb (Offset=10)

    11.19 FIFO Status MSB (Offset=10) STX104 Reference Manual CT_SRC0 Counter 0 Clock Source: 1 = Counter 0 Clock Source is a 100KHz on-board reference frequency. CT_SRC0 (J7.4) gates this signal. When this bit is high (default), the 100KHz signal runs, otherwise the 100KHz clock is stopped.
  • Page 74 INSW instruction. There is theoretically no limit, other than the maximum size of the entire STX104 FIFO memory, on the number of consecutive CPU reads that can occur. However, by limiting the number of samples readout by the CPU using the Insw() to approximately the size of the Data Fragment buffer, one can avoid I/O bus wait states and further improve bus bandwidth.
  • Page 75 11.19 FIFO Status MSB (Offset=10) STX104 Reference Manual It should be further stated that the CPU can still readout data at any rate along with any ADC sampling mode. In fact, the data fragment buffer will be used in nearly all cases, thus bus wait states become a thing of the past. The only case where I/O bus wait states will exist are cases where the number of samples read out by the CPU in a CPU-bursting readout (i.e.

  • Page 76: Adc Configuration (Offset=11)

    STX104 Reference Manual 11.20 ADC Configuration (Offset=11) stx104_fifo_status_full[board] = true; else stx104_fifo_status_full[board] = false; For firmware revisions 080214H or higher: static int stx104_fifo_status_blocks[STX104_BOARDS_COUNT_MAX]; static unsigned char stx104_fifo_status_full[STX104_BOARDS_COUNT_MAX]; static unsigned char stx104_fifo_status_empty[STX104_BOARDS_COUNT_MAX]; /***************************************************************** FIFO STATUS void STX104_FIFO_Status( board ) union unsigned int value;...
  • Page 77 REGISTER BANK SELECT Register Bank Select is a mechanism for providing additional configuration options for the STX104, while preserving the existing register set foot-print within the I/O space. Writing the sequence 0xFX, 0x5X, 0xDX will enable the Indexed Register Array Bank.
  • Page 78 STX104 Reference Manual 11.20 ADC Configuration (Offset=11) INPUT RANGE RESOLUTION ADBU +/- 10 V 305 uV +/- 5 V 153 uV +/- 2.5 V 76 uV +/- 1.25 V 38 uV 0 - 10 V 153 uV 0 - 5 V 76 uV 0 - 2.5 V...

  • Page 79: 8254 Ct0 Data (Offset=12, Rb='0'. Index=68, Rb='1')

    11.23 8254 CT2 Data (Offset=14, RB='0'. STX104 Reference Manual else /* request banking to the indexed register array */ ( (scratch & 0x80) == 0 ) scratch = scratch & 0x0F; value = scratch | 0xF0; outp( address, value );...

  • Page 80: 8254 Configuration (Offset=15, Rb='0'. Index=71, Rb='1')

    STX104 Reference Manual 11.24 8254 Configuration (Offset=15, See Also Register Summary ( see page 41) 11.24 8254 Configuration (Offset=15, RB='0'. Index=71, RB='1') 8254 Configuration Register Register Layout Offset=0xC, RB='0'. 8254 Counter/Timer Zero Data Register.This register is available when Register Bank Status is '0' (see ADC Configuration ( see page 68) Register bit RB).
  • Page 81 11.24 8254 Configuration (Offset=15, STX104 Reference Manual SC[1:0] Select Counter: 00 = Select Counter 0 01 = Select Counter 1 10 = Select Counter 2 11 = Read-Back Command (see read operations) RW[1:0] Read/Write: 00 = Counter latch command 01 = Read/Write least significant byte only...

  • Page 82: Fifo Status Lsb (Offset=15)

    STX104 Reference Manual 11.26 Index Data LSB (Offset=12, RB='1') low_count = 10L; /* 1 microsecond intervals */ high_count = time_interval_ns / 1000; while ( high_count > 65536L ) high_count = high_count >> 1; low_count = low_count << 1; while ( high_count < 2L ) high_count = high_count <<...

  • Page 83: Index Data Msb (Offset=13, Rb='1')

    11.28 Index Data (Offset=12, RB='1') STX104 Reference Manual See Also Register Summary ( see page 41) 11.27 Index Data MSB (Offset=13, RB='1') Indexed Data I/O most significant byte (or upper 8-bits). Please refer to Index Data ( see page 75) Register for further details.

  • Page 84: Index Pointer (Offset=14, Rb='1')

    I/O address space. The indexed array of registers are banked onto the 8254 I/O address space. At power up or reset, the entire STX104 register set will appear and function exactly as the previous firmware version of the STX104 card. By writing a...
  • Page 85 11.29 Index Pointer (Offset=14, RB='1') STX104 Reference Manual A logical representation of the indexed register array is illustrated below. The internal registers can consist of bytes (signed or unsigned char), words (signed or unsigned ints) or double words (signed or unsigned long). For advanced configuration it is possible to create a structure that can be simply uploaded to the indexed register array.

  • Page 86: Conversion Disable (Offset=1028; Index=64, Rb='1')

    STX104 Reference Manual 11.30 Conversion Disable (Offset=1028; static void STX104_Write_Indexed_Data_Byte( board, unsigned char index, unsigned char value ) outp( stx104_base_address[board] + STX104_INDEX_POINTER, index ); outp( stx104_base_address[board] + STX104_INDEX_DATA, (unsigned int) value ); /***************************************************************** INDEXED ARRAY DATA WORD WRITE static void...

  • Page 87: Burst Mode Enable (Offset=1029; Index=65, Rb='1')

    11.31 Burst Mode Enable (Offset=1029; STX104 Reference Manual Description Conversion Disable Register. On power-up or reset the conversion triggers are enabled. This register is only available if FE bit is true (DAS1602 Functions are enabled). Writing a 0x00 to this register enables ADC triggering. Writing 0x40 (64 ) to this register disables ADC triggering.

  • Page 88: Burst Function Enable (Offset=1030; Index=66, Rb='1')

    STX104 Reference Manual 11.33 Extended Status (Offset=1031; Example 11.32 Burst Function Enable (Offset=1030; Index=66, RB='1') ADC Function Enable Register. DAS1602 Compatible Configuration Register. In 10-bit address decode mode, the DAS1602 compatible registers are also accessible through the indexed register set.

  • Page 89: Extended Status (Offset=1031; Index=67, Rb='1')

    11.34 General Configuration (Index=0, STX104 Reference Manual 11.33 Extended Status (Offset=1031; Index=67, RB='1') ADC Extended Status Register. DAS1602 Compatible Configuration Register. In 10-bit address decode mode, the DAS1602 compatible registers are also accessible through the indexed register set. Register Layout Offset=0x407, RB=X.

  • Page 90: General Configuration (Index=0, Rb='1')

    STX104 Reference Manual 11.34 General Configuration (Index=0, 11.34 General Configuration (Index=0, RB='1') General Configuration Register Register Layout Index=0x00, Byte 0. RB='1'. AIID DMAJ Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION AIID Auto Index Increment Disable. Index register is automatically incremented by the size (byte/word) of the data that is read or written.

  • Page 91: Interrupt Source Select (Index=2, Rb='1')

    11.35 Interrupt Source Select (Index=2, STX104 Reference Manual Description See Also Register Summary ( see page 41) Example 11.35 Interrupt Source Select (Index=2, RB='1') Interrupt Source Select Register Register Layout Index=0x02, Byte 0, Word 0. RB='1'. ISB3 ISB2 ISB1 ISB0...

  • Page 92: Interrupt Configuration (Index=4, Rb='1')

    STX104 Reference Manual 11.36 Interrupt Configuration (Index=4, ISA[3:0] 0000 Interrupt Source A. Sets the ISA bit in the ADC Status Register when ISSBE=’1’. 0000 = none (default) 0001 = Reserved 0010 = Interrupt Threshold ( see page 86) Counter 0011 = Analog Input Frame Maximum ( see page 99)
  • Page 93 11.36 Interrupt Configuration (Index=4, STX104 Reference Manual ISSBE nINT_FF SITT ITS3 ITS2 ITS1 ITS0 Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION Enhanced Interrupt Selection 0 = Normal interrupt selection in ADC control register ( see page 62) (default) 1 = Enhanced interrupt selection in ADC control register...

  • Page 94: Interrupt Threshold (Index=8, Rb='1')

    STX104 Reference Manual 11.37 Interrupt Threshold (Index=8, RB='1') FIBLK[3:0] 0000 Number of Blocks to generate a FIFO Interrupt. This is the number of samples written to the FIFO in order to generate an interrupt; if the sample timing is constant, then this interrupt will be at a constant rate as well.
  • Page 95 11.38 Digital Output Configuration STX104 Reference Manual ITH15 ITH14 ITH13 ITH12 ITH11 ITH10 ITH9 ITH8 Index=0x0A, Byte 2. Index=0x0A, Word 1. RB='1'. ITH23 ITH22 ITH21 ITH20 ITH19 ITH18 ITH17 ITH16 Index=0x0B, Byte 3. Index=0x0A, Word 1. RB='1'. ITH31 ITH30 ITH29...

  • Page 96: Digital Output Configuration (Index=12, Rb='1')

    STX104 Reference Manual 11.38 Digital Output Configuration 11.38 Digital Output Configuration (Index=12, RB='1') Digital Output Configuration Register Register Layout Index=0x0C, Byte 0. RB='1'. SSHP CT0OP CT2OP DOP3 DOP2 DOP1 DOP0 Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION SSHP SSH (J7.14) Polarity...

  • Page 97: Digital Input Configuration (Index=14, Rb='1')

    11.39 Digital Input Configuration STX104 Reference Manual See Also Register Summary ( see page 41) Example 11.39 Digital Input Configuration (Index=14, RB='1') Digital Input Register Register Layout Index=0x0E, Byte 0. RB='1'. SDGF SDI31 DIP3 DIP2 DIP1 DIP0 Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION...

  • Page 98: Trigger Configuration (Index=16, Rb='1')

    STX104 Reference Manual 11.40 Trigger Configuration (Index=16, Description Sets the polarity and deglitch filters for the digital inputs. See Also Register Summary ( see page 41) Example 11.40 Trigger Configuration (Index=16, RB='1') Trigger Configuration Register Register Layout Index=0x10 Byte 0. Index=0x10 Word 0. RB='1'.
  • Page 99 11.40 Trigger Configuration (Index=16, STX104 Reference Manual TSS[3:0] 0000 Start Trigger Synchronization Source. 0000 = none (default) 0001 = writing 0x5A to the software strobe register 0010 = none 0011 = Analog Input Sample/Frame ( see page 15) Timer 0010 = none...

  • Page 100: Trigger Start Delay (Index=20, Rb='1')

    STX104 Reference Manual 11.41 Trigger Start Delay (Index=20, STS[3:0] 0000 Start Trigger Source 0000 = none (default) 0001 = writing 0x55 to the software strobe register 0010 = none 0011 = Analog Input Sample/Frame ( see page 15) Timer 0100 = 8254 Counter 0 Output (CT_OUT0) rising-edge...

  • Page 101: Analog Input General Configuration (Index=32, Rb='1')

    11.42 Analog Input General Configuration STX104 Reference Manual Index=0x16 Byte 2. Index=0x16 Word 1. RB='1'. TSD23 TSD22 TSD21 TSD20 TSD19 TSD18 TSD17 TSD16 Index=0x17 Byte 3. Index=0x16 Word 1. RB='1'. TSD31 TSD30 TSD29 TSD28 TSD27 TSD26 TSD25 TSD24 Bit Definitions...
  • Page 102 STX104 Reference Manual 11.42 Analog Input General Configuration Register Layout Index=0x20, Byte 0. RB='1'. MAVG_INV SAIFTTS SAIFCTS nSGATE AISS3 AISS2 AISS1 AISS0 Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION Don't Care MAVG_INV Invert the state of the moving average filter jumper (M4). This allows one to enable/disable moving average filter through software.

  • Page 103: Analog Input Frame Timer (Index=36, Rb='1')

    11.43 Analog Input Frame Timer STX104 Reference Manual AISS[3:0] 0000 Analog Input Sampling Sources. This select the signal that is used to generate ADC-samples or ADC-bursts. 0000 = use ALSS[1:0] configuration (default, legacy ADC-sampling/-burst source) 0001 = Analog Input Sample/Frame ( see page 15) Timer.
  • Page 104 STX104 Reference Manual 11.44 Analog Input Burst Timer (Index=40, Index=0x25 Byte 1. Index=0x24 Word 0. RB='1'. AIFT15 AIFT14 AIFT13 AIFT12 AIFT11 AIFT10 AIFT9 AIFT8 Index=0x26 Byte 2. Index=0x26 Word 1. RB='1'. AIFT23 AIFT22 AIFT21 AIFT20 AIFT19 AIFT18 AIFT17 AIFT16 Index=0x27 Byte 3. Index=0x26 Word 1. RB='1'.

  • Page 105: Analog Input Burst Timer (Index=40, Rb='1')

    11.44 Analog Input Burst Timer (Index=40, STX104 Reference Manual 11.44 Analog Input Burst Timer (Index=40, RB='1') Analog Input Burst Timer. Adjusts timing between samples during ADC-burst mode. Register Layout Index=0x28, Byte 0. Index=0x28, Word 0. RB='1'. AIBT7 AIBT6 AIBT5 AIBT4...
  • Page 106 <= 7674 ohms. You will want to keep the devices driving the STX104 inputs with source impedance of less than 8K ohms when operating in Burst mode at its maximum speed and assuming no other source of input capacitance (short cables, for example).

  • Page 107: Analog Input Frame Maximum (Index=44, Rb='1')

    11.45 Analog Input Frame Maximum STX104 Reference Manual a source impedance of 10K ohms. Settle_time = Rin * [ Cin * bits_resolution * ln(2) ] = 10K * [ 300pF * 16 * ln(2) ] = 11.09 * Rin * Cin...

  • Page 108: Analog Input Frame Counter (Index=48, Rb='1')

    STX104 Reference Manual 11.46 Analog Input Frame Counter AIFM31 AIFM30 AIFM29 AIFM28 AIFM27 AIFM26 AIFM25 AIFM24 Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION AIFM[31:0] 0x00000000 Analog Input Frame ( see page 15) Maximum Description When the value of the Analog Input Frame (...

  • Page 109: Miscellaneous Output Configuration Register (Index=208, Rb='1')

    11.47 Miscellaneous Output Configuration STX104 Reference Manual AIFC7 AIFC6 AIFC5 AIFC4 AIFC3 AIFC2 AIFC1 AIFC0 Index=0x31, Byte 1. Index=0x30, Word 0. RB='1'. AIFC15 AIFC14 AIFC13 AIFC12 AIFC11 AIFC10 AIFC9 AIFC8 Index=0x32, Byte 2. Index=0x32, Word 1. RB='1'. AIFC23 AIFC22 AIFC21...
  • Page 110 STX104 Reference Manual 11.47 Miscellaneous Output Configuration Register Layout Index=0xD0, Byte 0. Word 0. RB='1'. CTOUT2PE CTOUT2SEL2 CTOUT2SEL1 CTOUT2SEL0 CTOUT0PE CTOUT0SEL2 CTOUT0SEL1 CTOUT0SEL0 Index=0xD1, Byte 1. Word 0. RB='1'. Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION CTOUT2PE CT_OUT2 (J7.2) pulse extender 0 = disabled (default) 1 = enabled, extend selected signal by 100nSec approximately.

  • Page 111: Fifo Data Available (Index=224, Rb='1')

    11.48 FIFO Data Available (Index=224, STX104 Reference Manual See Also Register Summary ( see page 41) Example 11.48 FIFO Data Available (Index=224, RB='1') FIFO Data Available Register Register Layout Index=0xE0, Byte 0. Index=0xE0, Word 0. RB='1'. FDA7 FDA6 FDA5 FDA4...

  • Page 112: Fifo Configuration (Index=228, Rb='1')

    Description Enabling the High Speed CPU FIFO Buffer can reduce bus wait states generated due to waiting for STX104 main memory data availability. In many cases, bus wait states (due to IOCHRDY) are eliminated. We found that overall throughput through the ISA bus was improved by approximately 15%.

  • Page 113: Scratch Pad (Index=248, Rb='1')

    11.51 Board ID (Index=250, RB='1') STX104 Reference Manual 11.50 Scratch Pad (Index=248, RB='1') Scratch Pad Register Register Layout Index=0xF8, Byte 0. Index=0xF8 Word 0. RB='1'. SCR7 SCR6 SCR5 SCR4 SCR3 SCR2 SCR1 SCR0 Index=0xF9, Byte 1. Index=0xF8 Word 0. RB='1'.
  • Page 114 STX104 Reference Manual 11.51 Board ID (Index=250, RB='1') BID7 BID6 BID5 BID4 BID3 BID2 BID1 BID0 Index=0xFB, Byte 1. Index=0xFA Word 0. RB='1'. BID15 BID14 BID13 BID12 BID11 BID10 BID9 BID8 Bit Definitions NAME DIRECTION DEFAULT DESCRIPTION BID[15:0] Board ID = 0x1008. Revision 080214 (14FEB08) and Revision 080407H (07APR08) Board ID = 0x1009.

  • Page 115: Power Supply

    STX104 Reference Manual Power Supply PC/104 Connector Minimum input Power Requirements at the PC/104 Connector: +5V at 250mA. Power Available at J7 J7.1: +5V at 200mA (+5V at 450mA at the PC/104 connector). J7.15: -5V at 25mA The +5V at J7 pin 1 is tied directly to the PC/104 +5V supply line.

  • Page 117: Interrupt Summary

    STX104 Reference Manual Interrupt Summary Description CLASSIC INTERRUPT SOURCE SELECTION (When Interrupt Configuration Register Bit nINT_FF='0') FIE DMA M1 Interrupt Function 0 No interrupt generated. Poll INT to determine when a DMA terminal count is received from the DMA controller to indicate completion of the DMA transfer.
  • Page 118 STX104 Reference Manual 1 Interrupt generated when 512 samples deposited in the FIFO. Write to the Clear Interrupt Register to clear the interrupt. The number of blocks required to generate an interrupt is now configurable, refer to the Interrupt Configuration ( see page 84) Register.

  • Page 119: Connector Summary

    STX104 Reference Manual Connector Summary Description STX104 I/O Connector J7 Name Notes CT_OUT0 CT_CLK0 CT_OUT2 TRIG/DIN0 DIN1 CT_GATE0 / DIN2 Copyright © 2009 by Apex Embedded Systems. All rights reserved. Thursday, October 08, 2009...
  • Page 120 STX104 Reference Manual DIN3 DOUT0 DOUT1 DOUT2 DOUT3 DAC_OUT_1 DAC_OUT_2 CHn LOW / CHn CHn HIGH / CHn +5V POWER 200mA maximum 25mA maximum DGND AGND See ADC Channel ( see page 50)Register for details UNIPOLAR OR BIPOLAR ANALOG INPUT (J9)
  • Page 121 STX104 Reference Manual Note: 1 = Jumper installed, 0 = Jumper not installed. DAC RANGE SETTINGS (J5) DA1_UB DA1_R DAC-1 RANGE 0 to +5 Volts * 0 to +10 Volts -5 to +5 Volts -10 to 10 Volts * Factory Default Note: 1 = Jumper installed, 0 = Jumper not installed.

  • Page 123: Mechanicals

    STX104 Reference Manual Mechanicals Description The table below lists the locations of key mechanicals of the STX104 board. LOCATION (milli-inches or mils) (milli-inches or mils) Lower Left Mounting Hole Lower Right Mounting Hole 3350 Upper Left Mounting Hole 3575 Upper Right Mounting Hole...
  • Page 124 STX104 Reference Manual Copyright © 2009 by Apex Embedded Systems. All rights reserved. Thursday, October 08, 2009...

  • Page 125: Revision Information

    STX104 Reference Manual Revision Information By scanning and manipulating the STX104 registers one can determine the firmware revision that is installed. Description Revision Releases Date Revision ROM Label Board ID Register Value July 16, 2004 071604 Does not exist February 14, 2008...

  • Page 127: Support Policy

    17.3 Need Custom Modifications? STX104 Reference Manual Support Policy 17.1 General Support Policy We support all hardware products for a period of 3 months from time of delivery. See limited warranty terms. 17.2 Recommended Sequence in Obtaining Customer Support Review user manuals for additional information not found in demo software.
  • Page 129 • Trigger Modes: Gated pacer, software polled. (Gate must be disabled by software after trigger event) • Data Transfer: From 1 mega-sample FIFO via interrupt, DMA or software NOTE: Least Significant Bit (LSB). Analog Outputs ( Without Analog Outputs, see STX104-ND ) • Resolution: 16 bits • Number of Channels: 2 •...
  • Page 130 STX104 Reference Manual configurable by jumpers. • Offset Error: less than 8 LSB • Gain Error: Adjustable to 0 LSB by potentiometer • Differential ( see page 19) non-linearity: ±1 LSB max • Settle Time: 10 microseconds • Integral non-linearity: ±1 LSB max •...
  • Page 131 STX104 16-bit Analog I/O Module with 1M sample FIFO and dual 16-bit DACs. SKU: STX104-1MFIFO-DAQ STX104 without Analog Outputs: Link: STX104-ND 16-bit PC/104 Analog I/O Module with 1M sample FIFO without dual 16-bit DAC SKU: STX104-1MFIFO-DAQ-NODAC ---------------------------------------------------------------------- For the latest drivers and technical support, please contact us at customer.service@apexembeddedsystems.com...
  • Page 133 STX104 Reference Manual Index Calibration 17, 35 Classic DAS1602 23 8254 Configuration (Offset=15, RB='0'. Index=71, RB='1') 72 Classic DAS16jr/16 22 8254 CT0 Data (Offset=12, RB='0'. Index=68, RB='1') 71 Clear Interrupts (Offset=8) 59 8254 CT1 Data (Offset=13, RB='0'. Index=69, RB='1') 71 Compatibility Selection and Extended Functions 38 8254 CT2 Data (Offset=14, RB='0'.
  • Page 134 STX104 Reference Manual FIFO Configuration (Index=228, RB='1') 104 Need Custom Modifications? 119 FIFO Data Available (Index=224, RB='1') 103 N-Sample Collection 26 FIFO Status LSB (Offset=15) 74 FIFO Status MSB (Offset=10) 65 Frame 15 Ordering Information 123 General Configuration (Index=0, RB='1') 82...

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