LG 28LN45 Series Service Manual page 29

+1.5V_DDR
+1.5V_DDR
A-MVREFDQ
A-MVREFCA
CLose to Saturn7M IC
CLose to DDR3
EAN61848802
IC1201
K4B2G1646E-BCK0
DDR_2G_1600_SS
M8 N3
A-MVREFCA VREFCA A0
P7
A1
P3
A2
H1 N2
A-MVREFDQ VREFDQ A3
P8
A4
P2
R1203 A5
L8 R8
ZQ A6
R2
240
A7
+1.5V_DDR 1% T8
A8
B2 R3
VDD_1 A9
L7
D9
C1205 10uF
VDD_2 A10/AP
G7 R7
C1207 0.1uF
VDD_3 A11
K2 N7
C1208 0.1uF
VDD_4 A12/BC
K8 T3
C1210 0.1uF
VDD_5 A13
N1
C1211 0.1uF
VDD_6
N9 M7
C1212 0.1uF
VDD_7 NC_5
R1
C1213 0.1uF
VDD_8
R9 M2
C1214 0.1uF
VDD_9 BA0
N8
C1215 0.1uF
BA1
M3
C1216 0.1uF
BA2
A1
VDDQ_1
A8 J7
VDDQ_2 CK
C1 K7
VDDQ_3 CK
C9 K9
VDDQ_4 CKE
D2
VDDQ_5
E9 L2
VDDQ_6 CS
F1 K1
VDDQ_7 ODT
H2 J3
VDDQ_8 RAS
H9 K3
VDDQ_9 CAS
L3
WE
J1
NC_1
J9 T2
NC_2 RESET
L1
NC_3
L9
NC_4
T7 F3
A-MA14 NC_6 DQSL
G3
DQSL
A9 C7
VSS_1 DQSU
B3 B7
VSS_2 DQSU
E1
VSS_3
G8 E7
VSS_4 DML
J2 D3
VSS_5 DMU
J8
VSS_6
M1 E3
VSS_7 DQL0
M9 F7
VSS_8 DQL1
P1 F2
VSS_9 DQL2
P9 F8
VSS_10 DQL3
T1 H3
VSS_11 DQL4
T9 H8
VSS_12 DQL5
G2
DQL6
H7
DQL7
B1
VSSQ_1
B9 D7
VSSQ_2 DQU0
D1 C3
VSSQ_3 DQU1
D8 C8
VSSQ_4 DQU2
E2 C2
VSSQ_5 DQU3
E8 A7
VSSQ_6 DQU4
F9 A2
VSSQ_7 DQU5
G1 B8
VSSQ_8 DQU6
G9 A3
VSSQ_9 DQU7
1G 1600
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2013 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
+1.5V_DDR +1.5V_DDR
+1.5V_DDR
B-MVREFDQ
B-MVREFCA
CLose to Saturn7M IC CLose to DDR3
IC101
MSD804KKX
S7LR-M_NON_MS10
A-MA0
A11
A-MA1 A-MA0
A_DDR3_A[0]
C14
A-MA2 A-MA1 A_DDR3_A[1]
B11
A-MA3 A-MA2 A_DDR3_A[2]
F12
A-MA4 A-MA3
A_DDR3_A[3]
C15
A-MA5 A-MA4 A_DDR3_A[4]
E12
A-MA6 A-MA5
A_DDR3_A[5]
A14
A-MA7 A-MA6 A_DDR3_A[6]
D11
A-MA8 A-MA7 A_DDR3_A[7]
B14
A-MA9 A-MA8
A_DDR3_A[8]
D12
A-MA10 A-MA9 A_DDR3_A[9]
C16
A-MA11 A-MA10 A_DDR3_A[10]
C13
A-MA12 A-MA11
A_DDR3_A[11]
A15
A-MA13 A-MA12 A_DDR3_A[12]
E11
A-MA13 A_DDR3_A[13]
B13
A-MA14 A_DDR3_A[14]
A-MBA0 A-MCK
F13
A-MBA1 A-MBA0 A_DDR3_BA[0]
B15
A-MBA2 A-MBA1 A_DDR3_BA[1]
C1209 E13
A-MBA2
A_DDR3_BA[2]
0.01uF
50V C17
A-MCK A_DDR3_MCLK
A17
A-MCKE A-MCKB
A_DDR3_MCLKZ
B16
A-MCKB A-MCKE A_DDR3_MCLKE
A-MODT
E14
A-MRASB +1.5V_DDR A-MODT A_DDR3_ODT
B12
A-MCASB A-MRASB
R1231 A_DDR3_RASZ
A12
10K
A-MWEB A-MCASB A_DDR3_CASZ
C12
A-MWEB A_DDR3_WEZ
A-MRESETB
F11
A-MRESETB A_DDR3_RESET
A-MDQSL
B19
A-MDQSLB A-MDQSL A_DDR3_DQSL
C18
A-MDQSLB
A_DDR3_DQSLB
A-MDQSU
B18
A-MDQSUB A-MDQSU A_DDR3_DQSU
A18
A-MDQSUB
A_DDR3_DQSUB
A-MDML
E15
A-MDMU A-MDML A_DDR3_DQML
A21
A-MDMU A_DDR3_DQMU
A-MDQL0
D17
A-MDQL1 A-MDQL0
A_DDR3_DQL[0]
G15
A-MDQL2 A-MDQL1 A_DDR3_DQL[1]
B21
A-MDQL3 A-MDQL2 A_DDR3_DQL[2]
F15
A-MDQL4 A-MDQL3
A_DDR3_DQL[3]
B22
A-MDQL5 A-MDQL4 A_DDR3_DQL[4]
F14
A-MDQL6 A-MDQL5 A_DDR3_DQL[5]
A22
A-MDQL7 A-MDQL6
A_DDR3_DQL[6]
D15
A-MDQL7 A_DDR3_DQL[7]
A-MDQU0
G16
A-MDQU1 A-MDQU0 A_DDR3_DQU[0]
B20
A-MDQU2 A-MDQU1 A_DDR3_DQU[1]
F16
A-MDQU3 A-MDQU2
A_DDR3_DQU[2]
C21
A-MDQU4 A-MDQU3 A_DDR3_DQU[3]
E16
A-MDQU5 A-MDQU4 A_DDR3_DQU[4]
A20
A-MDQU6 A-MDQU5
A_DDR3_DQU[5]
D16
A-MDQU7 A-MDQU6 A_DDR3_DQU[6]
C20
A-MDQU7
A_DDR3_DQU[7]
DDR_1600_HYNIX_9003(DEV)
IC1202-*1
H5TQ1G63EFR-PBC
N3 M8
A0 VREFCA
P7
A1
P3
A2
N2 H1
P8 A3 VREFDQ
A4
P2
A5
R8 L8
A6 ZQ
R2
T8 A7
A8
R3 B2
A9 VDD_1
L7 D9
A10/AP VDD_2
R7 G7
N7 A11 VDD_3 K2
A12/BC VDD_4
T3 K8
NC_7 VDD_5
N1
VDD_6
M7 N9
NC_5 VDD_7 R1
VDD_8
M2 R9
BA0 VDD_9
N8
BA1
M3
BA2 A1
VDDQ_1
J7 A8
CK VDDQ_2
K7 C1
CK VDDQ_3
K9 C9
CKE VDDQ_4 D2
VDDQ_5
L2 E9
CS VDDQ_6
K1 F1
ODT VDDQ_7
J3 H2
K3 RAS VDDQ_8 H9
CAS VDDQ_9
L3
WE
J1
NC_1
T2 J9
RESET NC_2 L1
NC_3
L9
NC_4
F3 T7
DQSL NC_6
G3
DQSL
C7 A9
DQSU VSS_1
B7 B3
DQSU VSS_2
E1
E7 VSS_3 G8
DML VSS_4
D3 J2
DMU VSS_5
J8
VSS_6
E3 M1
F7 DQL0 VSS_7 M9
DQL1 VSS_8
F2 P1
DQL2 VSS_9
F8 P9
DQL3 VSS_10
H3 T1
H8 DQL4 VSS_11 T9
DQL5 VSS_12
G2
DQL6
H7
DQL7
B1
D7 VSSQ_1 B9
DQU0 VSSQ_2
C3 D1
DQU1 VSSQ_3
C8 D8
DQU2 VSSQ_4
C2 E2
A7 DQU3 VSSQ_5 E8
DQU4 VSSQ_6
A2 F9
DQU5 VSSQ_7
B8 G1
DQU6 VSSQ_8
A3 G9
DQU7 VSSQ_9
OPT
B-MA0
B-MA1
B23
B-MA0 B-MA2
B_DDR3_A[0]
D25
B_DDR3_A[1] B-MA1 B-MA3
F22
B_DDR3_A[2] B-MA2 B-MA4
G22
B-MA3 B-MA5
B_DDR3_A[3]
E24
B_DDR3_A[4] B-MA4 B-MA6
F21
B-MA5 B-MA7
B_DDR3_A[5]
E23
B_DDR3_A[6] B-MA6 B-MA8
D22
B_DDR3_A[7] B-MA7 B-MA9
D24
B-MA8 B-MA10
B_DDR3_A[8]
D21
B_DDR3_A[9] B-MA9 B-MA11
C24
B_DDR3_A[10] B-MA10 B-MA12
C25
B-MA11 B-MA13
B_DDR3_A[11]
F23
B_DDR3_A[12] B-MA12
E21
B-MA13
B_DDR3_A[13]
D23
B_DDR3_A[14] B-MA14
B-MBA0
B-MCK
B-MBA1
G20
B_DDR3_BA[0] B-MBA0 B-MBA2
F24
C1240
B_DDR3_BA[1] B-MBA1
F20
B-MBA2
B_DDR3_BA[2] 0.01uF
50V
G25
B_DDR3_MCLK B-MCK B-MCKE
G23
B-MCKB
B-MCKB
B_DDR3_MCLKZ
F25
B_DDR3_MCLKE B-MCKE
B-MODT
+1.5V_DDR B-MRASB
D20
B_DDR3_ODT B-MODT B-MCASB
B25
B-MRASB R1232 B-MWEB
B_DDR3_RASZ
B24 10K
B_DDR3_CASZ B-MCASB
A24
B_DDR3_WEZ B-MWEB B-MRESETB
E20
B_DDR3_RESET B-MRESETB
B-MDQSL
B-MDQSLB
K24
B_DDR3_DQSL B-MDQSL
K25
B-MDQSLB B-MDQSU
B_DDR3_DQSLB
B-MDQSUB
J21
B_DDR3_DQSU B-MDQSU
J20
B-MDQSUB B-MDML
B_DDR3_DQSUB
B-MDMU
H24
B_DDR3_DQML B-MDML
L20
B_DDR3_DQMU B-MDMU B-MDQL0
B-MDQL1
L23
B-MDQL0 B-MDQL2
B_DDR3_DQL[0]
J24
B_DDR3_DQL[1] B-MDQL1 B-MDQL3
L24
B_DDR3_DQL[2] B-MDQL2 B-MDQL4
J23
B-MDQL3 B-MDQL5
B_DDR3_DQL[3]
M24
B_DDR3_DQL[4] B-MDQL4 B-MDQL6
H23
B_DDR3_DQL[5] B-MDQL5 B-MDQL7
M23
B_DDR3_DQL[6] B-MDQL6
K23
B_DDR3_DQL[7] B-MDQL7 B-MDQU0
B-MDQU1
G21
B_DDR3_DQU[0] B-MDQU0 B-MDQU2
L22
B_DDR3_DQU[1] B-MDQU1 B-MDQU3
H22
B-MDQU2 B-MDQU4
B_DDR3_DQU[2]
K20
B_DDR3_DQU[3] B-MDQU3 B-MDQU5
H20
B_DDR3_DQU[4] B-MDQU4 B-MDQU6
L21
B-MDQU5 B-MDQU7
B_DDR3_DQU[5]
H21
B_DDR3_DQU[6] B-MDQU6
K21
B-MDQU7
B_DDR3_DQU[7]
2G 1600
DDR_2G_1600_HYNIX
IC1201-*4
H5TQ2G63DFR-PBC
N3 M8
P7 A0 VREFCA
A1
P3
A2
N2 H1
A3 VREFDQ
P8
P2 A4
A5
R8 L8
A6 ZQ
R2
A7
T8
R3 A8 B2
A9 VDD_1
L7 D9
A10/AP VDD_2
R7 G7
A11 VDD_3
N7 K2
T3 A12/BC VDD_4 K8
A13 VDD_5
N1
VDD_6
M7 N9
NC_5 VDD_7
R1
M2 VDD_8 R9
BA0 VDD_9
N8
BA1
M3
BA2
A1
J7 VDDQ_1 A8
CK VDDQ_2
K7 C1
CK VDDQ_3
K9 C9
CKE VDDQ_4
D2
L2 VDDQ_5 E9
CS VDDQ_6
K1 F1
ODT VDDQ_7
J3 H2
RAS VDDQ_8
K3 H9
L3 CAS VDDQ_9
WE
J1
NC_1
T2 J9
RESET NC_2
L1
NC_3 L9
NC_4
F3 T7
DQSL NC_6
G3
DQSL
C7 A9
DQSU VSS_1
B7 B3
DQSU VSS_2
E1
VSS_3
E7 G8
D3 DML VSS_4 J2
DMU VSS_5
J8
VSS_6
E3 M1
DQL0 VSS_7
F7 M9
F2 DQL1 VSS_8 P1
DQL2 VSS_9
F8 P9
DQL3 VSS_10
H3 T1
DQL4 VSS_11
H8 T9
G2 DQL5 VSS_12
DQL6
H7
DQL7
B1
VSSQ_1
D7 B9
C3 DQU0 VSSQ_2 D1
DQU1 VSSQ_3
C8 D8
DQU2 VSSQ_4
C2 E2
DQU3 VSSQ_5
A7 E8
A2 DQU4 VSSQ_6 F9
DQU5 VSSQ_7
B8 G1
DQU6 VSSQ_8
A3 G9
DQU7 VSSQ_9
EAN61836301
IC1202
K4B1G1646G-BCK0
DDR_1600_SS
N3 M8
A0 VREFCA B-MVREFCA
P7
A1
P3
A2
N2 H1
A3 VREFDQ B-MVREFDQ
P8
A4
P2
A5 R1226
R8 L8
A6 ZQ
R2
240
A7
T8 1% +1.5V_DDR
A8
R3 B2
A9 VDD_1
L7 D9 C1227 10uF
A10/AP VDD_2
R7 C1228 0.1uF
G7
A11 VDD_3
C1229 0.1uF
N7 K2
A12/BC VDD_4
T3 K8 C1230 0.1uF
A13 VDD_5
C1231 0.1uF
N1
VDD_6
M7 N9 C1232 0.1uF
NC_5 VDD_7
R1 C1233 0.1uF
VDD_8
C1234 0.1uF
M2 R9
BA0 VDD_9
N8 C1235 0.1uF
BA1
M3 C1236 0.1uF
BA2
A1
VDDQ_1
J7 A8
CK VDDQ_2
K7 C1
CK VDDQ_3
K9 C9
CKE VDDQ_4
D2
VDDQ_5
L2 E9
CS VDDQ_6
K1 F1
ODT VDDQ_7
J3 H2
RAS VDDQ_8
K3 H9
CAS VDDQ_9
L3
WE
J1
NC_1
T2 J9
RESET NC_2
L1
NC_3
L9
NC_4
F3 T7
B-MA14
DQSL NC_6
G3
DQSL
C7 A9
DQSU VSS_1
B7 B3
DQSU VSS_2
E1
VSS_3
E7 G8
DML VSS_4
D3 J2
DMU VSS_5
J8
VSS_6
E3 M1
DQL0 VSS_7
F7 M9
DQL1 VSS_8
F2 P1
DQL2 VSS_9
F8 P9
DQL3 VSS_10
H3 T1
DQL4 VSS_11
H8 T9
DQL5 VSS_12
G2
DQL6
H7
DQL7
B1
VSSQ_1
D7 B9
DQU0 VSSQ_2
C3 D1
DQU1 VSSQ_3
C8 D8
DQU2 VSSQ_4
C2 E2
DQU3 VSSQ_5
A7 E8
DQU4 VSSQ_6
A2 F9
DQU5 VSSQ_7
B8 G1
DQU6 VSSQ_8
A3 G9
DQU7 VSSQ_9
NC4_S7LRM
DDR
EAX65303801
2013.1.14
12 13
LGE Internal Use Only