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Jameco Electronics Rabbit 2000 User Manual

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Summary of Contents for Jameco Electronics Rabbit 2000

  • Page 1 Distributed by: www.Jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner.
  • Page 2 ® Rabbit 3000 Microprocessor User’s Manual 019–0108 • 040731–O...
  • Page 3 Rabbit 3000 Microprocessor User’s Manual Part Number 019-0108 • 040731–O • Printed in U.S.A. ©2002–2004 Rabbit Semiconductor • All rights reserved. Rabbit Semiconductor reserves the right to make changes and improvements to its products without providing notice. Trademarks Rabbit and Rabbit 3000 are registered trademarks of Rabbit Semiconductor. Dynamic C is a registered trademark of Z-World, Inc.

  • Page 4: Table Of Contents

    Chapter 1. Introduction 1.1 Features and Specifications Rabbit 3000...2 1.2 Summary of Rabbit 3000 Advantages ...6 1.3 Differences Rabbit 3000 vs. Rabbit 2000 ...7 Chapter 2. Rabbit 3000 Design Features 2.1 The Rabbit 8-bit Processor vs. Other Processors...10 2.2 Overview of On-Chip Peripherals and Features ...11 2.2.1 5 V Tolerant Inputs ...11...
  • Page 5 3.5 Interrupt Structure ... 44 3.5.1 Interrupt Priority ... 44 3.5.2 Multiple External Interrupting Devices ... 46 3.5.3 Privileged Instructions, Critical Sections and Semaphores ... 46 3.5.4 Critical Sections ... 47 3.5.5 Semaphores Using Bit B,(HL) ... 47 3.5.6 Computed Long Calls and Jumps ... 48 Chapter 4.
  • Page 6 8.5 Memory Bank Control Registers ...120 8.5.1 Optional A16, A19 Inversions by Segment (/CS1 Enable) ...121 8.6 Allocation of Extended Code and Data ...123 8.7 Instruction and Data Space Support...124 8.8 How the Compiler Compiles to Memory ...127 Chapter 9. Parallel Ports 9.1 Parallel Port A...130 9.2 Parallel Port B ...131 9.3 Parallel Port C ...132...
  • Page 7 Chapter 14. Rabbit 3000 Clocks 14.1 Low-Power Design... 210 Chapter 15. EMI Control 15.1 Power Supply Connections and Board Layout ... 212 15.2 Using the Clock Spectrum Spreader ... 212 Chapter 16. AC Timing Specifications 16.1 Memory Access Time ... 215 16.2 I/O Access Time...
  • Page 8 19.16 Block Move Instructions...256 19.17 Control Instructions - Jumps and Calls...257 19.18 Miscellaneous Instructions ...257 19.19 Privileged Instructions ...258 Chapter 20. Differences Rabbit vs. Z80/Z180 Instructions Chapter 21. Instructions in Alphabetical Order With Binary Encoding Appendix A. The Rabbit Programming Port A.1 Use of the Programming Port as a Diagnostic/Setup Port ...270 A.2 Alternate Programming Port ...270 A.3 Suggested Rabbit Crystal Frequencies...271...
  • Page 9 Rabbit 3000 Microprocessor...

  • Page 10: Chapter 1. Introduction

    NTRODUCTION Rabbit Semiconductor was formed expressly to design a a better microprocessor for use in small and medium-scale controllers. The first microprocessor was the Rabbit 2000. The second microprocessor, now available, is the Rabbit 3000. Rabbit microprocessor design- ers have had years of experience using Z80, Z180, and HD64180 microprocessors in small controllers.

  • Page 11: Features And Specifications Rabbit 3000

    1.1 Features and Specifications Rabbit 3000 • 128-pin LQFP package. Operating voltage 1.8 V to 3.6 V. Clock speed to 54+ MHz. All specifications are given for both industrial and commercial temperature and voltage ranges. Rabbit microprocessors are low-cost. • Industrial specifications are for 3.3 V ±10% and a temperature range from -40°C to +85°C.
  • Page 12 A Rabbit that is slaved to a master processor can operate entirely with volatile RAM, depending on the master for a cold program boot. • There are 56 parallel I/O lines (shared with serial ports). Some I/O lines are timer syn- chronized, which permits precisely timed edges and pulses to be generated under com- bined hardware and software control.
  • Page 13 • A built-in clock doubler allows ½-frequency crystals to be used. • The built-in main clock oscillator uses an external crystal or a ceramic resonator. Typical crystal or resonator frequencies are in the range of 1.8 MHz to 30 MHz. Since precision timing is available from the separate 32.768 kHz oscillator, a low-cost ceramic resonator with ½...
  • Page 14 Figure 1-1. Rabbit 3000 Block Diagram User’s Manual...

  • Page 15: Summary Of Rabbit 3000 Advantages

    1.2 Summary of Rabbit 3000 Advantages • The glueless architecture makes it is easy to design the hardware system. • There are a lot of serial ports and they can communicate very fast. • Precision pulse and edge generation is a standard feature. •...

  • Page 16: Differences Rabbit 3000 Vs. Rabbit 2000

    1.3 Differences Rabbit 3000 vs. Rabbit 2000 For the benefit of readers who are familiar with the Rabbit 2000 microprocessor the Rab- bit 3000 is contrasted with the Rabbit 2000 in the table below. Feature Maximum clock speed Maximum crystal frequency main oscillator (may be doubled internally) 32.768 kHz crystal oscillator...
  • Page 17 Feature Serial ports with support for SDLC/HDLC IrDA communications Maximum asynchronous baud rate Input capture unit Rabbit 3000 Rabbit 2000 None clock speed/8 clock speed/32 None Rabbit 3000 Microprocessor...

  • Page 18: Chapter 2. Rabbit 3000 Design Features

    Rabbit 2000. Both the Rabbit 3000 and the Rabbit 2000 follow in broad outline the instruction set and the register layout of the Z80 and Z180. Compared to the Z180 the instruction set has been augmented by a sub- stantial number of new instructions.

  • Page 19: The Rabbit 8-Bit Processor Vs. Other Processors

    2.1 The Rabbit 8-bit Processor vs. Other Processors The Rabbit 3000 processor has been designed with the objective of creating practical sys- tems to solve real world problems in an economical fashion. A cursory comparison of the Rabbit 3000 compared to other processors with similar capabilities may miss certain Rab- bit strong points.

  • Page 20: Overview Of On-Chip Peripherals And Features

    The Rabbit is an 8-bit processor with an 8-bit external data bus and an 8-bit internal data bus. Because the Rabbit makes the most of its external 8-bit bus and because it has a com- pact instruction set, its performance is as good as many 16-bit processors. We hesitate to compare the Rabbit to 32-bit processors, but there are undoubtedly occa- sions where the user can use a Rabbit instead of a 32-bit processor and save a vast amount of money.

  • Page 21: System Clock

    The ability to directly transmit a high voltage level address bit was not included in the original revision of the Rabbit 2000 processor. Serial ports A, B, C and D can be operated in the clocked serial mode. In this mode, a clock line synchronously clocks the data in or out.

  • Page 22: Parallel I/O

    2.2.5 Parallel I/O There are 56 parallel input/output lines divided among seven 8-bit ports designated A through G. Most of the port lines have alternate functions, such as serial data or chip select strobes. Parallel Ports D, E, F, and G have the capability of timer-synchronized outputs. The output registers are cascaded as shown in Figure 2-1.

  • Page 23: Slave Port

    2.2.6 Slave Port The slave port is designed to allow the Rabbit to be a slave to another processor, which could be another Rabbit. The port is shared with Parallel Port A and is a bidirectional data port. The master can read any of three registers selected via two select lines that form the register address and a read strobe that causes the register contents to be output by the port.

  • Page 24: Auxiliary I/O Bus

    2.2.7 Auxiliary I/O Bus The Rabbit 3000 instruction set supports memory access and I/O access. Memory access takes place in a 1 megabyte memory space. I/O access takes place in a 64K I/O space. In a traditional microprocessor design the same address and data lines are used for both mem- ory and I/O spaces.

  • Page 25: Input Capture Channels

    perclk perclk perclk/2 Timer A1 perclk/2 perclk/8 Timer B System Figure 2-4. Rabbit Timers A and B 2.2.9 Input Capture Channels The input capture channels are used to determine the time at which an event takes place. An event is signaled by a rising or falling edge (or optionally by either edge) on one of 16 input pins that can be selected as input for either of the two channels.

  • Page 26: Quadrature Encoder Inputs

    and stop condition, for example a rising edge could be the start condition and a falling edge the stop condition. However, optionally, the start and stop condition can be input from separate pins. The input capture channels can be used to measure the width of fast pulses. This is done by starting the counter on the first edge of the pulse and capturing the counter value on the second edge of the pulse.

  • Page 27: Spread Spectrum Clock

    length of the pulses. When the duty cycle is greater then 1/1024 the pulses are spread into groups distributed 256 counts apart in the 1024 frame. The pulse width modulation outputs can be passed through a filter and used as a 10-bit D/A converter. The outputs can also be used to directly drive devices that have intrinsic filtering such as motors or solenoids.

  • Page 28: Standard Bios

    reset pin, and to a programmable output pin that is used to signal the PC that attention is needed. With proper precautions in design and software, it is possible to use Serial Port A as both a programming port and as a user-defined serial port, although this will not be nec- essary in most cases.
  • Page 29 Rabbit 3000 Microprocessor...

  • Page 30: Chapter 3. Details On Rabbit Microprocessor Features

    3.1 Processor Registers The Rabbit’s registers are nearly identical to those of the Z180 or the Z80. The figure below shows the register layout. The XPC and IP registers are new. The EIR register is the same as the Z80 I register, and is used to point to a table of interrupt vectors for the exter- nally generated interrupts.
  • Page 31 The Rabbit (and the Z80/Z180) processor has two accumulators—the A register serves as an 8-bit accumulator for 8-bit operations such as . The 16-bit register HL regis- ter serves as an accumulator for 16-bit operations such as , which adds the 16- ADD HL,DE bit register DE to the 16-bit accumulator HL.

  • Page 32: Memory Mapping

    3.2 Memory Mapping Although the Rabbit memory mapping scheme is fairly complex, the user rarely needs to worry about it because the details are handled by the Dynamic C development system. Except for a handful of special instructions (see Section 19.5, “16-bit Load and Store 20- bit Address”.), the Rabbit instructions directly address a 64K data memory space.
  • Page 33 XPC register STACKSEG register DATASEG register SEGSIZE register Figure 3-3. Example of Memory Mapping Operation The names given to the segments in the figure are evocative of the common uses for each segment. The root segment is mapped to the base of flash memory and contains the startup code as well as other code that may happen to be stored there.
  • Page 34 the root segment or it may contain data variables. The stack segment is normally 4K long and it holds the system stack. The XPC segment is normally used to execute code that is not stored in the root segment or the data segment. Special instructions support executing code that is visible in the XPC segment.

  • Page 35: Extended Code Space

    3.2.1 Extended Code Space A crucial element of the Rabbit memory mapping scheme is the ability to execute pro- grams containing up to a megabyte of code in an efficient manner. This ability is absent in a pure 16-bit address processor, and it is poorly supported by the Z180 through its memory mapping unit.

  • Page 36: Separate I And D Space - Extending Data Memory

    than the XPC segment, can call other code in the root using short jumps and calls. Code in the XPC segment can also call code in the root using short jumps and calls. However, a long call must be used when code in the XPC segment is called. Functions located in the root have an efficiency advantage because a long call and a long return require 32 clocks to execute, but a short call and a short return require only 20 clocks to execute.
  • Page 37 fetching an instruction from memory and fetching or storing data in memory. When enabled separate I and D space make available the combined root and data segment, typi- cally 52k bytes for root code in the I space. In the D space, the root code segment part of the D space is typically used for constant data mapped to flash memory while the data seg- ment part of the D space is used for variable data mapped to RAM.

  • Page 38: Using The Stack Segment For Data Storage

    not have split I and D space and memory accesses to these segments do not distinguish between I and D space. The advantage of having more root code space is that root code executes faster because short calls using a 16 bit address are used to call it. This compares to long calls that have a 20 bit address for extended code.

  • Page 39: Practical Memory Considerations

    Stack Segment used as data window Stacks in data Data segment (RAM) Root Code (flash) Using Stack Segment for a Data Window Figure 3-7. Schemes for Data Memory Windows A third approach is to place the data and root code in RAM in the root segment, freeing the data segment to be a window to extended memory.
  • Page 40 ded applications. Some applications may require large data arrays or tables that will require additional data memory. For this purpose Dynamic C supports a type of extended data memory that allows the use of additional data memory, even extending far beyond a megabyte.

  • Page 41: Instruction Set Outline

    3.3 Instruction Set Outline “Load Immediate Data to a Register” on page 33 “Load or Store Data from or to a Constant Address” on page 33 “Load or Store Data Using an Index Register” on page 34 “Register-to-Register Move” on page 35 “Register Exchanges”...

  • Page 42: Load Immediate Data To A Register

    • Input/output instructions are now accomplished by normal memory access instructions prefixed by an op code byte to indicate access to an I/O space. There are two I/O spaces, internal peripherals and external I/O devices. Some Z80 and Z180 instructions have been deleted and are not supported by the Rabbit (see Chapter 20, “Differences Rabbit vs.

  • Page 43: Load Or Store Data Using An Index Register

    3.3.3 Load or Store Data Using an Index Register An index register is a 16-bit register, usually IX, IY, SP or HL, that is used for the address of a byte or word to be fetched from or stored to memory. Sometimes an 8-bit offset is added to the address either as a signed or unsigned number.

  • Page 44: Register-To-Register Move

    3.3.4 Register-to-Register Move Any of the 8-bit registers, A, B, C, D, E, H, and L, can be moved to any other 8-bit regis- ter, for example: LD A,c LD d,b LD e,l The alternate 8-bit registers can be a destination, for example: LD a’,c LD d’,b These instructions are unique to the Rabbit and require 2 bytes and four clocks because of...

  • Page 45: Push And Pop Instructions

    3.3.6 Push and Pop Instructions There are instructions to push and pop the 16-bit registers AF, HL, DC, BC, IX, and IY. The registers AF', HL', DE', and BC' can be popped. Popping the alternate registers is exclusive to the Rabbit, and is not allowed on the Z80 / Z180. Examples POP HL PUSH BC...
  • Page 46 instruction is a special instruction designed to help test the HL register. BOOL sets HL to the value 1 if HL is non zero, otherwise, if HL is zero its value is not changed. The flags are set according to the result. BOOL ;...
  • Page 47 instruction can also be used to perform a sign extension. ; extend sign of l to HL LD A,l ; sign to carry SBC A,a ; a is all 1’s if sign negative LD h,a ; sign extended The multiply instruction performs a signed multiply that generates a 32-bit signed result. ;...

  • Page 48: Input/Output Instructions

    3.3.8 Input/Output Instructions The Rabbit uses an entirely different scheme for accessing input/output devices. Any memory access instruction may be prefixed by one of two prefixes, one for internal I/O space and one for external I/O space. When so prefixed, the memory instruction is turned into an I/O instruction that accesses that I/O space at the I/O address specified by the 16- bit memory address used.

  • Page 49: How To Do It In Assembly Language-Tips And Tricks

    3.4 How to Do It in Assembly Language—Tips and Tricks 3.4.1 Zero HL in 4 Clocks BOOL HL ; 2 clocks, clears carry, HL is 1 or 0 RR HL ; 2 clocks, 4 total - get rid of possible 1 This sequence requires four clocks compared to six clocks for LD HL,0.

  • Page 50: Comparisons Of Integers

    3.4.4 Comparisons of Integers Unsigned integers may be compared by testing the zero and carry flags after a subtract operation. The zero flag is set if the numbers are equal. With the cleared is set if the number subtracted is less than or equal to the number it is subtracted from.
  • Page 51 Some simplifications are possible if one of the unsigned numbers being compared is a constant. Note that the carry has a reverse sense from pseudo-code in the form LD DE,(65535-B) address pointed to by 65535-B the 16-bit unsigned integer ;test for HL>B B is constant LD DE,(65535-B) ADD HL,DE...

  • Page 52: Atomic Moves From Memory To I/O Space

    A>B (!S & !V & !Z) v (S & V) A<B (S & !V) v (!S & V & !Z) A==B A>=B A<=B Another method of doing signed compare is to first map the signed integers onto unsigned integers by inverting bit 15. This is shown in Figure 3-8. Once the mapping has been per- formed by inverting bit 15 on both numbers, the comparisions can be done as if the num- bers were unsigned integers.

  • Page 53: Interrupt Structure

    3.5 Interrupt Structure When an interrupt occurs on the Rabbit, the return address is pushed on the stack, and con- trol is transferred to the address of the interrupt service routine. The address of the inter- rupt service routine has two parts: the upper byte of the address comes from a special register and the lower byte is fixed by hardware for each interrupt, as shown in Table 6-1.
  • Page 54 the same priority, this introduces interrupt latency while the next routine is waiting for the previous routine to allow more interrupts to take place. If a number of devices have inter- rupt service routines, and all interrupts are of the same priority, then pending interrupts can not take place until at least the interrupt service routine in progress is finished, or at least until it changes the interrupt priority.

  • Page 55: Multiple External Interrupting Devices

    3.5.2 Multiple External Interrupting Devices The Rabbit 3000 has two distinct external interrupt request lines. If there are more than two external causes of interrupts, then these lines must be shared between multiple devices. The interrupt line is edge-sensitive, meaning that it requests an interrupt only when a rising or falling edge, whichever is specified in the setup registers, takes place.

  • Page 56: Critical Sections

    The privileged instructions to manipulate the IP register are listed below. IPSET 0 ; shift IP left and set priority 00 in bits 1,0 IPSET 1 IPSET 2 IPSET 3 IPRES ; rotate IP right 2 bits, restoring previous priority RETI ;...

  • Page 57: Computed Long Calls And Jumps

    3.5.6 Computed Long Calls and Jumps The instruction to set the XPC is privileged to so that a computed long call or jump can be made. This would be done by the following sequence. LD xpc,a JP (HL) In this case, A has the new XPC, and HL has the new PC. This code should normally be executed in the root segment so as not to pull the memory out from under the JP (HL) instruction.

  • Page 58: Chapter 4. Rabbit Capabilities

    This chapter describes the various capabilities of the Rabbit that may not be obvious from the technical description. 4.1 Precisely Timed Output Pulses The Rabbit can output precise pulses under software control. The effect of interrupt latency is avoided because the interrupt always prepares a future pulse edge that is clocked into the output registers on the next clock.

  • Page 59: Pulse Width Modulation To Reduce Relay Power

    For example, if the driver is switched to a 75% duty cycle using pulse width modu- lation after the initial period when the relay armature is picked, the holding current will be approximately 75% of the full duty-cycle current and the power consumption will be about 56% as great. Rabbit 2000 Microprocessor...

  • Page 60: Open-Drain Outputs Used For Key Scan

    4.2 Open-Drain Outputs Used for Key Scan The Parallel Port D outputs can be individually programmed to be open drain. This is use- ful for scanning a switch matrix, as shown in Figure 4-2. A row is driven low, then the col- umns are scanned for a low input line, which indicates a key is closed.

  • Page 61: Cold Boot

    Rabbit-based microprocessor board. • If the Rabbit is used as a slave processor, the master processor can cold boot it over via the slave port. This means the slave can operate without any nonvolatile memory. Only RAM is required. Rabbit 2000 Microprocessor...

  • Page 62: The Slave Port

    4.4 The Slave Port The slave port allows a Rabbit to act as a slave to another processor, which can also be a Rabbit. The slave has to have only a processor chip, a RAM chip, and clock and reset sig- nals that can be supplied by the master.

  • Page 63: Slave Rabbit As A Protocol Uart

    A prime application for the Rabbit used as a slave is to create a 4-port UART that can also handle the details of a communication protocol. The master sends and receives messages over the slave port. Error correction, retransmission, etc., can be handled by the slave. Rabbit 2000 Microprocessor...

  • Page 64: Chapter 5. Pin Assignments And Functions

    5. P SSIGNMENTS AND UNCTIONS User’s Manual...

  • Page 65: Lqfp Package

    5.1 LQFP Package 5.1.1 Pinout Rabbit 3000 (AT56C55-IL1T, IL2T) 128-pin Low-Profile Quad Flat Pack (LQFP) 14 × 14 Body, 0.4 mm pitch Figure 5-1. Package Outline and Pin Assignments Rabbit 3000 Microprocessor...

  • Page 66: Mechanical Dimensions And Land Pattern

    5.1.2 Mechanical Dimensions and Land Pattern Figure 5-2 shows the mechanical dimensions of the Rabbit 3000 LQFP package. Figure 5-2. Mechanical Dimensions Rabbit LQFP Package User’s Manual...
  • Page 67 Figure 5-3 shows the PC board land pattern for the Rabbit 3000 chip in a 128-pin LQFP package. This land pattern is based on the IPC-SM-782 standard developed by the Surface Mount Land Patterns Committee and specified in Surface Mount Design and Land Pat- tern Standard, IPC, Northbrook, IL, 1999.

  • Page 68: Ball Grid Array Package

    5.2 Ball Grid Array Package 5.2.1 Pinout Rabbit 3000 (AT56C55-IZ1T, IZ2T) 128-pin Thin Map Ball Grid Array (TFBGA) 10 × 10 Body, 0.8 mm pitch VDDCORE VSSCORE VDDCORE VSSCORE Figure 5-4. Ball Grid Array Pinout Looking Through the Top of Package User’s Manual VSSCORE VDDCORE...

  • Page 69: Mechanical Dimensions And Land Pattern

    5.2.2 Mechanical Dimensions and Land Pattern Table 5-2. Ball and Land Size Dimensions Nominal Ball Tolerance Diameter Variation (mm) (mm) 0.35–0.25 The design considerations in Table 5-3 are based on 5 mil design rules and assume a single conductor between solder lands. Table 5-3.
  • Page 70 Figure 5-5. BGA Package Outline User’s Manual...

  • Page 71: Rabbit Pin Descriptions

    5.3 Rabbit Pin Descriptions Table 5-1 lists all the pins on the device, along with their direction, function, and pin num- ber on the package. Table 5-1. Rabbit Pin Descriptions Pin Group Pin Name Hardware CLK32K /RESET RESOUT XTALA1 XTALA2 CPU Buses ADDR[19:0] DATA[7:0]...
  • Page 72 Table 5-1. Rabbit Pin Descriptions (continued) Pin Group Pin Name I/O ports PA[7:0] I/O ports (continued) PB[7:0] PC[7:0] PD[7:0] PE[7:0] PF[7:0] PG[7:0] Power, VDDCORE processor core Power Processor I/O VDDIO Ring Power Battery VBAT Backup Ground Processor VSSCORE Core Ground Processor I/O VSSIO Ring...

  • Page 73: Bus Timing

    5.4 Bus Timing The external bus has essentially the same timing for memory cycles or I/O cycles. A mem- ory cycle begins with the chip select and the address lines. One clock later, the output enable is asserted for a read. The output data and the write enable are asserted for a write. valid Notes: Read may have no wait states.

  • Page 74: Description Of Pins With Alternate Functions

    5.5 Description of Pins with Alternate Functions Table 5-2. Pins With Alternate Functions Pin Name Output Function PA[7:0] SLAVE D[7:0], ID[7:0] SLAVEATTN, IA5 CLKA CLKB APWM3 ATXA APWM2 ATXB User’s Manual Input Function SLAVE D[7:0], ID[7:0] /ASCS /SRD /SWR CLKA CLKB ARXA ARXB...
  • Page 75 Table 5-2. Pins With Alternate Functions (continued) Pin Name Output Function PWM3 PWM2 PWM1 PWM0 CLKC CLKD APWM1 RCLKE TCLKE APWM0 RCLKF TCLKF * Introduced with Rabbit 3000A chip Input Function AQD2A AQD2B AQD1A AQD1B QD2A QD2B QD1A, CLKC QD1B, CLKD RCLKE, ARXE TCLKE, ARCLKE RCLKF, ARXF...
  • Page 76 The alternate output functions identified in Table 5-2 are configured by setting the appro- priate bits in the Paralle Port x Function Register. Table 5-3. Parallel Port x Alternate Functions Parallel Port x Function Register Bit(s) Value The corresponding port bit functions normally. The corresponding port bit carries its alternate signal as an output.

  • Page 77: Dc Characteristics

    5.6 DC Characteristics Table 5-5. Rabbit 3000 Absolute Maximum Ratings Symbol Operating Temperature Storage Temperature Maximum Input Voltage: • Oscillator Buffer Input • 5-V-tolerant I/O Maximum Operating Voltage Stresses beyond those listed in Table 5-5 may cause permanent damage. The ratings are stress ratings only, and functional operation of the Rabbit 3000 chip at these or any other conditions beyond those indicated in this section is not implied.

  • Page 78: I/O Buffer Sourcing And Sinking Limit

    5.7 I/O Buffer Sourcing and Sinking Limit Unless otherwise specified, the Rabbit I/O buffers are capable of sourcing and sinking 6.8 mA of current per pin at full AC switching speeds. The limits are related to the maxi- mum sustained current permitted by the metallization on the die. User’s Manual...
  • Page 79 Rabbit 3000 Microprocessor...

  • Page 80: Chapter 6. Rabbit Internal I/O Registers

    6. R I/O R ABBIT NTERNAL EGISTERS User’s Manual...
  • Page 81 Table 6-1. Rabbit 3000 Peripherals and Interrupt Service Vectors On-Chip Peripheral System Management Memory Management Slave Port Parallel Port A Parallel Port F Parallel Port B Parallel Port G Parallel Port C Input Capture Parallel Port D Parallel Port E External I/O Control Pulse Width Modulator Quadrature Decoder...

  • Page 82: Default Values For All The Peripheral Control Registers

    6.1 Default Values for all the Peripheral Control Registers The default values for all of the peripheral control registers are shown in Table 6-2. The registers within the CPU affected by reset are the Stack Pointer (SP), the Program Counter (PC), the IIR register, the EIR register, and the IP register.
  • Page 83 Table 6-2. Rabbit Internal I/O Registers (continued) Register Name Global Revision Register Port A Data Register Port B Data Register Port B Data Direction Register Port C Data Register Port C Function Register Port D Data Register Port D Control Register Port D Function Register Port D Drive Control Register Port D Data Direction Register...
  • Page 84 Table 6-2. Rabbit Internal I/O Registers (continued) Register Name Port E Bit 7 Register Port F Data Register Port F Control Register Port F Function Register Port F Drive Control Register Port F Data Direction Register Port G Data Register Port G Control Register Port G Function Register Port G Drive Control Register...
  • Page 85 Table 6-2. Rabbit Internal I/O Registers (continued) Register Name PWM MSB 0 Register PWM LSB 1 Register PWM MSB 1 Register PWM LSB 2 Register PWM MSB 2 Register PWM LSB 3 Register PWM MSB 3 Register Quad Decode Ctrl/Status Register Quad Decode Control Register Quad Decode Count 1 Register Quad Decode Count 2 Register...
  • Page 86 Table 6-2. Rabbit Internal I/O Registers (continued) Register Name Timer A Time Constant 5 Register Timer A Time Constant 6 Register Timer A Time Constant 7 Register Timer B Control/Status Register Timer B Control Register Timer B MSB 1 Register Timer B LSB 1 Register Timer B MSB 2 Register Timer B LSB 2 Register...
  • Page 87 Table 6-2. Rabbit Internal I/O Registers (continued) Register Name Serial Port D Address Register Serial Port D Long Stop Register Serial Port D Status Register Serial Port D Control Register Serial Port D Extended Register Serial Port E Data Register Serial Port E Address Register Serial Port E Long Stop Register Serial Port E Status Register...

  • Page 88: Chapter 7. Miscellaneous Functions

    7. M 7.1 Processor Identification Four read-only registers are provided to allow software to identify the Rabbit micropro- cessor and recognize the features and capabilities of the chip. Five bits in each of these registers are unique to each version of the chip. One register is reserved for the on-chip flash memory configuration (GROM), one register is reserved for the on-chip RAM mem- ory configuration (GRAM), one register identifies the CPU (GCPU), and the final register is reserved for revision identification (GREV).

  • Page 89: Rabbit Oscillators And Clocks

    Table 7-3. Global CPU Register Global CPU Register Bit(s) Value Program fetch as a function of the SMODE pins. (read only) Ignore the SMODE pins program fetch function. read These bits report the state of the SMODE pins. 00001 CPU identifier for this version of the chip. Table 7-4.
  • Page 90 32.768 kHz Clock The 32.768 kHz clock is primarily used to clock the on-chip real-time clock. In addition, it is also used to support remote cold boot via Serial Port A, driving the 2400 baud commu- nications used to initiate the cold boot. Another function of the 32.768 kHz oscillator is to drive the low power sleepy mode with the main oscillator shut down to reduce power.
  • Page 91 Table 7-5. Global Control/Status Register Global Control/Status Register Bit(s) Value No Reset or Watchdog Timer time-out since the last read. The Watchdog Timer timed out. These bits are cleared by a read of this register. (rd-only) This bit combination is not possible. Reset occurred.

  • Page 92: Clock Doubler

    7.3 Clock Doubler The clock doubler is provided to allow a lower frequency crystal to be used for the main oscillator and to provide an added range of clock frequency adjustability. The clock dou- bler is controlled via the Global Clock Double Register as shown in Table 7-7. Table 7-7.
  • Page 93 When the clock doubler is used and there is no subsequent division of the clock, the output clock will be asymmetric, as shown in Figure 7-2. Oscillator Oscillator delayed and inverted Doubled clock Delay time Address / CS Example Write Cycle write pulse early write pulse...
  • Page 94 variation in period on alternate clocks. This does not affect the no-wait states memory access time since two adjacent clocks are always used. However, the maximum allowed clock speed must be slightly reduced if the clock is supplied via the clock doubler. The only signals clocked on the falling edge of the clock are the memory and I/O write pulses and the early option memory output enable.

  • Page 95: Clock Spectrum Spreader

    7.4 Clock Spectrum Spreader When enabled the spectrum spreader stretches and compresses the clocks in a complex pattern that results in spreading the energy in the clock harmonics over a wide range of frequencies. The spectrum spreader has a normal and a strong setting. With either setting the peak spectral strength of the clock harmonics is reduced by approximately 15 dB for frequencies above 100 MHz.

  • Page 96: Chip Select Options For Low Power

    7.5 Chip Select Options for Low Power Some types of flash memory and RAM consume power whenever the chip select is enabled even if no signals are changing. The chip select behavior of the Rabbit 3000 can be modified to reduce unnecessary power consumption when the Rabbit 3000 is running at a reduced clock speed.
  • Page 97 When operating in the 32 kHz mode, it is also possible to further divide the clock to a fre- quency as low as 2 kHz, further reducing execution speed and current consumption. Global Power Save Control Register Bit(s) Value Self-timed chip selects are disabled. This bit combination is reserved and should not be used.
  • Page 98 clock ADDR Valid DATA MEMCSxB MEMOExB Figure 7-4. Short Chip Select Memory Read 32 kHz ADDR Valid DATA MEMCSxB MEMOExB Figure 7-5. Self-Timed Chip Select Memory Read Cycle User’s Manual Valid ~100 ns...

  • Page 99: Output Pins Clk, Status, /Wdtout, /Bufen

    7.6 Output Pins CLK, STATUS, /WDTOUT, /BUFEN Certain output pins can have alternate assignments as specified in Table 7-9. Table 7-9. Global Output Control Register (GOCR = 0x0E) Bit(s) Value CLK pin is driven with peripheral clock. CLK pin is driven with peripheral clock divided by 2. CLK pin is low.

  • Page 100: Time/Date Clock (Real-Time Clock)

    7.7 Time/Date Clock (Real-Time Clock) The time/date clock (RTC) is a 48-bit (ripple) counter that is driven by the 32.768 kHz oscillator. The RTC is a modified ripple counter composed of six separate 8-bit counters. The carries are fed into all six 8-bit counters at the same time and then ripple for 8 bits. The time for this ripple to take place is a few nanoseconds per bit, and certainly should not should not exceed 200 ns for all 8 bits, even when operating at low voltage.
  • Page 101 Table 7-10. Real-Time Clock RTCxR Data Registers Real-Time Clock x Holding Register Bit(s) Value Read The current value of the 48-bit RTC holding register is returned. Writing to the RTC0R transfers the current count of the RTC to six holding Write registers while the RTC continues counting.

  • Page 102: Watchdog Timer

    7.8 Watchdog Timer The watchdog timer is a 17-bit counter. In normal operation it is driven by the 32.768 kHz clock. When the watchdog timer reaches any of several values corresponding to a delay of from 0.25 to 2 seconds, it “times out.” When it times out, it emits a 1-clock pulse from the watchdog output pin and it resets the processor via an internal circuit.
  • Page 103 Table 7-13. Watchdog Timer Test Register (WDTTR adr = 0x09) Bit(s) Value Clock the least significant byte of the watchdog timer from the peripheral 0x51 clock. (Intended for chip test and code 0x54 below only.) Clock the most significant byte of the watchdog timer from the peripheral 0x52 clock.

  • Page 104: System Reset

    7.9 System Reset The Rabbit 3000 contains a master reset input (pin 46), which initializes everything in the device except for the Real-Time Clock (RTC). This reset is delayed until the completion of any write cycles in progress to prevent potential corruption of memory. If no write cycles are in progress the reset takes effect immediately.
  • Page 105 Table 7-14. Rabbit 3000 Reset Sequence and State of I/O Pins Pin Name Direction /RESET CLK32K RESOUT XTALA1 XTALA2 A[19:0] D[7:0] Bidirectional /WDTOUT STATUS SMODE[1:0] /CS0 /CS1 /CS2 /OE0 /OE1 /WE0 /WE1 /BUFEN /IORD /IOWR PA[7:0] Input/Output PB[7:0] Input/Output PC[7:0] PD[7:0] Input/Output PE[7:0]...

  • Page 106: Rabbit Interrupt Structure

    7.10 Rabbit Interrupt Structure An interrupt causes a call to be executed, pushing the PC on the stack and starting to exe- cute code at the interrupt vector address. The interrupt vector addresses have a fixed lower byte value for all interrupts. The upper byte is adjustable by setting the registers EIR and IIR for external and internal interrupts respectively.
  • Page 107 Table 7-15. Interrupts—Priority and Action to Clear Requests Priority Interrupt Source Highest External 1 External 0 Periodic (2 kHz) Quadrature Decoder Timer B Timer A Input Capture Slave Port Serial Port E Serial Port F Serial Port A Serial Port B Serial Port C Lowest Serial Port D...

  • Page 108: External Interrupts

    7.10.1 External Interrupts There are two external interrupts. Each interrupt has 2 input pins that can be used to trig- ger the interrupt. The inputs have a pulse catcher that can detect rising, falling or either ris- ing or falling edges. INT1A [PE1] INT1B [PE5] INT0A [PE0]...

  • Page 109: Interrupt Vectors: Int0 - Eir,0X00/Int1 - Eir,0X08

    Table 7-16. Control Registers for External Interrupts Reg Name Reg Address I0CR 10011000 I1CR 10011001 7.10.2 Interrupt Vectors: INT0 - EIR,0x00/INT1 - EIR,0x08 When it is desired to expand the number of interrupts for additional peripheral devices, the user should use the interrupt routine to dispatch interrupts to other virtual interrupt rou- tines.

  • Page 110: Bootstrap Operation

    7.11 Bootstrap Operation The device provides the option of bootstrap from any of three sources: from the Slave Port, from Serial Port A in clocked serial mode, or from Serial Port A in asynchronous mode. This is controlled by the state of the SMODE pins after reset. Bootstrap operation is disabled if (SMODE1, SMODE0) = (0, 0).
  • Page 111 Serial Port A is selected for bootstrap operation as a clocked serial port when SMODE = 10. In this case bit 7 of Parallel Port C is used for the serial data and bit 1 of Parallel Port B is used for the serial clock. Note that the serial clock must be externally supplied for boot- strap operation.

  • Page 112: Pulse Width Modulator

    7.12 Pulse Width Modulator The Pulse Width Modulator consists of a ten-bit free running counter, and four width reg- isters. Each PWM output is High for "n + 1" counts out of the 1024-clock count cycle, where "n" is the value held in the width register. The PWM output High time can option- ally be spread throughout the cycle to reduce ripple on the externally filtered PWM output.
  • Page 113 n=255, normal n=255, spread (64 counts) n=256, spread (65 counts) n=257, spread (65 counts) n=258, spread (65 counts) n=259, spread (65 counts) n=259, normal Table 7-17. PWM LSB x Register PWM LSB x Register Bit(s) Value write The least significant two bits for the Pulse Width Modulator count are stored. These bits are ignored.

  • Page 114: Input Capture

    7.13 Input Capture The two-channel Input Capture can be used to time input signals from various port pins. Each Input Capture channel consists of a sixteen-bit counter that is clocked by the output of Timer A8, and can be connected to one or two out of sixteen parallel port pins. The Input Capture channel captures the state of its counter upon either of two programmed conditions and can then generate an interrupt.
  • Page 115 Each Input Capture counter operates in one of three modes, or can be disabled. The counter is never automatically reset, but must be reset by a software command. Although it does not generate an interrupt, there is a status bit which is set when the counter over- flows (counts from 0xFFFF to 0x0000) so that software can recognize this condition.
  • Page 116 Table 7-19. Input Capture Control/Status Register Input Capture Control/Status Register Bit(s) Value These status bits (but not the interrupt enable bits) are cleared by the read of this (read) register, as is the Input Capture Interrupt. The Input Capture 2 Start condition has not occurred. (read) The Input Capture 2 Start condition has occurred.
  • Page 117 Table 7-20. Input Capture Control Register Input Capture Control Register Bit(s) Value These bits are ignored. Input Capture interrupts are disabled. Input Capture interrupt use Interrupt Priority 1. Input Capture interrupt use Interrupt Priority 2. Input Capture interrupt use Interrupt Priority 3. Table 7-21.
  • Page 118 Table 7-22. Input Capture Source x Register Input Capture Source x Register Bit(s) Value Parallel Port C used for Start condition input. Parallel Port D used for Start condition input. Parallel Port F used for Start condition input. Parallel Port G used for Start condition input. Use port bit 1 for Start condition input.

  • Page 119: Quadrature Decoder

    7.14 Quadrature Decoder The two-channel Quadrature Decoder accepts inputs, via Port F, from two external optical incremental encoder modules. Each channel of the Quadrature Decoder accepts an in- phase (I) and a quadrature-phase (Q) signal and provides 8-bit counters to track shaft rota- tion and provide interrupts when the count goes from 0x00 to 0xFF or from 0xFF to 0x00.
  • Page 120 Peri Clock Timer A10 Rejected Accepted The Quadrature Decoder generates an interrupt when the counter increments from 0xFF to 0x00 or when the counter decrements from 0x00 to 0xFF. The timing for the interrupt is shown below. Note that the status bits in the QDCSR are set coincident with the interrupt, and the interrupt (and status bits) are cleared by reading the QDCSR.
  • Page 121 Table 7-25. Quadrature Decoder Control/Status Register Quad Decode Control/Status Register Bit(s) Value Quadrature Decoder 2 did not increment from 0xFF. Quadrature Decoder 2 incremented from 0xFF to 0x00. This bit is cleared by a (read-only) read of his register. Quadrature Decoder 2 did not decrement from 0x00. Quadrature Decoder 2 decremented from 0x00 to 0xFF.
  • Page 122 Table 7-26. Quadrature Decoder Control Register Quad Decode Control Register Bit(s) Value Disable Quadrature Decoder 2 inputs. Writing a new value to these bits will not cause Quadrature Decoder 2 to increment or decrement. This bit combination is reserved and should not be used. Quadrature Decoder 2 inputs from Port F bits 3 and 2.
  • Page 123 Rabbit 3000 Microprocessor...

  • Page 124: Chapter 8. Memory Interface And Mapping

    8. M EMORY NTERFACE AND APPING 8.1 Interface for Static Memory Chips Static memory chips generally have address lines, data line, a chip select line, an output enable line and a write enable. The Rabbit 3000 has these same lines that can connect directly to a number of static memory chips.
  • Page 125 Rabbit 3000 /CS0 /CS1 /CS2 /OE0 /OE1 /WE0 /WE1 Figure 8-2. Typical Memory Chip Connection DATA LINES (8) MEMORY ADDRESS LINES (20) MEMORY STATIC FLASH STATIC Rabbit 3000 Microprocessor...

  • Page 126: Memory Mapping Overview

    8.2 Memory Mapping Overview See Section 3.2, “Memory Mapping,” for a discussion of Rabbit memory mapping. Figure 8-3 shows an overview of the Rabbit memory mapping. The task of the memory mapping unit is to accept 16-bit addresses and translate them to 20-bit addresses. The memory interface unit accepts the 20-bit addresses and generates control signals applied directly to the memory chips.
  • Page 127 Boundary SEGSIZE[4..7] Boundary SEGSIZE[0..3] STACKSEG DATASEG 16-bit address 20-bit address The memory management unit accepts a 16-bit address from the processor and translates it into a 20-bit address. The procedure to do this works as follows. 1. It is determined which segment the 16-bit address belongs to by inspecting the upper 4 bits of the address.

  • Page 128: Memory Interface Unit

    8.4 Memory Interface Unit The 20-bit memory addresses generated by the memory-mapping unit feed into the mem- ory interface unit. The memory interface unit has a separate write-only control register for each 256K quadrant of the 1M physical memory. This control register specifies how mem- ory access requests to that quadrant are to be dispatched to the memory chips connected to the Rabbit.

  • Page 129: Memory Bank Control Registers

    8.5 Memory Bank Control Registers Table 8-3 describes the operation of the four memory bank control registers. The registers are write-only. Each register controls one quadrant in the 1M address space. Table 8-3. Memory Bank Control Register x (MBxCR = 0x014 + x) Memory Bank x Control Register Bit(s) Value...

  • Page 130: Optional A16, A19 Inversions By Segment (/Cs1 Enable)

    Bit 3—Inhibits the write pulse to memory accessed in this quadrant. Useful for protecting flash mem- ory from an inadvertent write pulse, which will not actually write to the flash because it is protected by lock codes, but will temporarily disable the flash memory and crash the system if the memory is used for code.
  • Page 131 Table 8-5. MMU Expanded Code Register (MECR = 0x018) MMU Expanded Code Register Bit(s) Value These bits are ignored for write, and return zeros when read. Normal operation. For an XPC access, use MB0CR independent of A19-A18. For an XPC access, use MB1CR independent of A19-A18. For an XPC access, use MB2CR independent of A19-A18.

  • Page 132: Allocation Of Extended Code And Data

    The Breakpoint/Debug controller allows the RST 28 instruction to be used as a software breakpoint. Normally the RST 28 instruction causes a call to a particular location in mem- ory, but the operation of this instruction is modified when the breakpoint/debug feature is enabled.

  • Page 133: Instruction And Data Space Support

    8.7 Instruction and Data Space Support Instruction and Data space (I and D space) support is accomplished by optionally invert- ing address lines A16 and/or A19 when the processor accesses D space, but not inverting those lines when the processor accesses I space. The MMIDR register (see Table 8-8) is used to control this inversion.
  • Page 134 are mapped into contiguous regions of memory to create a continuous root code segment starting at the bottom of physical memory in flash. In the I space the division between the root segment and the data segment is irrelevant because the DATASEG register contains zero and the division between the segments defined by the lower 4 bits of the SEGSIZE register does not mark a division in physical memory for code space.
  • Page 135 64k+4*n Root I Space alloc consts Constant D Space Flash memory available for extended code, constant data. Figure 8-6. Use of Physical Memory Separate I & D Space Model In Figure 8-6 arrows indicate the direction in which variables and constants are allocated as the compile or assemble proceeds.

  • Page 136: How The Compiler Compiles To Memory

    8.8 How the Compiler Compiles to Memory The compiler actually generates code for root code and constants and extended code and extended constants. It allocates space for data variables, but does not generate data bits to be stored in memory. In any but the smallest programs, most of the code is compiled to extended memory.
  • Page 137 Rabbit 3000 Microprocessor...

  • Page 138: Chapter 9. Parallel Ports

    The Rabbit has seven 8-bit parallel ports designated A, B, C, D, E, F, and G. The pins used for the parallel ports are also shared with numerous other functions as shown in Table 5-2. The important properties of the ports are summarized below. •...

  • Page 139: Parallel Port A

    9.1 Parallel Port A Parallel Port A has a single read/write register: Table 9-1. Parallel Port A Registers Register Name Port A Data Register Slave Port Control Register Table 9-2. Parallel Port A Data Register Bit Functions Bit 7 Bit 6 PADR (R/W) adr = 0x030 This register should not be used if the slave port or auxiliary I/O bus is enabled.

  • Page 140: Parallel Port B

    9.2 Parallel Port B Parallel Port B, has eight pins that can programmed individually to be inputs and outputs. After reset, Parallel Port B comes up as six inputs (PB[5:0]) and two outputs (PB7 and PB6). The output value on pins PB6 and PB7 (package pins 99, 100) will be low. Table 9-3.

  • Page 141: Parallel Port C

    9.3 Parallel Port C Parallel Port C, shown in Table 9-6, has four inputs and four outputs. The even-numbered ports, PC0, PC2, PC4, and PC6, are outputs. The odd-numbered ports, PC1, PC3, PC5, and PC7, are inputs. When the data register is read, bits 1,3,5,7 return the value of the volt- age on the pin.

  • Page 142: Parallel Port D

    9.4 Parallel Port D Parallel Port D, shown in Figure 9-1, has eight pins that can be programmed individually to be inputs or outputs. When programmed as outputs, the pins can be individually selected to be open-drain outputs or standard outputs. Port D pins can be addressed by bit if desired.
  • Page 143 perclk/2 I/O Data Timer A1 Timer B1 Timer B2 perclk/2 Timer A1 Timer B1 Timer B2 Figure 9-1. Parallel Port D Block Diagram ARXA ATXA ARXB ATXB inputs Driver—optional open drain Rabbit 3000 Microprocessor...
  • Page 144 Table 9-8. Parallel Port D Register functions Bit 7 Bit 6 PDDR (R/W) adr = 0x060 out = out = PDDCR (W) open open adr = 0x066 drain drain PDFR (W) alt TXA x adr = 0x065 PDDDR (W) dir = dir = adr = 0x067 PDB0R (W)
  • Page 145 The following registers are described in Table 9-8 and in Table 9-9. • PDDR—Parallel Port D data register. Read/Write. • PDDDR—Parallel Port D data direction register. A "1" makes the corresponding pin an output. Write only. • PDDCR—Parallel Port D drive control register. A "0" makes the corresponding pin a regular output.

  • Page 146: Parallel Port E

    9.5 Parallel Port E Parallel Port E, shown in Figure 9-2, has eight I/O pins that can be individually pro- grammed as inputs or outputs. PE7 is used as the slave port chip select when the slave port is enabled. Each of the port E outputs can be configured as an I/O strobe. In addition, four of the port E lines can be used as interrupt request inputs.
  • Page 147 Table 9-10. Parallel Port E Registers Register Name Port E Data Register Port E Control Register Port E Function Register Port E Data Direction Register Port E Bit 0 Register Port E Bit 1 Register Port E Bit 2 Register Port E Bit 3 Register Port E Bit 4 Register Port E Bit 5 Register...
  • Page 148 Table 9-11. Parallel Port E Register functions Bit 7 Bit 6 PEDR (R/W) adr = 0x070 PEFR (W) alt /I7 alt /I6 adr = 0x075 PEDDR (W) dir = dir = adr = 0x077 PEB0R (W) adr = 0x078 PEB1R (W) adr = 0x079 PEB2R (W) adr = 0x07A...

  • Page 149: Parallel Port F

    9.6 Parallel Port F Parallel Port F is a byte-wide port with each bit programmable for data direction and drive. These are simple inputs and outputs controlled and reported in the Port F Data Register. As outputs, the bits of the port are buffered, with the data written to the Port F Data Regis- ter transferred to the output pins on a selected timing edge.

  • Page 150: Using Parallel Port A And Parallel Port F

    Table 9-15. Parallel Port F Control Register (adr = 0x03C) Bits 7, 6 Bits 5, 4 00—clock upper nibble on pclk/2 01—clock on timer A1 10—clock on timer B1 11—clock on timer B2 The following registers are described in Table 9-14 and in Table 9-15. •...
  • Page 151 The functionality of the Parallel Port F pins is not affected for pulse width modulation out- puts and serial clock outputs, except that the Parallel Port F function and direction regis- ters should be set up before a conflicting function on Parallel Port A is in use, since writing to these registers also writes to the Parallel Port A output register.

  • Page 152: Parallel Port G

    9.7 Parallel Port G Parallel Port G is a byte-wide port with each bit programmable for data direction and drive. These are simple inputs and outputs controlled and reported in the Port G Data Reg- ister. As outputs, the bits of the port are buffered, with the data written to the Port G Data Register transferred to the output pins on a selected timing edge.
  • Page 153 Table 9-18. Parallel Port G Control Register (adr= 0x04C) Bits 7, 6 Bits 5, 4 00—clock upper nibble on pclk/2 01—clock on timer A1 10—clock on timer B1 11—clock on timer B2 The following registers are described in Table 9-17 and in Table 9-18. •...

  • Page 154: Chapter 10. I/O Bank Control Registers

    10. I/O B The pins of Port E can be set individually to be I/O strobes. Each of the eight possible I/O strobes has a control register that controls the nature of the strobe and the number of wait states that will be inserted in the I/O bus cycle. Writes can also be suppressed for any of the strobes.
  • Page 155 Table 10-1 shows how the eight I/O bank control registers are organized. Table 10-1. I/O Bank x Control Register I/O Bank x Control Register Bit(s) Value Fifteen wait states for accesses in this bank. Seven wait states for accesses in this bank. Three wait states for accesses in this bank.
  • Page 156 The eight I/O bank control registers determine the number of I/O wait states applied to an external I/O access within the zone controlled by each register even if the associated strobes are not enabled. Note that the /IORD and /IOWR signals reflect these registers as well.
  • Page 157 Rabbit 3000 Microprocessor...

  • Page 158: Chapter 11. Timers

    There are two timers—Timer A and Timer B. Timer A is intended mainly for generating the clock for various peripherals, baud clock for the serial ports, a periodic clock for clocking Parallel Ports D and E, or for generating periodic interrupts. Timers A1–A7 are general-purpose timers, and Timers A8–A10 are dedicated to specific peripherals.

  • Page 159: Timer A

    11.1 Timer A Timer A consists of ten separate countdown timers A1–A10 as shown in Figure 11-1. Timers A1 and A2–A10 are 8-bit countdown registers as shown in Figure 11-2. The reload register can contain any number in the range from 0 to 255. The counter divides by (n+1). For example, if the reload register contains 127, then 128 pulses enter on the left before a pulse exits on the right.

  • Page 160: Timer A I/O Registers

    For seven of the counters (A1–A7), the terminal count condition is reported in a status regis- ter and can be programmed to generate an interrupt. There is one interrupt vector for Timer A and a common interrupt priority. A common status register (TACSR) has a bit for each timer that indicates if the output pulse for that timer has taken place since the last read of the status register.
  • Page 161 The following table summarizes Timer A’s capabilities. Table 11-2. Timer A Capabilities Timer Cascade from A1 from A1 from A1 from A1 from A1 from A1 The control/status register for Timer A (TACSR) is laid out as shown in Table 11-3. Table 11-3.
  • Page 162 Table 11-3. Timer A Control and Status Register (continued) Timer A Control and Status Register Bit(s) Value A4 interrupt disabled. (write) A4 interrupt enabled. A3 counter has not reached its terminal count. (read) A3 count done. This status bit is cleared by a read of this register. A3 interrupt disabled.
  • Page 163 The control register (TACR) is laid out as shown in Table 11-4. Table 11-4. Timer A Control Register Timer A Control Register Bit(s) Value Timer A7 clocked by the main Timer A clock. Timer A7 clocked by the output of Timer A1. Timer A6 clocked by the main Timer A clock.

  • Page 164: Practical Use Of Timer A

    The time constant register for each timer (TATxR) is simply an 8-bit data register holding a number between 0 and 255. This time constant will take effect the next time that the Timer A counter counts down to zero. The timer counts modulo (divide-by) n+1, where n is the programmed time constant.

  • Page 165: Timer B

    11.2 Timer B Figure 11-1 shows a block diagram of Timer B. The Timer B counter can be driven directly by perclk/2, by that clock divided by 8, or by the output of Timer A1. Timer B has a continuously running 10-bit counter. The counter is compared against two match regis- ters, the B1 match register and the B2 match register.
  • Page 166 The control/status register for Timer B (TBCSR) is laid out as shown in Table 11-7. Table 11-7. Timer B Control and Status Register Timer B Control and Status Register Bit(s) Value These bits are always read as zero. Timer B2 comparator has not encountered a match condition. Timer B2 comparator has encountered a match condition.
  • Page 167 The MSB x registers for Timer B (TBM1R/TBM2R) are laid out as shown in Table 11-9. Table 11-9. Timer B Count MSB x Registers Timer B Count MSB x Register Bit(s) Value The two MSBs of the comparae value for the Timer B comparator are stored. Write This compare value will be loaded into the actual comparator when the current compare detects a match.

  • Page 168: Using Timer B

    11.2.1 Using Timer B Normally the prescaler is set to divide perclk/2 by a number that provides a counting rate appropriate to the problem. For example, if the clock is 22.1184 MHz, then perclk/2 is 11.0592 MHz. A Timer B clock rate of 11.0592 MHz will cause a complete cycle of the 10-bit clock in 92.6 µs.
  • Page 169 Timer B can be used for various purposes. The 10-bit counter can be read to record the time at which an event takes place. If the event creates an interrupt, the timer can be read in the interrupt routine. The known time of execution of the interrupt routine can be sub- tracted.

  • Page 170: Chapter 12. Rabbit Serial Ports

    The Rabbit 3000 has 6 on-chip serial ports designated A, B, C, D, E, and F. All the ports can per- form asynchronous serial communications at high baud rates. Ports A-D can operate as clocked ports. Ports A and B can be switched to alternate pins. Ports E and F support SDLC/HDLC syn- chronous communications in addition to standard asynchronous communications.
  • Page 171 Table 12-1. Serial Port Signals (continued) Serial Port Serial Port F TCLKF RCLKF Figure 12-1 shows a block diagram of the serial ports. Timer A4 Timer A5 Timer A6 Input to timers Timer A7 perclk /2 or perclk prescaled (Timer A1) Timer A2 Timer A3 Figure 12-1.
  • Page 172 The individual serial ports are capable of operating at baud rates in excess of 500,000 bps in the asynchronous mode, and 8 times faster than that in the synchronous mode. Either 7 or 8 data bits may be transmitted and received in the asynchronous mode. The so-called "9th"...

  • Page 173: Serial Port Register Layout

    12.1 Serial Port Register Layout Figure 12-2 shows a functional block diagram of a serial port. Each serial port has a data register, a control register and a status register. Writing to the data register starts transmis- sion. The least significant bit (LSB) is always transmitted first. This is true for both asyc- nchronous and synchronous communication.
  • Page 174 The clock input to the serial port unit must be 8 or 16 (selectable) times the baud rate in the asynchronous mode and 2 times the baud rate for the clocked serial mode when the internal clock is used. Timers A2–A7 supply the input clock for Serial Ports A–F. These timers can divide the frequency by any number from 1 to 256 (see Chapter 11).

  • Page 175: Serial Port Registers

    12.2 Serial Port Registers Each serial port has 6 registers shown in the tables below. The status, control and extended registers may have somewhat different formats for different serial ports. Table 12-2. Serial Port A Registers Register Name Serial Port A Data Register Serial Port A Address Register Serial Port A Long Stop Register Serial Port A Status Register...
  • Page 176 Table 12-5. Serial Port D Registers Register Name Serial Port D Data Register Serial Port D Address Register Serial Port D Long Stop Register Serial Port D Status Register Serial Port D Control Register Serial Port D Extended Register Table 12-6. Serial Port E Registers Register Name Serial Port E Data Register Serial Port E Address Register...
  • Page 177 Table 12-8. Data Register All Ports Serial Port x Data Register Bit(s) Value Read Returns the contents of the receive buffer. Write Loads the transmit buffer with a data byte for transmission. Table 12-9. Address Register All Ports Serial Port x Address Register Bit(s) Value Returns the contents of the receive buffer.
  • Page 178 Table 12-10. Long Stop Register All Ports Serial Port x Long Stop Register Bit(s) Value Read Returns the contents of the receive buffer. Loads the transmit buffer with an address byte, marked with a “one” address bit, Write for transmission. In HDLC mode the last byte of a frame is written to this register to enable subsequent closing Flag transmission.
  • Page 179 Table 12-11. Status Register Asynchronous Mode Only (All Ports) Serial Port x Status Register Bit(s) Value The receive data register is empty—no input character is ready. There is a byte in the receive buffer. The transition from "0" to "1" sets the receiver interrupt request flip-flop.
  • Page 180 Table 12-12. Status Register Clocked Serial (Ports A-D only) Serial Port x Status Register Bit(s) Value The receive data register is empty There is a byte in the receive buffer. The serial port will request an interrupt while this bit is set. The interrupt is cleared when the receive buffer is empty. This bit is always zero in clocked serial mode.
  • Page 181 Table 12-13. Status Register HDLC Mode (Ports E and F only) Serial Port x Status Register Bit(s) Value The receive data register is empty There is a byte in the receive buffer. The serial port will request an interrupt while this bit is set. The interrupt is cleared when the receive buffer is empty. The byte in the receive buffer is data.
  • Page 182 Table 12-14. Serial Port Control Register Ports A and B Serial Port x Control Register Bit(s) Value No operation. These bits are ignored in the Async mode. In clocked serial mode, start a byte receive operation. In clocked serial mode, start a byte transmit operation. In clocked serial mode, start a byte transmit operation and a byte receive operation simultaneously.
  • Page 183 Table 12-15. Serial Port Control Register Ports C and D Serial Port x Control Register Bit(s) Value No operation. These bits are ignored in the async mode. In clocked serial mode, start a byte receive operation. In clocked serial mode, start a byte transmit operation. In clocked serial mode, start a byte transmit operation and a byte receive operation simultaneously.
  • Page 184 Table 12-16. Serial Port Control Register Ports E and F Serial Port x Control Register Bit(s) Value No operation. These bits are ignored in the Async mode. In HDLC mode, force receiver in Flag Search mode. No operation. In HDLC mode, transmit an Abort pattern. Enable the receiver input.
  • Page 185 Table 12-17. Extended Register Asynchronous Mode All Ports Serial Port x Extended Register Bit(s) Value These bits are ignored in async mode. Normal async data encoding. Enable RZI coding (3/16ths bit cell IrDA-compliant). Normal Break operation. This option should be selected when address bits are expected.
  • Page 186 Table 12-18. Extended Register Clocked Serial Mode (Ports A-D only) Serial Port x Extended Register Bit(s) Value Normal clocked serial operation. Timer synchronized clocked serial operation. Timer-synchronized clocked serial uses Timer B1. Timer-synchronized clocked serial uses Timer B2. Normal clocked serial clock polarity, inactive High. Internal or external clock. Normal clocked serial clock polarity, inactive Low.
  • Page 187 Table 12-19. Extended Register HDLC Mode (Ports E and F only) Serial Port x Extended Register Bit(s) Value NRZ data encoding for HDLC receiver and transmitter. NRZI data encoding for HDLC receiver and transmitter. Biphase-Level (Manchester) data encoding for HDLC receiver and transmitter. Biphase-Space data encoding for HDLC receiver and transmitter.

  • Page 188: Serial Port Interrupt

    12.3 Serial Port Interrupt A common interrupt vector is used for the receive and transmit interrupts. There is a sepa- rate interrupt request flip-flop for the receiver and transmitter. If either of these flip-flops is set, a serial port interrupt is requested. The flip-flops are set by a rising edge only. The flip-flops are cleared by a pulse generated by an I/O read or write operation as shown in Figure 12-3.

  • Page 189: Transmit Serial Data Timing

    12.4 Transmit Serial Data Timing On transmit, if the interrupts are enabled, an interrupt is requested when the transmit regis- ter becomes empty and, in addition, an interrupt occurs when the shift register and trans- mit register both become empty, that is, when the transmitter becomes idle. The shift register is empty when the last bit is shifted out.

  • Page 190: Receive Serial Data Timing

    12.5 Receive Serial Data Timing When the receiver is ready to receive data, a falling edge indicates that a start bit must be detected. The falling edge is detected as a different Rx input between two different clocks, the clock being 8x or 16x the baud rate. Once the start bit has been detected, data bits are sampled at the middle of each data bit and are shifted into the receive shift register.

  • Page 191: Clocked Serial Ports

    12.6 Clocked Serial Ports Ports A–D can operate in clocked mode. The data line and clock line are driven as shown in Figure 12-4. The data and clock are provided as 8-bit bursts with the LSB shifted out and/or received first. By default the transmit shift register advances on the falling edge of the clock and the receiver samples the data on the rising edge of the clock.
  • Page 192 with new incoming data. Similarly, writing the data to the SxAR register causes the trans- mitter to start a byte transmit operation, eliminating the need for the software to issue the Start Transmit command. The effect of these codes is different, depending on whether the mode is internal clock or external clock.
  • Page 193 answer its interrupts within 20 µs. There will be no slow down if the receiver can answer its interrupt within 1/2 clock or 1.25 µs. If it can answer within 1.5 clocks, or 2.75 µs, the data rate will slow to 44,444 bytes per second. If it can answer in 2.5 clocks or 6.25 µs, the data rate slows to 40,000 bytes per second.

  • Page 194: Clocked Serial Timing

    12.7 Clocked Serial Timing 12.7.1 Clocked Serial Timing With Internal Clock For synchronous serial communication, the serial clock can be either generated by the Rabbit or by an external device. The timing diagram in Figure 12-6 below can be applied to both full-duplex and half-duplex clocked serial communication where the serial clock is generated internally by the Rabbit.
  • Page 195 Figure 12-8 shows the timing relationship among data receive. Note that RxA is sampled by the rising edge of perclk CLKA (Ext.) Figure 12-8. Synchronous Serial Data Receive Timing with External Clock (Mode 00) When clocking the Rabbit externally, the maximum serial clock frequency is limited by the amount of time required to synchronize the external clock with the Rabbit we sum the maximum number of tion for each of the receive and transmit cases, then the fastest external serial clock fre-...

  • Page 196: Synchronous Communications On Ports E And F

    12.8 Synchronous Communications on Ports E and F Serial Port E and F are a dual-function serial ports that can be used in either asynchronous or HDLC mode. Four bytes of buffering are available for both receiver and transmitter to reduce interrupt overhead.
  • Page 197 the current receive frame is not needed (because it is addressed to a different station, for example) a Flag Search command is available. This command forces the receiver to ignore the incoming data stream until another Flag is received. In the transmitter, the CRC gener- ator is preset and the opening Flag is transmitted automatically after the first byte is writ- ten to the transmitter buffer, and CRC and the closing flag are transmitted after the byte that is written to the buffer through the Address Register.
  • Page 198 Serial Clock NRZ Data NRZI NRZI Biphase-Level Biphase-Space Biphase-Space Biphase-Mark Biphase-Mark data "1" "0" In HDLC mode the internal clock comes from the output of Timer A2. This timer output is divided by sixteen to form the transmit clock, and is fed to the Digital Phase-Locked Loop (DPLL) to form the receive clock.
  • Page 199 clock rate must be very small, and depends on the longest possible run of zeros in the received frame. NRZI encoding guarantees at least one transition every six bits (with the inserted zeros). Since the DPLL can adjust by two counts every bit cell, the maximum dif- ference between the sending data rate and the DPLL output clock rate is 1/48 (~2%).
  • Page 200 With NRZ and NRZI encoding all transitions occur on bit-cell boundaries and the data should be sampled in the middle of the bit cell. If a transition occurs after the expected bit- cell boundary (but before the midpoint) the DPLL needs to lengthen the count to line up the bit-cell boundaries.

  • Page 201: Serial Port Software Suggestions

    12.9 Serial Port Software Suggestions The receiver and transmitter share the same interrupt vector, but it is possible to make the receive and transmit interrupt service routines (ISRs) separate by dispatching the interrupt to either of two different routines. This is desirable to make the ISR less complex and to reduce the interrupt off time.

  • Page 202: Controlling An Rs-485 Driver And Receiver

    LD (HL),A ; 6 update the in pointer IOI LD A,(SCDR) ; 11 get data register port C, clears interrupt request IPRES ; 4 restore the interrupt priority ; 68 clocks to here ; to level before interrupt took place ;...

  • Page 203: Transmitting And Detecting A Break

    2. Clear bit 4 of the Parallel Port C function register so that the output no longer comes from the serial port. Of course, this should not be done until the transmitter is idle. A similar procedure can be used if the serial port is set up to use alternate output pins on port D.

  • Page 204: Parity, Extra Stop Bits With 7-Data-Bit Characters

    Figure 12-9 illustrates the standard asynchronous serial output patterns. data bits start bit Character with 9th bit low Character w/o 9th bit low start bit Character w. 9th bit high start bit Signal shown at output pin on processor. A “1” is high. Figure 12-9.

  • Page 205: Supporting 9Th Bit Communication Protocols

    12.9.8 Supporting 9th Bit Communication Protocols This section describes how 9th bit communication protocols work. 9th bit communication protocols are supported by processors such as the 8051 and the Z180, and by companies such as Cimentrics Technology. The data bytes have an extra 9th bit appended where a parity bit would normally be placed.
  • Page 206 the receiving interrupt service routine to detect this gap, it is suggested that dummy char- acters be transmitted to help detect the gap. This can be done in the following manner. The transmitter starts transmitting dummy characters when the first character interrupt is received.
  • Page 207 Rabbit 3000 Microprocessor...

  • Page 208: Chapter 13. Rabbit Slave Port

    When a Rabbit microprocessor is configured as a slave, Parallel Port A and certain other data lines are used as communication lines between the slave and the master. The slave unit is a Rabbit configured as a slave. The master can be another Rabbit or any other type of processor.
  • Page 209 A status register can be read by either the slave or the master. The status register has full/ empty bits for each of the six registers. A data register is considered full when it is written to by whichever side is capable of writing to it. If the same register is then read by either side it is considered to be empty.
  • Page 210 The following table explains the parameters used in Figure 13-2. Symbol Tsu(SCS) /SCS Setup Time Th(SCS) /SCS Hold Time Tsu(SA) SA Setup Time Th(SA) SA Hold Time Tw(SRD) /SRD Low Pulse Width Ten(SRD) /SRD to SD Enable Time Ta(SRD) /SRD to SD Access Time Tdis(SRD) /SRD to SD Disable Time Tsu(SRW –...
  • Page 211 Master writes SPD0R Slave writes status register Slave writes SPD0R Master writes status register Figure 13-3. Slave Port Handshaking and Interrupts Figure 13-4 shows a sample connection of two slave Rabbits to a master Rabbit. The mas- ter drives the slave reset line for both slaves and provides the main processor clock from its own clock.
  • Page 212 Master Rabbit D0–D7 /IORD /IOWR portout INT0A INT1A Reset Pulldown Figure 13-4. Typical Connection Slave Rabbit to Master Rabbit The slave port lines are shown in Figure 13-1. The function of these lines is described below. • SD0–SD7—These are bidirectional data lines, and are generally connected to the data bus of the master processor.

  • Page 213: Hardware Design Of Slave Port Interconnection

    • /SLAVEATTN—This line is set low (asserted) if the slave writes to the SPD0R register. This line is set high if the master writes anything to the slave status register. This line is usually connected to cause the master to be interrupted when it goes low. The data lines of the slave port are shared with Parallel Port A that uses the same package pins.
  • Page 214 If the user for some reason wants to depart from the suggested protocols and poll a register while waiting for the other side to write something to the register, the user should be aware that all the bits might not change at the exact same time when the result changes, and a transitional value could be read from the register where some bits have changed to the new value and others have not.

  • Page 215: Applications And Communications Protocols For Slaves

    Bits 1,0—This 2-bit field sets the priority of the slave port interrupt. The interrupt is disabled by (0,0). Table 13-3 describes the slave port status register. The status register has 6 bits that are set if the particular register is full. That means that the register has been written by the processor that can write to it but it has not been read by the processor that can read it.

  • Page 216: Master-Slave Messaging Protocol

    require a speciality processor. The slave processor can process data to perform pattern recognition or to extract a specific parameter from a data stream. 13.3.2 Master-Slave Messaging Protocol In this protocol the master sends messages to the slave and receives an acknowledgement message.
  • Page 217 for this.) Once the software is loaded into the slave, the slave can begin to perform its function. As a simple example, suppose that the slave is to be used as a four-port UART. It has the capability to send or receive characters on any of its four serial ports. Leaving aside the question of setup for parameters, such as the baud rate, we could define a protocol as fol- lows.

  • Page 218: Chapter 14. Rabbit 3000 Clocks

    14. R 3000 C ABBIT LOCKS The Rabbit 3000 normally uses two clocks, the main clock and the 32.768 kHz clock. The 32.768 kHz clock is needed for the battery-backable clock, the watchdog timer, and the cold-boot function. The main oscillator provides the run-time clock for the microproces- sor.

  • Page 219: Low-Power Design

    14.1 Low-Power Design The power consumption is proportional to the clock frequency and to the square of the operating voltage. Thus, operating at 3.3 V instead of 5 V will reduce the power consump- tion by a factor of 10.9/25, or 43% of the power required at 5 V. The clock speed is reduced proportionally to the voltage at the lower operating voltage.

  • Page 220: Chapter 15. Emi Control

    EMI or electromagnetic interference from unintentional radiation is of concern to the microprocessor system designer. One concern is passing the tests sometimes required by the U.S. Federal Communications Commission (FCC) or by the European EMC Directive. For example, in the U.S. the FCC requires that computing devices intended for use in the home or in office environments (but not industrial or medical environments) not have unintentional electromagnetic radia- tion above certain limits of field strength that depend on frequency and whether the device...

  • Page 221: Power Supply Connections And Board Layout

    15.1 Power Supply Connections and Board Layout Refer to Technical Note TN221, PC Board Layout Suggestions for the Rabbit 3000 Microprocessor, for recommendations on laying out a PC board to minmize EMI emsis- sions. 15.2 Using the Clock Spectrum Spreader The spectrum spreader is very powerful for reducing EMI because it will reduce all sources of EMI above 100 MHz that are related to the clock by about 15 dB.
  • Page 222 Table 15-1. Spread Spectrum Enable/Disable Register Global Clock Modulator 0 Register Bit(s) Value Enable normal spectrum spreading. Enable strong spectrum spreading. These bits are reserved. Table 15-2. Spread Spectrum Mode Select Global Clock Modulator 1 Register Bit(s) Value Disable the spectrum spreader. Enable the spectrum spreader.
  • Page 223 so low as to be undetectable, except perhaps for extremely weak stations. The effect of a pure harmonic on TV reception is to create a herringbone pattern created by a harmonic falling within the station’s band. If the spreader is engaged the pattern will disappear unless the station is very weak, in which case the interference will be seen as noise distrib- uted over the screen.

  • Page 224: Chapter 16. Ac Timing Specifications

    16. AC T The Rabbit 3000 processor may be operated at voltages between 1.8 V and 3.6 V, and at temperatures from –40°C to +85°C with use possible use over the extended range -55°C to +105°C. For long life it is desirable not to exceed a die temperature of 125°C. Most users will operate the Rabbit at 3.3 V.
  • Page 225 Figure 16-1 illustrates the parameters used to describe memory access time. Figure 16-1. Parameters Used to Describe Memory Access Time Table 16-2 lists the delays in gross memory access time for several values of V Table 16-2. Data and Clock Delays V Clock to Address Output Delay (ns) 30 pF...
  • Page 226 Figure 16-2 and Figure 16-3 illustrate the memory read and write cycles. The Rabbit 3000 operates at 2 clocks per bus cycle plus any wait states that might be specified. Figure 16-2. Memory Read and Write Cycles User’s Manual...
  • Page 227 The following memory read time delays were measured. Table 16-3. Memory Read Time Delays Time Delay Max. clock to address delay (T Max. clock to memory chip select delay (T Max. clock to memory read strobe delay (T Min. data setup time (T Min.
  • Page 228 Figure 16-3. Memory Read and Write Cycles—Early Output Enable and Write Enable Timing User’s Manual...
  • Page 229 Figure 16-4 illustrates the sources that create memory access time delays. address clock to address memory access output time Figure 16-4. Sources of Memory Access Time Delays The gross memory access time is 2T, where T is the clock period. To calculate the actual memory access time, subtract the clock to address output time, the data in setup time, and the clock period shortening due to the clock spectrum spreader from 2T.
  • Page 230 The required memory output enable access time is more complicated since it is affected by the clock doubler delays. The clock doubler setup register creates a nominal delay time ranging from 6 to 20 ns, resulting in a nominal clock low time ranging from 6 to 20 ns. The clock low time depends on internal delays, and is subject to variation arising from process variation, operating voltage and temperature.
  • Page 231 The following factors have to be taken into account when calculating the output enable access time required. • The gross output enable access time is T + minimum clock low time (it is assumed that the early output enable option is enabled) This is reduced by the spectrum spreader loss, the time from clock to output for the output enable signal, the data setup time, and a correction for the asymmetry of the original oscillator clock.

  • Page 232: I/O Access Time

    16.2 I/O Access Time Figure 16-6 illustrates the I/O read and write cycles. Figure 16-6. I/O Read and Write Cycles—No Extra Wait States NOTE: /IOCSx can be programmed to be active low (default) or active high. User’s Manual...
  • Page 233 The following I/O read time delays were measured. Table 16-5. I/O Read Time Delays Time Delay Max. clock to address delay (T Max. clock to memory chip select delay (T Max. clock to I/O chip select delay (T Max. clock to I/O read strobe delay (T Max.

  • Page 234: Further Discussion Of Bus And Clock Timing

    16.3 Further Discussion of Bus and Clock Timing The clock doubler is normally used, except in situations where low-frequency systems are specifically being used. The clock doubler works by oring the clock with a delayed ver- sion of itself. The nominal delay varies from 6 to 20 ns, and is settable under program con- trol.
  • Page 235 Oscillator Oscillator delayed and inverted Doubled clock Delay time 0.48P address, /CS Example Write Data out Cycle write pulse early write pulse option address, /CS Example Read output enb Cycle early output enb option Figure 16-7. Clock Doubler and Memory Timing 0.52P 0.48P 0.52P...

  • Page 236: Maximum Clock Speeds

    16.4 Maximum Clock Speeds The Rabbit 3000 is rated for a minimum clock period of 17 ns (commercial specifications) and 18 ns (industrial specifications). The commercial rating calls for a ±5% voltage varia- tion from 3.3 V and a temperature range from -40 to + 70°C. The industrial ratings stretch the voltage variation to ±10% and a temperature range from -40 to + 85°C.
  • Page 237 Example The spreader and doubler are enabled, with 8 ns nominal delay in the doubler. The high and low clock are equal to within 1 ns. This violates the duty cycle requirement by 3 ns since (clock low - clock high) can be as small as -1 ns, but the requirement is that it not be less than 2 ns.

  • Page 238: Power And Current Consumption

    16.5 Power and Current Consumption With the Rabbit 3000 it is possible to design systems that perform their task with very low power consumption. Unlike competitive processors, the Rabbit 3000 has short chip select features designed to minimize power consumption by external memories, which can easily become the dominant power consumers at low clock frequencies if not well handled.
  • Page 239 Figure 16-9. Rabbit 3000 System Current vs. Frequency at 3.3 V Figure 16-10. Rabbit 3000 System Current vs. Frequency at 3.3 V (enlarged view over 0–16 MHz range) Clock Frequency (MHz) Clock Frequency (MHz) xtal=25.80 xtal=14.74 xtal=11.05 xtal=3.68 xtal=25.80 xtal=14.74 xtal=11.05 xtal=3.68 Rabbit 3000 Microprocessor...
  • Page 240 Lowering the operating voltage will greatly reduce current consumption and power. Drop- ping to 2.7 V from 3.3 V will result in 70% current consumption and 60% of the power. Further dropping to 1.8 V will reduce current to 40% and power to 20% compared to 3.3 V. Naturally this complicates the selection of memories, especially at 1.8 V.

  • Page 241: Current Consumption Mechanisms

    16.6 Current Consumption Mechanisms The following mechanisms contribute to the current consumption of the Rabbit 3000 while it is operating. 1. A current proportional to voltage and clock frequency that results from the charging of internal and external capacitances. At 3.3 V (see (2) below) approximately 57% of the current is due to charging and 43% is due to crossover current.

  • Page 242: Sleepy Mode Current Consumption

    16.7 Sleepy Mode Current Consumption In sleepy mode the unit operates from the 32.768 kHz clock, which may be divided down to as slow as 2.048 kHz. The current consumption is given by: (µA) = 0.32 × V × f + 0.23 × V ×...

  • Page 243: Memory Current Consumption

    16.8 Memory Current Consumption Since there are many different memories available, let’s look at an example using one of the recommended flash and SRAM memories. Flash memory—SST part SST39LF512020, 256K × 8, 45 ns access time. Standby current: nil. • Static Current (chip select low): 3.5 mA @ 3.3 V •...

  • Page 244: Battery-Backed Clock Current Consumption

    16.9 Battery-Backed Clock Current Consumption When using the suggested tiny logic oscillator, the oscillator and clock consume current as shown in Figure 16-12 below. Normally a resistor is placed in the battery circuit to limit the current to about 3 µA, which results in a voltage setpoint of about 1.7 V. When operat- ing at 3.3 V in sleepy mode, the current of the oscillator and the real-time clock—about 12 µA—must be added.

  • Page 245: Reduced-Power External Main Oscillator

    16.10 Reduced-Power External Main Oscillator The circuit in Figure 16-13 can be used to generate the main clock using less power than with the built-in oscillator buffer. The power consumption is less because of the current- limiting resistors that cannot be used with the built-in buffer. The 2.2 kΩ series resistor must be reduced as the clock frequency increases, as must be the current-limiting resistors.

  • Page 246: Chapter 17. Rabbit Bios And Virtual Driver

    17. R ABBIT When a program is compiled by Dynamic C for a Rabbit target, the Virtual Driver is auto- matically incorporated into the program. Virtual Driver is the name given to some initial- ization routines and a group of services performed by the periodic interrupt. The Rabbit BIOS, software that handles startup, shutdown and various basic features of the Rabbit, is compiled to the target along with the application program.

  • Page 247: Bios Assumptions

    17.1.2 BIOS Assumptions The BIOS makes certain assumptions concerning the physical configuration of the proces- sor. Processors are expected to have RAM connected to /CS1, /WE1, and /OE1. Flash is expected to be connected to /CS0, /WE0, and /OE0. (See the Rabbit 3000 Designer’s Handbook Memory Planning chapter if you want to design a board with RAM only.) The crystal frequency is expected to be n*1.8432 MHz.
  • Page 248 gram consistency checking or because a part of the program that should be executing peri- odically is not executing and the watchdog times out. The Virtual Driver’s periodic interrupt hits the hardware watchdog timer with a 2 second time-out. If the periodic interrupt stops working, then the watchdog will time out after 2 seconds.
  • Page 249 Rabbit 3000 Microprocessor...

  • Page 250: Chapter 18. Other Rabbit Software

    18. O THER ABBIT OFTWARE 18.1 Power Management Support The power consumption and speed of operation can be throttled up and down with rough synchronism. This is done by changing the clock speed or the clock doubler. The range of control is quite wide: the speed can vary by a factor of 16 when the main clock is driving the processor.

  • Page 251: Reading And Writing I/O Registers

    18.2 Reading and Writing I/O Registers The Rabbit has two I/O spaces: internal I/O registers and external I/O registers. 18.2.1 Using Assembly Language The fastest way to read and write I/O registers in Dynamic C is to use a short segment of assembly language inserted in the C program.

  • Page 252: Shadow Registers

    18.3 Shadow Registers Many of the registers of the Rabbit’s internal I/O devices are write-only. This saves gates on the chip, making possible greater capability at lower cost. Write-only registers are eas- ier to use if a memory location, called a shadow register, is associated with each write- only register.

  • Page 253: Write-Only Registers Without Shadow Registers

    ld hl,PDDDRShadow ld de,PDDDR set 5,(hl) ; use ldd instruction for atomic transfer ioi ldd In this case, the instruction when used with an I/O prefix provides a convenient data move from a memory location to an I/O location. Importantly, the atomic operation so there is no danger that an interrupt routine could change the shadow register during the move to the PDDDR register.
  • Page 254 Two library functions are provided to read and write the real-time clock: unsigned long int read_rtc(void) void write_rtc(unsigned long int time) ; // write bits 15-46 // note: bits 0-14 and bit 47 are zeroed However, it is not intended that the real-time clock be read and written frequently. The procedure to read it is lengthy and has an uncertain execution time.
  • Page 255 Rabbit 3000 Microprocessor...

  • Page 256: Chapter 19. Rabbit Instructions

    19. R ABBIT NSTRUCTIONS Summary “Load Immediate Data” on page 250 “Load & Store to Immediate Address” on page 250 “8-bit Indexed Load and Store” on page 250 “16-bit Indexed Loads and Stores” on page 250 “16-bit Load and Store 20-bit Address” on page 251 “Register to Register Moves”...
  • Page 257 Spreadsheet Conventions ALTD (“A” Column) Symbol Key Flag ALTD selects alternate flags ALTD selects alternate flags and register ALTD selects alternate register ALTD operation is a special case IOI and IOE (“I” Column) Symbol Key Flag IOI and IOE affect source and destination IOI and IOE affect destination IOI and IOE affect source Z L/V...
  • Page 258 Symbols Rabbit Z180 Bit select: 000 = bit 0, 001 = bit 1, 010 = bit 2, 011 = bit 3, 100 = bit 4, 101 = bit 5, 110 = bit 6, 111 = bit 7 Condition code select: 00 = NZ, 01 = Z, 10 = NC, 11 = C 7-bit (signed) displacement.

  • Page 259: Load Immediate Data

    19.1 Load Immediate Data Instruction LD IX,mn LD IY,mn LD dd,mn LD r,n 19.2 Load & Store to Immediate Address Instruction LD (mn),A LD A,(mn) LD (mn),HL LD (mn),IX LD (mn),IY LD (mn),ss LD HL,(mn) LD IX,(mn) LD IY,(mn) LD dd,(mn) 19.3 8-bit Indexed Load and Store Instruction LD A,(BC)

  • Page 260: 16-Bit Load And Store 20-Bit Address

    19.5 16-bit Load and Store 20-bit Address Instruction LDP (HL),HL LDP (IX),HL LDP (IY),HL LDP HL,(HL) LDP HL,(IX) LDP HL,(IY) LDP (mn),HL LDP (mn),IX LDP (mn),IY LDP HL,(mn) LDP IX,(mn) LDP IY,(mn) Note that the instructions wrap around on a 64K page boundary. Since the tion operates on two-byte values, the second byte will wrap around and be written at the start of the page if you try to read or write across a page boundary.

  • Page 261: Exchange Instructions

    19.7 Exchange Instructions Instruction EX (SP),HL EX (SP),IX EX (SP),IY EX AF,AF’ EX DE’,HL EX DE’,HL’ EX DE,HL EX DE,HL’ EX AF,AF’ EX DE,HL’ A’ F’ H’ L’ 19.8 Stack Manipulation Instructions Instruction ADD SP,d POP IP POP IX POP IY POP zz PUSH IP PUSH IX...

  • Page 262: 8-Bit Arithmetic And Logical Ops

    ADD IY,yy ADD SP,d AND HL,DE AND IX,DE AND IY,DE BOOL HL BOOL IX BOOL IY DEC IX DEC IY DEC ss INC IX INC IY INC ss OR HL,DE OR IX,DE OR IY,DE RL DE RR DE RR HL RR IX RR IY SBC HL,ss...

  • Page 263: 8-Bit Bit Set, Reset And Test

    CP* n CP* r OR (HL) fr s * * L 0 OR (IX+d) fr s * * L 0 OR (IY+d) fr s * * L 0 OR n OR r SBC* (IX+d) fr s * * V * SBC* (IY+d) fr s * * V * SBC* A,(HL)

  • Page 264: 8-Bit Fast A Register Operations

    19.13 8-bit Fast A Register Operations Instruction RLCA RRCA 19.14 8-bit Shifts and Rotates RL, RLA RLC, RLCA RR, RRA RRC, RRCA Instruction RL (HL) RL (IX+d) RL (IY+d) RL r RLC (HL) RLC (IX+d) RLC (IY+d) RLC r RR (HL) RR (IX+d) RR (IY+d) RR r...

  • Page 265: Instruction Prefixes

    SLA r SRA (HL) SRA (IX+d) SRA (IY+d) SRA r SRL (HL) SRL (IX+d) SRL (IY+d) SRL r 19.15 Instruction Prefixes Instruction ALTD 19.16 Block Move Instructions Instruction LDDR 6+7i LDIR 6+7i If any of the block move instructions are prefixed by an I/O prefix, the destination will be in the specified I/O space.

  • Page 266: Control Instructions - Jumps And Calls

    19.17 Control Instructions - Jumps and Calls Instruction CALL mn DJNZ j JP (HL) JP (IX) JP (IY) JP f,mn JP mn JR cc,e JR e LCALL xpc,mn LJP xpc,mn LRET RET f RETI RST v 19.18 Miscellaneous Instructions Instruction IPSET 0 IPSET 1 IPSET 2...

  • Page 267: Privileged Instructions

    19.19 Privileged Instructions The privileged instructions are described in this section. Privilege means that an interrupt cannot take place between the privileged instruction and the following instruction. The three instructions below are privileged. LD SP,HL ; load the stack pointer LD SP,IY LD SP,IX The instructions to load the stack are privileged so that they can be followed by an instruc-...

  • Page 268: Chapter 20. Differences Rabbit Vs. Z80/Z180 Instructions

    20. D IFFERENCES The Rabbit is highly code compatible with the Z80 and Z180, and it is easy to port non I/O dependent code. The main areas of incompatibility are instructions that are concerned with I/O or particular hardware implementations. The more important instructions that were dropped from the Z80/Z180 are automatically simulated by an instruction sequence in the Dynamic C assembler.
  • Page 269 The following instructions use different register names. LD A,EIR LD EIR,A ; was R register LD IIR,A LD A,IIR ; was I register The following Z80/Z180 instructions have been dropped and are not supported. Alterna- tive Rabbit instructions are provided. Z80/Z180 Instructions Dropped CALL CC,ADR TST R ((HL),n)

  • Page 270: Chapter 21. Instructions In Alphabetical Order With Binary Encoding

    21. I NSTRUCTIONS IN Spreadsheet Conventions ALTD (“A” Column) Symbol Key Flag ALTD selects alternate flags ALTD selects alternate flags and register ALTD selects alternate register ALTD operation is a special case IOI and IOE (“I” Column) Symbol Key Flag IOI and IOE affect source and destination IOI and IOE affect destination IOI and IOE affect source...
  • Page 271 Symbols Rabbit Z180 Bit select: 000 = bit 0, 010 = bit 2, 100 = bit 4, 110 = bit 6, Condition code select: 00 = NZ, 01 = Z, 10 = NC, 11 = C 7-bit (signed) displacement. Expressed in two’s complement. Word register select destination: 00 = BC, 01 = DE, 10 = HL, 11 = SP Word register select alternate: 00 = BC ', 01 = DE ', 10 = HL ' 8-bit (signed) displacement added to PC.
  • Page 272 Instruction Byte 1 ADC A,(HL) 10001110 ADC A,(IX+d) 11011101 ADC A,(IY+d) 11111101 ADC A,n 11001110 ADC A,r 10001-r- ADC HL,ss 11101101 ADD A,(HL) 10000110 ADD A,(IX+d) 11011101 ADD A,(IY+d) 11111101 ADD A,n 11000110 ADD A,r 10000-r- ADD HL,ss 00ss1001 ADD IX,xx 11011101 ADD IY,yy 11111101...
  • Page 273 Instruction Byte 1 EX AF,AF' 00001000 EX DE,HL 11101011 EX DE',HL 11100011 EX DE,HL' 01110110 EX DE',HL' 01110110 11011001 INC (HL) 00110100 INC (IX+d) 11011101 INC (IY+d) 11111101 INC IX 11011101 INC IY 11111101 INC r 00-r-100 INC ss 00ss0011 ss= 00-BC, 01-DE, 10-HL, 11-SP 11011011 11010011...
  • Page 274 Instruction Byte 1 LD A,(BC) 00001010 LD A,(DE) 00011010 LD A,(mn) 00111010 LD A,EIR 11101101 LD A,IIR 11101101 LD A,XPC 11101101 LD dd,(mn) 11101101 LD dd',BC 11101101 LD dd',DE 11101101 LD dd,mn 00dd0001 LD bc,mn 00000001 LD de,mn 00010001 LD hl,mn 00100001 LD sp,mn 00110001...
  • Page 275 Instruction Byte 1 LDP HL,(HL) 11101101 LDP HL,(IX) 11011101 LDP HL,(IY) 11111101 LDP HL,(mn) 11101101 LDP IX,(mn) 11011101 LDP IY,(mn) 11111101 LJP nbr,mn 11000111 LRET 11101101 11110111 11101101 00000000 OR (HL) 10110110 OR (IX+d) 11011101 OR (IY+d) 11111101 OR HL,DE 11101100 OR IX,DE 11011101...
  • Page 276 Instruction Byte 1 RR r 11001011 00011111 RRC (HL) 11001011 RRC (IX+d) 11011101 RRC (IY+d) 11111101 RRC r 11001011 RRCA 00001111 RST v 11-v-111 SBC (IX+d) 11011101 SBC (IY+d) 11111101 SBC A,(HL) 10011110 SBC A,n 11011110 SBC A,r 10011-r- SBC HL,ss 11101101 00110111 SET b,(HL)
  • Page 277 Rabbit 3000 Microprocessor...

  • Page 278: Appendix A. The Rabbit Programming Port

    The programming port provides a standard physical and electrical interface between a Rabbit-based system and the Dynamic C programming platform. A special interface cable and converter connects a PC serial port to the programming port. The programming port is implemented by means of a 10-pin standard 2 mm connector. (Of course the user can change the physical implementation of the connector if he so desires.) With this setup the PC can communicate with the target, reset it and reboot it.

  • Page 279: Use Of The Programming Port As A Diagnostic/Setup Port

    A.1 Use of the Programming Port as a Diagnostic/Setup Port The programming port, which is already in place, can serve as a convenient communica- tions port for field setup, diagnosis or other occasional communication need (for example, as a diagnostic port). There are several ways that the port can be automatically integrated into the user’s software scheme.

  • Page 280: Suggested Rabbit Crystal Frequencies

    an asynchronous signal suitable for the PC. Since the target controls the clock for both send and receive, the data transmission proceeds at a rate controlled by the target board under development. This scheme does not allow for an interrupt, and it is not desirable to use up an external interrupt for this purpose.
  • Page 281 Table A-1. Preliminary Crystal Frequencies, Memory Access Times, and Baud Rates Crystal Doubled Frequency Frequency (MHz) (MHz) 1.8432 3.6864 3.6864 7.3728 7.3728 14.7456 9.216 18.432 11.0592 22.1184 12.9024 25.8048 14.7456 29.4912 18.432 36.864 22.1184 44.2368 25.8048 51.6096 Non-Stock Crystals 20.2752 40.5504 21.1968 42.3936...

  • Page 282: Appendix B. Rabbit 3000 Revisions

    PPENDIX Since its release, the Rabbit 3000 microprocessor has gone through one revision. The revi- sion reflects bug fixes, improvements, and the introduction of new features. All Rabbit 3000 revisions are pin-compatible, and transparently replace previous versions of the chip. The Rabbit 3000 has been supplied in the following versions.
  • Page 283 2. First revision (Rabbit 3000A)—Available in two packages and identified by IL2T for the LQFP package and IZ2T for the TFBGA package. This version began shipping in August 2003. All the bugs in the original Rabbit 3000 were fixed. The Rabbit 3000A contains a number of new features and improvements.
  • Page 284 (l) The quadrature decoder hardware can be configured to use a 10-bit counter in place of the existing 8-bit counter. (m)An option was added to alternatively multiplex PWM outputs, slave chip select (/SCS), and Serial Ports E and F transmit and receive clocks on other pins. (n) The Schmitt trigger IC normally required for the low power 32.768 kHz oscil- lator circuit is now integrated inside the Rabbit 3000A.

  • Page 285: Discussion Of Fixes And Improvements

    B.1 Discussion of Fixes and Improvements Table B-1 lists the bug fixes, improvements, and additions for the various revisions of the Rabbit 3000. Table B-1. Summary of Rabbit 3000 Improvements and Fixes Description ID Registers for version/revision identification. System/User mode. Memory protection scheme.

  • Page 286: Rabbit Internal I/O Registers

    B.1.1 Rabbit Internal I/O Registers Table B-2 summarizes the reset state of the new I/O registers added in the Rabbit 3000A revision. Table B-3 summarizes the reset state of the existing I/O registers with new features. Table B-2. Reset State of New Rabbit 3000A I/O Registers Register Name Secondary Watchdog Timer Register RAM Segment Register...
  • Page 287 Table B-2. Reset State of New Rabbit 3000A I/O Registers (continued) Register Name External Interrupt User Enable Register Timer A User Enable Register Timer B User Enable Register Serial Port A User Enable Register Serial Port B User Enable Register Serial Port C User Enable Register Serial Port D User Enable Register Serial Port E User Enable Register...
  • Page 288 Table B-3. Reset State of I/O Registers Modified in Rabbit 3000A Register Name Global Power Save Control Register Global Revision Register MMU Expanded Code Register Memory Timing Control Register Breakpoint/Debug Control Register I/O Bank 0 Control Register I/O Bank 1 Control Register I/O Bank 2 Control Register I/O Bank 3 Control Register I/O Bank 4 Control Register...

  • Page 289: Peripheral And Isr Address

    B.1.2 Peripheral and ISR Address Table B-4. Rabbit 3000 I/O Address Ranges On-Chip Peripheral System Management Memory Management Slave Port Parallel Port A Parallel Port F Parallel Port B Parallel Port G Parallel Port C Input Capture Parallel Port D Parallel Port E External I/O Control Pulse Width Modulator...
  • Page 290 Table B-4. Rabbit 3000 I/O Address Ranges and Interrupt Service Vectors (continued) (continued) On-Chip Peripheral SYSCALL instruction RST 38 instruction Secondary Watchdog Stack Limit Violation Write Protection Violation System Mode Violation User’s Manual I/O Address Range ISR Starting Address {IIR[7:1], 0, 0x60} {IIR[7:1], 0, 0x70} 0x000C {IIR[7:1], 0, 0x10}...

  • Page 291: Revision-Level Id Register

    B.1.3 Revision-Level ID Register Two read-only registers are provided to allow software to identify the Rabbit microproces- sor and recognize the features and capabilities of the chip. Five bits in each of these regis- ters are unique to each version of the chip. One register identifies the CPU (GCPU), and the other register is reserved for revision identification (GREV).

  • Page 292: System/User Mode

    B.1.4 System/User Mode By default, all of the hardware is accessible by the programmer. However, if a control bit in the Enable Dual Mode Register (EDMR) is set to one, two operating modes, System and User, become available. The System mode is just like the normal operating mode, but the User mode restricts program access to the hardware and to the System mode.

  • Page 293: Memory Protection

    B.1.5 Memory Protection The ability to inhibit writes to physical memory was added. The sixteen 64 KB physical memory blocks can be individually protected, and two of those blocks can additionally be subdivided and protected at a granularity of 4 KB. When a write is attempted, a new Priority 3 write-protection interrupt request is generated.
  • Page 294 Table B-7. Write Protect Low Register Write Protect Low Register Bit(s) Value Disable 64K write-protect for physical address 0x70000–0x7FFFF. Enable 64K write-protect for physical address 0x70000–0x7FFFF. Disable 64K write-protect for physical address 0x60000–0x6FFFF. Enable 64K write-protect for physical address 0x60000–0x6FFFF. Disable 64K write-protect for physical address 0x50000–0x5FFFF.
  • Page 295 Table B-8. Write Protect High Register Write Protect High Register Bit(s) Value Disable 64K write-protect for physical address 0xF0000–0xFFFFF. Enable 64K write-protect for physical address 0xF0000–0xFFFFF. Disable 64K write-protect for physical address 0xE0000–0xEFFFF. Enable 64K write-protect for physical address 0xE0000–0xEFFFF. Disable 64K write-protect for physical address 0xD0000–0xDFFFF.
  • Page 296 Table B-10. Write Protect Segment x Low Register Write Protect Segment x Low Register Bit(s) Value Disable 4K write-protect for address offset 0x7000–0x7FFF in WP Segment x Enable 4K write-protect for address offset 0x7000–0x7FFF in WP Segment x Disable 4K write-protect for address offset 0x6000–0x6FFF in WP Segment x Enable 4K write-protect for address offset 0x6000–0x6FFF in WP Segment x Disable 4K write-protect for address offset 0x5000–0x5FFF in WP Segment x Enable 4K write-protect for address offset 0x5000–0x5FFF in WP Segment x...
  • Page 297 Table B-11. Write Protect Segment x High Register Write Protect Segment x High Register Bit(s) Value Disable 4K write-protect for address offset 0xF000–0xFFFF in WP Segment x Enable 4K write-protect for address offset 0xF000–0xFFFF in WP Segment x Disable 4K write-protect for address offset 0xE000–0xEFFF in WP Segment x Enable 4K write-protect for address offset 0xE000–0xEFFF in WP Segment x Disable 4K write-protect for address offset 0xD000–0xDFFF in WP Segment x Enable 4K write-protect for address offset 0xD000–0xDFFF in WP Segment x...

  • Page 298: Stack Protection

    B.1.6 Stack Protection Stack overflow and underflow can now be detected. Low and high stack limits can be set on 256-byte boundaries. When a stack-relative memory access occurs within 16 bytes of these limits (or outside of them), a new Priority 3 stack violation interrupt occurs. The 16- byte buffer exists to allow stack protection even if the stack is placed against a memory segment boundary.
  • Page 299 The stack protection registers are listed in Table B-12, Table B-13, and Table B-14. Table B-12. Stack Limit Control Register Stack Limit Control Register Bit(s) Value These bits are reserved and should be written with zeros. Disable stack-limit checking. Enable stack-limit checking. Table B-13.

  • Page 300: Ram Segment Relocation

    B.1.7 RAM Segment Relocation Normally when instruction/data separation is enabled, instructions are stored in flash memory and data are stored in RAM memory. This can present a problem for the Interrupt Service Routine area, which often requires run-time modification. The RAM Segment Register (RAMSR) allows a 1, 2, or 4 KB segment of the logical memory space to be mapped as data would be mapped, even for program execution.

  • Page 301: Secondary Watchdog Timer

    B.1.8 Secondary Watchdog Timer The secondary watchdog timer (SWDT) is an eight-bit modulo n + 1 counter clocked by the 32.768 kHz clock. The timer is off by default, and is enabled by writing a 0x5F to the WDTCR. The secondary watchdog timer register (SWDTR) holds the time constant value.

  • Page 302: New Opcodes

    B.1.9 New Opcodes Eight new opcodes were added to the Rabbit 3000A. UMA and UMS allow multiply-and- add and multiply-and-subtract operations on large integers, and were added to speed up common cryptographic math used in public-key calculations. The remaining six expand the block copy operations available, especially to and from I/O addresses (internal and external).
  • Page 303 B.1.9.2 New Block Copy Opcodes The LDxR family of block move opcodes has been expanded. In the Rabbit 3000 proces- sor, block copy operations could only be done between memory addresses, or from mem- ory to an I/O address. In addition, the destination I/O address would increment (or decrement if using LDDR) after each byte, making the block copy opcodes effectively useless for repeated reads or writes to a peripheral (for example, a device on the external I/P bus).

  • Page 304: Expanded I/O Memory Addressing

    B.1.10 Expanded I/O Memory Addressing In the Rabbit 3000, only the lower 8 bits of an I/O address were decoded. To provide room for new peripherals, this was expanded to 16 bits. To ensure backwards compatibility, the processor always comes up in 8-bit I/O address mode; the 16-bit I/O address mode needs to be enabled in the MMIDR register by setting bit 7 to 1.

  • Page 305: External I/O Improvements

    B.1.11 External I/O Improvements Three new features have been added to the external I/O strobes: the ability to invert the strobe signal, the ability to shorten a read strobe by one clock, and the ability to direct a strobe to either the alternate I/O bus (if enabled) or the memory bus. The new control bits for the external I/O strobes are listed in Table B-21.

  • Page 306: Short Chip Select Timing For Writes

    B.1.12 Short Chip Select Timing for Writes The Rabbit 3000 provided the ability to produce shorter chip select strobes for reads when in a reduced-speed mode. A new feature has been added to produce short chip select strobes for writes as well, and can be controlled by the GPCSR register. The new control bit for the short chip selects are listed in Table B-22.
  • Page 307 B.1.12.1 Clock Select and Power Save Modes Table B-24 outlines the power save modes available in the Rabbit 3000A. The GCSR is shown in Table B-23 for reference. Table B-23. Global Control/Status Register Global Control/Status Register Bit(s) Value No reset or watchdog timer time-out since the last read. The watchdog timer timed out.
  • Page 308 B.1.12.2 Short Chip Select Timing When short chip selects are enabled for read cycles, the chip select signals are active only for the last part of the bus cycle. Wait states are inserted between T1 and T2, so this will have no effect on the duration of the chip select signals in this mode.
  • Page 309 o s c illa t o r c lo c k A D D R D A T A / C S x / O E x Figure B-4. Short Chip Select Timing: CLK/6, Read Operation oscillator clock ADDR DATA /CSx /OEx Figure B-5.
  • Page 310 oscillato r clock ADD R DATA /CSx /OEx Figure B-6. Short Chip Select Timing: CLK/2, Read Operation User’s Manual Valid divide -by-2 mo de...
  • Page 311 When operating from the 32 kHz oscillator, the same options are available, but the timing is somewhat different. This is illustrated in the diagrams below for the four different cases. In these case the chip selects are one clock cycle (of the 32 kHz clock) long. 32KHz 32 kHz clock...
  • Page 312 32 kHz clock ADD R DAT A /CSx /O Ex Figure B-9. Short Chip Select Timing: 8 kHz, Read Operation 32 kHz clock ADD R DATA /CSx /OEx Figure B-10. Short Chip Select Timing: 16 kHz, Read Operation User’s Manual Valid 8 kHz ope ratio n Valid...
  • Page 313 32 kHz clock ADD R DATA /CSx /OEx Figure B-11. Short Chip Select Timing: 32 kHz, Read Operation Valid 32 kHz operatio n Rabbit 3000 Microprocessor...
  • Page 314 In the case of write cycles, the chip select signals are active only around the trailing edge of the write signal. Wait states are inserted between T1 and T2, and this will have no effect on the duration of the chip select signals in this mode. The timing diagrams below illus- trate the actual timing for the different divided cases.
  • Page 315 oscillator clock ADDR Valid DATA /CSx /WEx Figure B-13. Short Chip Select Timing: CLK/6, Write Operation o s c illa t o r c lo c k A D D R D A T A /C S x /W E x Figure B-14.
  • Page 316 oscillator clock ADDR DATA /CSx /WEx Figure B-15. Short Chip Select Timing: CLK/2, Write Operation User’s Manual Valid divide-by-2 mode...
  • Page 317 The timing diagrams below illustrate the actual timing for the 32KHz cases of write cycles. In these cases the chip selects are active for one clock cycle before and one clock cycle after the trailing edge of the write signal. 32 kHz 32KHz clock...
  • Page 318 32 kHz clock ADDR DATA /CSx /WEx Figure B-18. Short Chip Select Timing: 8 kHz, Write Operation 32 kHz clock ADDR DATA /CSx /WEx Figure B-19. Short Chip Select Timing: 16 kHz, Write Operation User’s Manual Valid 8 kHz operation Valid 16 kHz operation...
  • Page 319 32 kHz clock ADDR DATA /CSx /WEx Figure B-20. Short Chip Select Timing: 32 kHz, Write Operation Valid 32 kHz operation Rabbit 3000 Microprocessor...

  • Page 320: Pulse Width Modulator Improvements

    B.1.13 Pulse Width Modulator Improvements Several new features have been added to the pulse width modulator. First, a new PWM interrupt can be set up to be requested on every PWM cycle, every other cycle, every fourth cycle, or every eighth cycle. The setup for this interrupt is done in the PWL0R and PWL1R registers, listed in Table B-25 and Table B-26.
  • Page 321 Table B-25. PWM LSB 0 Register PWM LSB 0 Register Bit(s) Value write The least significant two bits for the Pulse Width Modulator count are stored. Normal PWM operation. Suppress PWM output seven out of eight iterations of PWM counter. Suppress PWM output three out of four iterations of PWM counter.
  • Page 322 Table B-27. PWM LSB 2 and 3 Registers PWM LSB x Register Bit(s) Value write The least significant two bits for the Pulse Width Modulator count are stored. Normal PWM operation. Suppress PWM output seven out of eight iterations of PWM counter. Suppress PWM output three out of four iterations of PWM counter.

  • Page 323: Quadrature Decoder Improvements

    B.1.14 Quadrature Decoder Improvements The quadrature decoder counters can now be expanded to 10 bits instead of 8 bits. This is controlled by bit 5 in QDCR, listed in Table B-28. The additional two bits can be read in the QDCxHR registers, listed in Table B-29. NOTE: Bit 5 of QDCR was always written with a zero in the original Rabbit 3000 chip.
  • Page 324 I input Q input Cnt (8 bit) Cnt (10 bit) 000 001 002 003 004 005 006 007 008 007 006 005 004 003 002 001 000 3FF Interrupt Figure B-22. Quadrature Decode, 8-bit and 10-bit Counter Timing User’s Manual...

  • Page 325: Pins With Alternate Functions

    B.2 Pins with Alternate Functions The Rabbit 3000A provides greater flexibility for multiplexing I/O functions to other pins. The following alternate connections were introduced in the Rabbit 3000A for these peripherals, and are indicated by an asterisk in Table 5-2. •...

  • Page 326: Appendix C. System/User Mode

    PPENDIX The Rabbit 3000A is the first Rabbit microprocessor to incorporate a “system/user mode.” The purpose of the System/User mode is to provide two tiers of control in the CPU: sys- tem, which provides full access to all processor resources; and user, a more restricted mode.

  • Page 327: System/User Mode Opcodes

    C.1 System/User Mode Opcodes Seven new opcodes have been added to support the System/User mode, and are listed in Table C-2. All but IDET are placed in previously empty opcode table assignments. IDET shares the value of in the opcode table, and will perform that operation when the LD E,E System/User mode is disabled, or when it is enabled and in the System mode.

  • Page 328: System/User Mode Registers

    C.2 System/User Mode Registers Table C-3 lists the new I/O registers added to support the System/User mode. The Enable Dual Mode Register (EDMR) is used to enable and disable the System/User mode. All other I/O registers listed in the table are “User mode enable” registers for each peripheral.
  • Page 329 The I/O banks on Port E (enabled for the User mode by IBUER) have a slightly different operation in the User mode. Disabling user access to a given I/O bank not only causes writes to the corresponding IBxCR register to be ignored in the User mode, but also inhib- its the strobe associated with that I/O bank.

  • Page 330: Interrupts

    C.3 Interrupts When enabled for User mode access, a peripheral interrupt (if it is capable of generating an interrupt) can only be requested at Interrupt Priority Level -2 or -1. Interrupts (and ) all enter the System mode automatically. There will be times, however, that SYSCALL an interrupt should be handled in the User mode.

  • Page 331: Peripheral Interrupt Prioritization

    C.3.1 Peripheral Interrupt Prioritization Most interrupts can be programmed to occur at any of three priority levels, but several are restricted to Level 3 (the highest priority) only. The interrupts restricted to Level 3 are sys- tem mode violation, stack limit violation, write protection violation, and the secondary watchdog.
  • Page 332 Table C-5. Interrupts—Priority and Action to Clear Requests Priority Interrupt Source Highest System Mode Violation Stack Limit Violation Write Protection Violation Secondary Watchdog External 1 External 0 Periodic (2 kHz) Quadrature Decoder Timer B Timer A Input Capture Slave Port Serial Port E Serial Port F Serial Port A...

  • Page 333: Using The System/User Mode

    C.4 Using the System/User Mode The System/User mode is designed to work with new features in the Rabbit 3000A (memory protection, stack protection, etc.) to provide a seamless framework for protection of critical code. However, there are many levels at which the System/User mode can be used;...

  • Page 334: Mixed System/User Mode Operation

    C.4.2 Mixed System/User Mode Operation This mode is similar to the previous mode, but with some portions of the program written for the System mode—for example, peripheral interrupts where latency is critical. By keeping the System mode code sections small, potential system crashes are still mini- mized.

  • Page 335: Complete Operating System

    C.4.3 Complete Operating System This section describes a “full” use of the System/User mode—separating all common functions into a System mode “operating system” while letting the application-specific code run in the User mode.By default, the System mode handles all peripherals and inter- rupts, as well as high-level interfaces such as a flash file system.

  • Page 336: Appendix D. Rabbit 3000A Internal I/O Registers

    3000A I ABBIT Table D-1 provides a list of all the Rabbit 3000A internal I/O registers. Table D-1. Rabbit 3000A Internal I/O Registers Register Name Global Control/Status Register Real Time Clock Control Register Real Time Clock Byte 0 Register Real Time Clock Byte 1 Register Real Time Clock Byte 2 Register Real Time Clock Byte 3 Register Real Time Clock Byte 4 Register...
  • Page 337 Table D-1. Rabbit 3000A Internal I/O Registers (continued) Register Name Memory Bank 0 Control Register Memory Bank 1 Control Register Memory Bank 2 Control Register Memory Bank 3 Control Register MMU Expanded Code Register Memory Timing Control Register Breakpoint/Debug Control Register RAM Segment Register Write Protect Control Register Stack Limit Control Register...
  • Page 338 Table D-1. Rabbit 3000A Internal I/O Registers (continued) Register Name I/O Bank User Enable Register PWM User Enable Register Quad Decode User Enable Register External Interrupt User Enable Register Timer A User Enable Register Timer B User Enable Register Serial Port A User Enable Register Serial Port E User Enable Register Serial Port B User Enable Register Serial Port F User Enable Register...
  • Page 339 Table D-1. Rabbit 3000A Internal I/O Registers (continued) Register Name Port D Bit 2 Register Port D Bit 3 Register Port D Bit 4 Register Port D Bit 5 Register Port D Bit 6 Register Port D Bit 7 Register Port E Data Register Port E Control Register Port E Function Register...
  • Page 340 Table D-1. Rabbit 3000A Internal I/O Registers (continued) Register Name I/O Bank 2 Control Register I/O Bank 3 Control Register I/O Bank 4 Control Register I/O Bank 5 Control Register I/O Bank 6 Control Register I/O Bank 7 Control Register PWM LSB 0 Register PWM MSB 0 Register PWM LSB 1 Register...
  • Page 341 Table D-1. Rabbit 3000A Internal I/O Registers (continued) Register Name Interrupt 0 Control Register Interrupt 1 Control Register Timer A Control/Status Register Timer A Prescale Register Timer A Time Constant 1 Register Timer A Control Register Timer A Time Constant 2 Register Timer A Time Constant 8 Register Timer A Time Constant 3 Register Timer A Time Constant 9 Register...
  • Page 342 Table D-1. Rabbit 3000A Internal I/O Registers (continued) Register Name Serial Port B Address Register Serial Port B Long Stop Register Serial Port B Status Register Serial Port B Control Register Serial Port B Extended Register Serial Port C Data Register Serial Port C Address Register Serial Port C Long Stop Register Serial Port C Status Register...
  • Page 343 Rabbit 3000 Microprocessor...

  • Page 344: Notice To Users

    OTICE TO SERS RABBIT SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COM- PONENTS IN LIFE-SUPPORT DEVICES OR SYSTEMS UNLESS A SPECIFIC WRITTEN AGREE- MENT REGARDING SUCH INTENDED USE IS ENTERED INTO BETWEEN THE CUSTOMER AND RABBIT SEMICONDUCTOR PRIOR TO USE. Life-support devices or systems are devices or systems intended for surgical implantation into the body or to sustain life, and whose failure to perform, when prop- erly used in accordance with instructions for use provided in the labeling and user’s manual, can be reason- ably expected to result in significant injury.

  • Page 346: Index

    ... 80, 86, 212, 225 timer and clock use ... 244 timing issues ... 225, 226 cold boot ... 52 comparison Rabbit 3000 vs. Rabbit 2000 ... 259 compiler ... 127 crystal frequencies ... 271 User’s Manual design features ... 9 5 V tolerant inputs ...
  • Page 347 PWM modulator ...103, 311 PWM outputs ...17, 50 quadrature decoder ...110 quadrature encoder inputs ...17 Rabbit 3000 block diagram ...5 comparison with Rabbit 2000 ...259 crystal frequencies ...271 design features ...9 features ...1 list of advantages ...6 on-chip peripherals ...11 programing port ...269...
  • Page 348 PDDDR ... 133 PDDR ... 133, 135 PDFR ... 133 PEBxR ... 138 PECR ... 138, 139 PEDDR ... 138 PEDR ... 138, 139 PEFR ... 138 PFCR ... 140, 141 PFDCR ... 140 PFDDR ... 140 PFDR ... 140 PFFR ...
  • Page 349 secondary watchdog timer ..292 serial ports ...11, 161 9th bit protocols ...196 address registers ...168 baud rates ...163 breaks ...194 clocked serial ports (Ports A– D) ...182 clocked serial timing ...185 control registers (Ports A–B) ...173 control registers (Ports C–D) ...174 control registers (Ports E–F) ...175...

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